JPS62138940A - Register access control system - Google Patents

Abstract

PURPOSE:To increase a reading access processing capacity by providing two pairs of a storage device to constitute the register group of the same constitution, writing the same data in parallel in the writing and executing respectively independently both individual accesses in the reading. CONSTITUTION:The mechanism to write such as the writing side of two pairs of load mechanisms L1 and L2 and an arithmetic mechanism E1 to a mask register 10 is in the same way connected to both storage devices 11 and 12, and the contents of the storage devices 11 and 12 are always coincident. Concerning the reading access, the access requester is suitably distributed to the storage devices 11 and 12, and respective requesters use either of the storage devices. Thus, the data of the same bank can be simultaneously read from the storage devices 11 and 12, in the reading cycle, the double number of the cycle can be used, and therefore, the number to be able to execute the parallel processing can be increased.

Description

[Detailed Description of the Invention] [Summary] This is a control method for increasing the number of parallel accesses to registers of a vector processing device, etc.

Two sets of storage devices forming register groups with the same configuration are provided,
During writing, by writing the same data to the re-storage device in parallel, the contents of the re-storage device are always made to match.
In reading, both accesses are configured to be executed independently. As described above, it is possible to increase the processing capacity of read access and improve the performance of the processing device.

[Industrial application field]

The present invention relates to a method for controlling access to registers in a vector processing device or the like of a computer system.

A vector processing device is a processing device that speeds up operations on array data by continuously processing operations using a so-called pipeline control method.

Therefore, in a vector processing device, operand data and control data must be supplied from registers at a sufficient speed so that the pipeline can operate efficiently.

[Prior art and problems to be solved by the invention] FIG. 3 is a block diagram showing an example of the configuration of a mask register in a vector processing device or the like.

As is well known, the mask register of a vector processing device is a register that holds mask bits, which are control bits provided corresponding to element data, in order to control the extraction of element data of an array to be operated on. , are accessed in synchronization with operations on the data held in a known vector register (not shown).

To this end, as shown in FIG. 3, the mask register 1 is divided into multiple banks 2, the same number as the vector registers (8 banks in the example shown), and different banks 2 are made to be accessible simultaneously, allowing multiple access to be able to run in parallel.

Further, the addresses of the mask register 1 are assigned in a so-called interleaved manner, in which they are arranged in the order of bank 0, bank 1, bank 2, etc., and with this configuration,
Starting from a predetermined timing, multiple access sources can sequentially access successive addresses through successive access cycles.

The pipeline mechanism, which is the mechanism that requests access to the mask register 1, includes a load mechanism (referred to as a The same applies hereafter) and a store mechanism (STυ, a mask operation mechanism (M) for performing operations between mask bits and writing the result into a mask register l, and a mask operation mechanism (M) for performing operations between mask bits and writing the result to a mask register l, and supplying mask bits horizontally to multiple data operations m, or for data operations There are access request mechanisms, such as various arithmetic mechanisms (El, El), for writing outputs from the mechanisms into mask registers.

They are connected by a switch 3.4 to the mask register 1 as shown in FIG.
Any one of the banks can be accessed, and 8 banks can be accessed in a total of 8 cycles.

The numbers on the lines of each bank in the figure indicate the bank number of the access destination, with R indicating read access and W indicating write access.

In such a control system, if there is a mechanism for requesting access as in this example, as is clear from FIG.
Banks allow access requests for up to five mechanisms to be processed in parallel.

Therefore, in order to support even more parallel processing, the number of banks of vector registers and mask registers l must be increased,
In addition, there was a problem in that major changes had to be made that affected the entire processing device, such as shortening the control cycle time.

[Means for solving problems]

FIG. 1 is a block diagram showing the configuration of the present invention.

The figure shows an example of a mask register, and the mask register 10 is composed of two sets of storage devices 11 and 12 having the same configuration.

[For production]

For example, the load mechanism of 2'fFJi, L2 and the mechanism that writes to the mask register, such as the write side of the arithmetic unit E1, are connected in the same way to both storage devices 11 and 12, and the same cycle is performed on both storage devices 11 and 12. .12, and when writing is performed, the same data is written to registers at the same address in storage devices 11 and 12 at the same time. As a result, the contents of storage devices 11 and 12 always match.

For read access to the mask register 10, access request sources are appropriately allocated to the storage devices 11 and 12, and each request source is configured to use one of the memory locations.

In this way, data of the same hunk can be stored in storage devices 11 and 12.
Since it becomes possible to simultaneously read data from and double the number of read cycles, it is possible to increase the number of possible parallel processes. In addition, by maintaining each configuration of the storage device 1112 in the same manner as before, the influence on vector registers and other systems of the processing device can be minimized.

〔Example〕

In FIG. 1, it is assumed that the storage devices 11 and 12 each have the same configuration as the conventional mask register 1, and are configured so that eight banks can be accessed in parallel.

For the mask register 10, in addition to the conventional access mechanisms ST, , M, E, , E, a load mechanism L2 is used.
, store mechanism ST, and calculation mechanisms E3 and E4 are added, and as shown in FIG. The write side interface is connected to both storage devices IL 12 in parallel.

In this way, each storage device 11, 12 can be accessed by allocating control cycles, for example as shown in FIG. As is clear from the figure, parallel access by a total of nine access request mechanisms can be realized by the eight bank configuration.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, it is possible to increase the number of parallel accessible mask registers, etc. of a vector processing device by adding a relatively small-scale circuit by installing the registers in parallel. , it has a remarkable industrial effect of improving the performance-price ratio of processing equipment, etc.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a timing explanatory diagram of the present invention, FIG. 3 is a block diagram of a conventional configuration example, and FIG. 4 is a conventional timing diagram. In the figure, 1.10 is a mask register, 2 is a bank, 3.4.13.14.15.16 is a switch, 11.12
are storage devices; Ll, L2, ST+, STz, E+, Ez are access request mechanisms; Figure 3 Conventional timing explanatory diagram

Claims (1)

[Claims] A storage device consisting of a plurality of banks and configuring a plurality of registers specified by addresses interleaved between the banks, and a plurality of storage devices connected so as to access the storage device at a predetermined timing. In a processing device having access sources of Equipment (11, 1
2) in parallel, and for each access source, all the storage devices (11, 12
) and assign a common write timing to the required access sources (ST_1, ST_2, E_1, E_2, E_
3, E_4, M) are connected to any one storage device (11, 12), respectively, and each access source is connected to each storage device (11, 12) for each access source.
) is a register access control method characterized by allocating individual read timings for each register.