JP4240610B2 - Computer system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a computer system having a multi-bank main memory device, and more particularly to a computer system that performs main memory skew.
[0002]
[Prior art]
As a configuration method of a main storage device of a computer system, an interleaving method composed of a large number of banks is known. FIG. 2 shows allocation of addresses by the interleave method when the number of banks constituting the main storage device is 16. The 16 banks are numbered sequentially from 0 to 15, and consecutive addresses are assigned to different banks in sequence. In this interleaving method, when sequentially accessing consecutive addresses, different banks are sequentially accessed, so that high-speed main memory access is possible. However, there is a known problem that when access is made at a specific address interval (stride), the access is concentrated in a specific bank or bank group, and the main memory access performance is lowered. For example, in the address allocation of FIG. 2, consider a case where access is made with a stride 16 starting from address 0. At this time, addresses 0, 16, 32, 48,... Are accessed, but since these addresses are all assigned to bank 0, high-speed main memory access becomes impossible due to bank conflicts. FIG. 3 shows the relationship between the stride and the distribution of access requests to the banks. If access requests are distributed to more banks, bank contention can be avoided and high main memory processing performance can be obtained.
[0003]
The address here refers to the number assigned to the memory location of each access unit of the memory. Hereinafter, unless otherwise specified, the address definition in this specification is as described above.
[0004]
Main memory skew is known as a means for alleviating the degradation in access request processing performance of the main storage device. The main memory skew is DJ Kuck: “ILLIAC IV Software and Application Programming”, IEEE Transactions on Computers, Vol. C-17, No. 8, pp. 758-770, August 1968 or P. Budnik and DJ Kuck: “The Mathematical foundation is given in "Organization and Use of Parallel Memories", IEEE Transactions on Computers, pp. 1566-1569, December 1971. There are various variations of the method, some of which are DT Harper III and JR Jump: “Vector Access Performance in Parallel Memories Using a Skewed Storage Scheme”, IEEE Transactions on Computers, Vol. C-36 (12 ), pp. 1440-1449, December 1987 or the same authors, “Performance Evaluation of Vector Accesses in Parallel Memories Using a Skewed Storage Scheme”, Conference Proceedings of the 13th Annual International Symposium on Computer Architecture, pp.324-328, June. 1986, IEEE or US Pat. No. 4,918,600.
[0005]
FIG. 4 shows an example of a computer system that performs main memory skew. The computer system generally indicated by reference numeral 1 has four processors 11 for processing data and a main storage device 31 for storing data, which are coupled to each other via an interconnection network 21. Yes. The main storage device 31 is composed of four memory modules 51, and each memory module 51 has four banks 91. The main storage device 31 as a whole has 16 banks. The interconnection network 21 has an address mapping circuit 41 for performing main memory skew. The address mapping circuit 41 determines a bank to send the main memory access request based on the address information accompanying the main memory access request. The relationship between the bank number BK, the address ADR, and the number N of memory modules (N = 16 in this case) is expressed by (Expression 1).
[0006]
(Equation 1)
BK = (ADR + ADR ÷ N) mod N
Here, mod N represents taking N modulo. FIG. 5 shows address allocation in the computer system 1 that performs this main memory skew. As shown in FIG. 5, the main memory skew in the computer system of FIG. 4 is such that every time the address advances by the number of banks (here, 16), one bank is allocated. FIG. 6 shows the relationship between the stride and the distribution of access requests to the bank when the memory is allocated by the main memory skew.
[0007]
As can be seen from the comparison between FIG. 3 and FIG. 6, by performing main memory skew, it is possible to reduce the types of strides that cause access requests to concentrate on a specific bank or group of banks, resulting in performance degradation. it can.
[0008]
[Problems to be solved by the invention]
In order to improve the performance of the main storage device, a method of replacing the current memory module with a memory module having a different configuration in which various techniques for speeding up are introduced can be considered. Here, when the memory module is replaced with a memory module having a larger number of banks, in the conventional computer system shown in FIG. 4, depending on the stride, the distribution of access requests to the banks does not match the increase in the number of banks. There is a problem that even if the number of banks is increased, the effect as increased cannot be obtained.
[0009]
For example, it is assumed that the entire main storage device is composed of 32 banks, and in a certain stride, access requests are concentrated only in 8 banks. Here, even if the number of banks in each memory module is quadrupled and the configuration of the main memory device is 128 banks, access requests are still concentrated in 8 banks in the stride, and as a result, the performance does not increase. .
[0010]
In the conventional computer system, the main memory skew is adjusted to the initial bank configuration (32 banks in the above example). The main memory skew is a new bank configuration (in the above example, by replacing the memory module). This is because it is not suitable for (128 banks).
[0011]
An object of the present invention is to solve the above-described problem and improve the performance of the main storage device by realizing a main storage skew suitable for the new bank configuration when the number of banks is increased by replacing the memory module. There is.
[0012]
[Means for Solving the Problems]
In order to solve the above problems, a computer system according to the present invention connects one or more processors for processing data, a main storage device for storing data, and the processor and the main storage device to each other. An interconnection network, the interconnection network having one or a plurality of address mapping circuits, the main memory device having a plurality of memory modules, and each memory module having an address mapping circuit. The address conversion is performed in two stages: the address mapping circuit in the interconnection network and the address mapping circuit in the memory module.
[0013]
The address conversion performed by the address mapping circuit in the memory module is a method suitable for the bank configuration of the memory module.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
An example of a computer system according to the present invention is shown in FIG. Although four processors 10 are shown, the number is not essential, and one processor may be used. For this processor, the main storage device 30 is composed of a plurality (four in the figure) of memory modules 50, and the processor 10 and each memory module of the main storage device 30 are connected by an interconnection network 20. The interconnection network 20 includes an address mapping circuit 40, which performs address conversion to reduce concentration of access requests to a specific memory module even during strided access. Furthermore, each memory module 50 constituting the main storage device 30 is also provided with an address mapping circuit 60, and the address conversion performed by the address mapping circuit 60 is a method suitable for the bank configuration in the memory module 50. . As a whole, address conversion for main memory skew is performed in two stages.
[0015]
Embodiments of the present invention will be described below with reference to the drawings.
[0016]
FIG. 7 shows a main configuration of a computer system according to an embodiment of the present invention. The computer system of this embodiment, indicated as a whole by reference numeral 2, has four processors 12 for processing data and a main storage device 32 for storing data, which are mutually connected via an interconnection network 22. Are combined. The interconnection network 22 includes four network control devices 92 corresponding to the four processors 12, and each network control device 92 includes an address mapping circuit 42. The main storage device 32 has four memory modules 52, and each memory module 52 includes an address mapping circuit 62.
[0017]
Each processor 12 has two access ports for the interconnection network 22. The network control device 92 has two access ports for the processor 12. There is a one-to-one correspondence between the processor 12 and the network control device 92 (processor # 0 and network control device # 0, processor # 1 and network control device # 1, etc.). An access path is established between each access port, and the access path between the processor 12 and the network controller 92 is duplicated. A maximum of one access request per cycle flows on each access path, and a maximum of two access requests per cycle are sent from each processor 12 to the corresponding network controller 92.
[0018]
The memory module 52 has four access ports corresponding to the four network control devices 92, respectively. The network control device 92 has four access ports corresponding to the four memory modules 52, respectively. An access path is established between corresponding ports of each network control device 92 and each memory module 52, and as a whole, four network control devices 92 and four memory modules 52 are coupled in an all-to-all manner. . A maximum of one access request flows per cycle on each access path.
[0019]
In the computer system 2 of this embodiment, as an access request sent from the processor 12 to the main storage device 32, a fetch request for storing data from the main storage device in a register (not shown) or a cache (not shown) in the processor, In addition, there is a store request for storing data in a main memory from a register or cache in the processor. However, in the present embodiment, for the sake of simplification, an operation related to store access will be described as an example. Also in the drawing, the apparatus part mainly related to the store request is shown, and circuits for other requests are omitted.
[0020]
When the processor 12 issues a store access request, the request is sent to the corresponding network control device 92 via the duplexed access path. Each processor 12 can issue a maximum of two store requests per cycle to the corresponding network controller 92. When receiving the store request from the processor 12, the network control device 92 transfers the store request to one of the memory modules 52 to which the address specified by the store request belongs. Each network control device 92 can issue a maximum of one store request per cycle independently to each of the four memory modules 52. As a result, a maximum of four store requests can be issued per cycle from each network control device 92 to the entire main storage device 32.
[0021]
As the memory module 52 used in the computer system 2 of this embodiment shown in FIG. 7, the memory module 52A shown in FIG. 8 is used first, and is later replaced with the memory module 52B shown in FIG. 9 to improve performance. And
[0022]
The memory module 52A shown in FIG. 8 includes an address mapping circuit 62A and two bank groups 82. Each bank group 82 includes four banks 72 and can receive a maximum of one store request per cycle. The two bank groups 82 in the memory module 52A operate independently and can be accessed in parallel from the network control device 92. This makes it possible to process more data elements than the number of memory modules in parallel.
[0023]
On the other hand, the memory module 52B shown in FIG. 9 includes an address mapping circuit 62B and eight bank groups 82. Each bank group 82 is the same as that shown in FIG. That is, each bank group 82 includes four banks 72 and can receive a maximum of one store request per cycle. The eight bank groups 82 in the memory module 52B operate independently and can be accessed in parallel from the network control device 92.
[0024]
The entire memory module 52A shown in FIG. 8 can receive up to two store requests per cycle, whereas the entire memory module 52B shown in FIG. 9 receives up to eight store requests per cycle. Can do. In addition, since the total number of banks increases, bank competition is less likely to occur. Accordingly, it is possible to obtain higher processing performance when the main storage device 32 is constructed using the memory module 52B.
[0025]
FIG. 10 shows an address field associated with a store access request issued by the processor 12. In the computer system 2 of this embodiment, the address is specified by 20 bits. Data is stored in the main storage device 32 in units of 8 bytes, and 8 bytes per element is an access unit. In the figure, the upper address means the previously defined address, that is, the number assigned to the access unit of the main storage device 32. In the present embodiment, hereinafter, this upper address may be simply referred to as an address. The upper address consists of 17 bits. On the other hand, the lower address indicates a byte address in one element of data. In this embodiment, since the data element has a size of 8 bytes, the lower address consists of 3 bits.
[0026]
When the main storage device 32 is constructed using the memory module 52A shown in FIG. 8, the address field in FIG. 10 is further interpreted as shown in FIG. When the most significant bit of the address is the 0th bit, the MM field consisting of 2 bits of the 15th bit and the 16th bit is a memory module to which the address is assigned when the address is assigned to the computer system of FIG. Indicates the number. The 14th bit is a BG field, which indicates the bank group number to which the address is assigned in the memory module determined by the MM field. A BK field consisting of 2 bits of the 12th and 13th bits indicates a bank number to which the address is assigned in the bank group. The 0th bit to the 11th bit are fields representing the offset in the bank, and represent the storage position of the access unit to which the address is assigned in the bank.
[0027]
On the other hand, when the main storage device 32 is constructed using the memory module 52B shown in FIG. 9, the address field in FIG. 10 is interpreted as shown in FIG. The MM field consisting of 2 bits of the 15th bit and the 16th bit indicates the memory module number to which the address is assigned when the address is assigned to the computer system of FIG. 7 by the interleave method. The 3rd bit from the 12th bit to the 14th bit is a BG field and indicates a bank group number to which the address is allocated in the memory module determined by the MM field. A BK field consisting of 2 bits of the 10th bit and the 11th bit indicates a bank number to which the address is assigned in the bank group. The 0th to 9th bits are a field representing an in-bank offset, and represent a storage position of an access unit to which the address is assigned in the bank.
[0028]
Hereinafter, an operation when a store access request is issued from the processor 12 will be described.
[0029]
When the processor 12 issues a store access request, the request is sent to the corresponding network control device 92 via the duplexed access path. As described above, each processor 12 can issue a maximum of two store requests per cycle to the corresponding network controller 92.
[0030]
The network controller 92 receives a maximum of two store requests from the processor 12 per cycle. When the store request is received, first, the address mapping circuit 42 is used to convert the address accompanying the store request into an address including the memory module number to be accessed according to the main memory skew scheme in this embodiment. Thereafter, the memory module 52 to which the store request is to be transferred is determined from the converted address, and the store request is transferred to the memory module 52. Each network controller 92 can transfer a maximum of one store request per cycle to each of the four memory modules 52 independently. As a result, a maximum of four store requests can be transferred from each network control device 92 to the entire main storage device 32 per cycle.
[0031]
FIG. 13 shows a method of address conversion performed by the address mapping circuit 42. The address mapping circuit 42 includes a modulo 4 2-bit adder 101. The adder 101 adds the thirteenth to fourteenth bits and the fifteenth to sixteenth bits of the pre-conversion address with 4 modulo and sets the result as the fifteenth to sixteenth bits of the post-conversion address. The carry generated during this addition is ignored (ie, modulo 4 addition is performed). The 0th to 14th bits and the 17th to 19th bits do not change between the pre-conversion address and the post-conversion address. The 15th to 16th bits of the post-conversion address are the memory module number to be accessed. FIG. 14 shows addresses assigned to the memory modules. The relationship between the memory module number MM and the address ADR is expressed by (Expression 2).
[0032]
(Equation 2)
MM = (ADR + ADR ÷ 4) mod 4
In the address allocation of FIG. 14, when the store request is issued from the processor 12 to the network control device 92 at a fixed address interval (stride), the relationship between the stride and the distribution status of the store request to the memory module 52 corresponding thereto Is shown in FIG. Further, in the address allocation of FIG. 14, when the processor 12 issues two store requests at a constant address interval (stride) to the network control device 92 for each cycle, the stride and the network control for it. The relationship with the processing performance of the apparatus 92 is shown in FIG. However, the performance in this case is that a sufficient time has passed since the processor 12 started issuing a store request, and the number of store request transfers from the network controller 92 to the main storage device 32 per cycle became a steady state. The performance when one request can be transferred in one cycle is 1. In order to focus on the processing performance of the network control device 92, it is assumed that there is no stagnation of store requests in the main storage device 32. When the stride is a multiple of 16, two requests are sent per cycle from the processor 12 to the network control unit 92, whereas only one request per cycle is transferred from the network control unit 92 to the main storage unit 32. I can't. Since the request input pitch to the network control device 92 exceeds the processing capability, it is necessary to appropriately suppress the store request issuance of the processor 12.
[0033]
For comparison, FIG. 17 shows an address assigned to each memory module 52 when the network control device 92 does not perform address conversion in the address mapping circuit 42. In addition, FIG. 18 shows the relationship between the stride and the distribution status of the store request to the memory module 52 in that case, and FIG. 19 shows the relationship between the stride and the processing performance of the network control device 92 corresponding thereto. As can be seen from the comparison between FIG. 15 and FIG. 18, the type of stride in which store requests concentrate on the specific memory module 52 can be reduced by the address conversion of the address mapping circuit 42. Further, as can be seen from the comparison between FIG. 16 and FIG. 19, the address conversion of the address mapping circuit 42 can reduce the types of strides that degrade the processing performance of the network control device 92.
[0034]
When the store request is transferred from the network controller 92 to the memory module 52, as shown in FIG. 20, the 15th to 16th bits (MM field) of the address associated with the store request are dropped and transferred. As a result, the number of necessary signal lines can be reduced.
[0035]
The network control device 92 may include a buffer or the like that temporarily stores a store request. As a result, even if the transfer destination of the store request is temporarily concentrated on a specific memory module 52, the store request from the processor 12 is not suppressed unless the store request holding capability in the network control device 92 is exceeded. That's it. Further, the address conversion performed by the address mapping circuit 42 may be different from that shown in FIG. For example, a 2-bit exclusive OR circuit may be used instead of the modulo 4 2-bit adder 101 of FIG.
[0036]
Next, the flow of store request processing in the memory module 52 will be described.
[0037]
First, the case where the memory module 52A shown in FIG. 8 is used will be described. The memory module 52A receives a maximum of one store request per cycle from each of the four network controllers 92. When the store request is received, first, the address mapping circuit 62A is used to convert the address accompanying the store request into an address including the bank group number and bank number to be accessed according to the main memory skew scheme in this embodiment. . Thereafter, the bank group 82 and the bank 72 to which the store request is transferred are determined from the converted address, and the store process is performed in the bank 72 of the bank group 82. Each bank group 82 can perform store processing independently.
[0038]
FIG. 21 shows a method of address conversion performed by the address mapping circuit 62A. The address mapping circuit 62A includes an exclusive OR circuit 102. The exclusive OR circuit 102 receives the 0th to 2nd bits, the 3rd to 5th bits, the 6th to 8th bits, the 9th to 11th bits, and the 12th to 14th bits of the pre-conversion address as a 3 bit wide bit. An exclusive OR is taken every time, and the result is taken as the 12th to 14th bits of the converted address. The 0th to 11th bits and the 15th to 17th bits do not change between the pre-conversion address and the post-conversion address. The 14th bit of the post-conversion address is the bank group number to be accessed, and the 12th to 13th bits are the bank numbers in the bank group. FIG. 22 shows the address allocation to each layer of the memory module, bank group, and bank when the main storage device 32 is constructed using the memory module 62A. FIG. 23 shows the relationship between the stride in this address allocation and the distribution status of the store request for the memory module, bank group, and bank.
[0039]
For comparison, FIG. 24 shows address allocation to each layer of the memory module, bank group, and bank when the memory module 52A does not perform address conversion by the address mapping circuit 62A. In addition, FIG. 25 shows the relationship between the stride and the distribution status of the store request corresponding to the memory module, bank group, and bank in that case. As can be seen from the comparison between FIG. 23 and FIG. 25, if the stride is a multiple of 2 by the address conversion of the address mapping circuit 62A, the number of bank groups and banks to which store requests are sent for the same stride increases. High main memory processing performance can be obtained.
[0040]
Next, a case where the memory module 52B shown in FIG. 9 is used will be described. The memory module 52B receives a maximum of one store request per cycle from each of the four network controllers 92. When a store request is received, first, the address mapping circuit 62B is used to convert the address accompanying the store request into an address including the bank group number and bank number to be accessed according to the main memory skew scheme in this embodiment. . Thereafter, the bank group 82 and the bank 72 to which the store request is transferred are determined from the converted address, and the store process is performed in the bank 72 of the bank group 82. Each bank group 82 can perform store processing independently.
[0041]
FIG. 26 shows a method of address conversion performed by the address mapping circuit 62B. The address mapping circuit 62B includes an exclusive OR circuit 103. The exclusive OR circuit 103 inputs the 0th to 4th bits, the 5th to 9th bits, and the 10th to 14th bits of the pre-conversion address, takes an exclusive OR for each bit of 5 bits width, and outputs the result. The 10th to 14th bits of the post-conversion address. The 0th to 9th bits and the 15th to 17th bits do not change between the pre-conversion address and the post-conversion address. The 12th to 14th bits of the post-conversion address are the bank group number to be accessed, and the 10th to 11th bits are the bank number within the bank group. 27 to 30 show the address assignment to the memory module, bank group, and bank hierarchy when the main storage device 30 is constructed using the memory module 62A. FIG. 31 shows the relationship between the stride in this address allocation and the distribution status of the store request for the memory module, bank group, and bank.
[0042]
For comparison, FIG. 32 to FIG. 35 show the address assignment to each layer of the memory module, bank group, and bank when the memory module 52A does not perform address conversion by the address mapping circuit 62B. In addition, FIG. 36 shows the relationship between the stride and the distribution status of the store request corresponding to the memory module, bank group, and bank in that case. As can be seen from the comparison between FIG. 31 and FIG. 36, if the stride is a multiple of 2 by the address conversion of the address mapping circuit 62B, the number of bank groups and banks to which store requests are sent for the same stride increases. High main memory processing performance can be obtained.
[0043]
As can be seen from the comparison between FIG. 23 and FIG. 31, the store request for the same stride can be obtained by replacing the memory module constituting the main storage device 32 from the memory module 52A in FIG. 8 to the memory module 52B in FIG. Increase in the number of bank groups and banks to which the main storage device 32 having higher processing performance is realized.
[0044]
The memory module 52A in FIG. 8 and the memory module 52B in FIG. 9 may include a buffer or the like that temporarily holds a store request. As a result, even if the transfer destination of the store request is temporarily concentrated on a specific bank group 82 or a specific bank 72, the network control is performed as long as the store request holding capability in the memory module 52A or the memory module 52B is not exceeded. It is not necessary to suppress store requests from the device 92. Further, the address conversion performed by the address mapping circuit 62A or the address mapping circuit 62B may be different from that shown in FIG. For example, a modulo 8 3-bit adder may be used in place of the 3-bit exclusive OR circuit 102 of FIG. In place of the 5-bit exclusive OR circuit 103 shown in FIG. 26, a modulo 32 5-bit adder may be used.
[0045]
A feature of the present invention is that address mapping circuits for realizing main memory skew are provided in two locations in the interconnection network and the memory module, and address conversion is performed in two stages. As a result, even when the configuration of the bank group and the bank is changed due to the replacement of the memory module, the main storage skew suitable for the new configuration can be realized, and high main storage performance can be obtained.
[0046]
Here, for the sake of comparison, consider replacing a memory module in a conventional computer system. In the conventional computer system 3 shown in FIG. 37, the memory module 53 does not have an address mapping circuit, and the address conversion performed by the address mapping circuit 43 in the network control device 93 is different from the address conversion performed by the address mapping circuit 42. The configuration is the same as that of the computer system 2 according to the embodiment of the present invention shown in FIG. As the memory module 53 used in the computer system 3 of FIG. 37, it is assumed that the memory module 53A shown in FIG. 38 is used first, and is later replaced with the memory module 53B shown in FIG. 39 in order to improve performance. The memory module 53A shown in FIG. 38 is the same as the memory module 52A shown in FIG. 8 except that it has no address mapping circuit and does not perform address conversion. 39 is the same as the memory module 52B of FIG. 9 except that it has no address mapping circuit and does not perform address conversion.
[0047]
FIG. 40 shows a method of address conversion performed by the address mapping circuit 43. In the address mapping circuit 43, when the memory module 53A is used in the computer system 3, address conversion is performed so that the same address allocation as that in the case where the memory module 52A is used in the computer system 2, that is, the address allocation of FIG. The address mapping circuit 43 includes a modulo 4 2-bit adder 104 and an exclusive OR circuit 105. The adder 104 adds the thirteenth to fourteenth bits and the fifteenth to sixteenth bits of the pre-conversion address by 4 modulo and sets the result as the fifteenth to sixteenth bits of the post-conversion address. The exclusive OR circuit 105 inputs the 0th to 2nd bits, the 3rd to 5th bits, the 6th to 8th bits, the 9th to 11th bits, and the 12th to 14th bits of the pre-conversion address, An exclusive OR is taken every time and the result is taken as the 12th to 14th bits of the converted address. The 0th to 11th bits and the 17th to 19th bits do not change between the pre-conversion address and the post-conversion address. The address allocation when the memory module 53A is used in the computer system 3 is the same as the address allocation when the memory module 52A is used in the computer system 2 (FIG. 22). Also, the relationship between the stride and the storage request memory module, bank group, and distribution status to the bank is the same as that in the case where the memory module 53A is used in the computer system 2 (FIG. 23).
[0048]
Here, the case where the memory module 53B is used as the memory module 53 of the computer system 3 is considered. The address assignment in this case is shown in FIGS. FIG. 45 shows the relationship between the stride in this address allocation and the distribution status of the store request corresponding to the memory module, bank group, and bank. As can be seen from the comparison between FIG. 31 and FIG. 45, the computer system 2 according to the present invention has a number of banks to which store requests are sent for the same stride when the stride is a multiple of 64 as compared with the conventional computer system 3. Increase, and higher main memory processing performance can be obtained.
[0049]
【The invention's effect】
As described above, in the computer system according to the present invention, even when the bank configuration is changed due to the replacement of the memory module, the main storage skew is suitable for the new bank configuration, thereby improving the performance of the main storage device. be able to.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a main configuration of a computer system according to the present invention.
FIG. 2 is a diagram showing address allocation in an interleave method in which main memory skew is not performed.
FIG. 3 is a diagram illustrating a relationship between a stride and a distribution state of access requests to the bank when the address assignment of FIG. 2 is performed;
FIG. 4 is a block diagram showing the overall configuration of a conventional computer system that performs main memory skew.
FIG. 5 is a diagram showing address allocation when main memory skew is performed in the computer system of FIG. 4;
6 is a diagram showing a relationship between a stride and a distribution state of access requests to banks in response to the address assignment of FIG. 5;
FIG. 7 is a block diagram showing the overall configuration of a computer system according to an embodiment of the present invention.
8 is a block diagram showing a configuration of an example of a memory module used in the computer system of FIG. The memory module is composed of 2 bank groups and each bank group is composed of 4 banks.
9 is a block diagram showing a configuration of an example of a memory module used in the computer system of FIG. The memory module is composed of 8 bank groups and each bank group is composed of 4 banks.
10 is a view showing an address field associated with an access request issued by the processor of the computer system of FIG. 7;
11 is a diagram showing an address field associated with a store request sent from the processor to the network control device when the main storage device of the computer system of FIG. 7 is constructed with the memory module of FIG. 8;
12 is a diagram showing an address field associated with a store request sent from the processor to the network control device when the main storage device of the computer system of FIG. 7 is constructed by the memory module of FIG. 9;
13 is a diagram showing a method of address conversion performed by the address mapping circuit 42 of the computer system of FIG. 7;
14 is a diagram showing addresses assigned to each memory module when the address conversion of FIG. 13 is performed.
15 is a diagram showing a relationship between a stride and a distribution status of store requests to memory modules in response to the address assignment shown in FIG. 14;
FIG. 16 is a diagram showing the relationship between stride and the processing performance of the network control apparatus for the address assignment in FIG.
17 is a diagram showing addresses assigned to each memory module when the address conversion in FIG. 13 is not performed.
18 is a diagram showing the relationship between the stride and the distribution status of store requests to the memory modules when the address allocation of FIG. 17 is performed.
19 is a diagram showing the relationship between stride and the processing performance of the network control apparatus for the address assignment in FIG.
20 is a diagram showing a method for reducing an address width when transferring a store request from the network control apparatus to the memory module in the computer system of FIG. 7;
FIG. 21 is a diagram illustrating a method of address conversion performed by the address mapping circuit 62A of the memory module in FIG. 8;
22 is a diagram showing address allocation when the memory module 52A of FIG. 8 is used in the computer system of FIG. 7;
FIG. 23 is a diagram showing a relationship between a stride and a distribution status of store requests corresponding to the memory modules, bank groups, and banks when the address allocation of FIG. 22 is performed;
24 is a diagram showing address assignment when the address conversion in FIG. 21 is not performed.
FIG. 25 is a diagram showing a relationship between a stride and a distribution status of store requests corresponding to the memory modules, bank groups, and banks when the address allocation of FIG. 24 is performed;
26 is a diagram showing a method of address conversion performed by the address mapping circuit 62B of the memory module in FIG. 9;
27 is a diagram showing a part of address assignment when the memory module 52B of FIG. 9 is used in the computer system of FIG. 7;
28 is a diagram showing a part of address assignment when the memory module 52B of FIG. 9 is used in the computer system of FIG. 7;
29 is a view showing a part of address assignment when the memory module 52B of FIG. 9 is used in the computer system of FIG. 7;
30 is a diagram showing a part of address assignment when the memory module 52B of FIG. 9 is used in the computer system of FIG. 7;
FIG. 31 is a diagram showing a relationship between a stride and a distribution status of store requests corresponding to the memory modules, bank groups, and banks when the addresses shown in FIGS. 27 to 30 are assigned;
FIG. 32 is a diagram showing a part of address assignment when the address conversion in FIG. 26 is not performed;
FIG. 33 is a diagram showing a part of address assignment when the address conversion in FIG. 26 is not performed;
34 is a diagram showing a part of address assignment when the address conversion in FIG. 26 is not performed.
FIG. 35 is a diagram showing a part of address assignment when the address conversion in FIG. 26 is not performed;
FIG. 36 is a diagram showing a relationship between a stride and a distribution status of store requests corresponding to the memory modules, bank groups, and banks when the address allocation of FIGS. 32 to 35 is performed.
FIG. 37 is a block diagram showing the overall configuration of an example of a conventional computer system.
38 is a block diagram showing a configuration of an example of a memory module used in the computer system of FIG. The memory module is composed of 2 bank groups and each bank group is composed of 4 banks.
39 is a block diagram showing a configuration of an example of a memory module used in the computer system of FIG. The memory module is composed of 8 bank groups and each bank group is composed of 4 banks.
40 is a diagram showing an address conversion method performed by the address mapping circuit 43 of the computer system of FIG. 37;
41 is a view showing a part of address assignment when the memory module 53B of FIG. 39 is used in the computer system of FIG. 37;
42 is a diagram showing a part of address assignment when the memory module 53B of FIG. 39 is used in the computer system of FIG. 37;
43 is a diagram showing a part of address assignment when the memory module 53B of FIG. 39 is used in the computer system of FIG.
44 is a diagram showing a part of address assignment when the memory module 53B of FIG. 39 is used in the computer system of FIG. 37;
45 is a diagram showing the relationship between the stride and the distribution status of store requests corresponding to the memory modules, bank groups, and banks when the addresses shown in FIGS. 41 to 44 are assigned. FIG.
[Explanation of symbols]
10 processor
20 Interconnection network
30 Main memory
40 Address mapping circuit
50 memory modules
60 Address mapping circuit.

Claims (2)

Comprising a one or more processors, a main memory device including a plurality of memory modules, and interconnection network to couple to each other between said plurality of memory modules of the main memory and the processor, wherein the plurality Each of the memory modules in a computer system having a plurality of memory banks ,
The interconnection network includes
A predetermined conversion is performed on a specific bit of a main memory address designated by the processor to identify a memory module corresponding to the main memory address designated by the processor, and an address allocation by an interleave method is performed on the plurality of memory modules by the conversion. A first address mapping circuit to be realized ;
Means for transferring a main memory address specified by the processor excluding the specific bit to the memory module specified by the first address mapping circuit ;
Each of the memory modules has a second address mapping circuit that converts the main memory address transferred via the coupling network and realizes address allocation by interleaving in the memory bank in each memory module by the conversion. And
A computer system that performs address conversion in two stages of the first and second address mapping circuits.   2. The computer system according to claim 1, wherein the address conversion performed by the second address mapping circuit is performed by a method suitable for a bank configuration of the memory module.

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