JP7408954B2 - Memory control method, memory control device, program - Google Patents

Description

The present invention relates to a memory control method, a memory control device, and a program for controlling a memory having a plurality of banks.

The processor transfers data from external memory and cache memory and performs arithmetic processing on the data. Therefore, data arithmetic processing performance is affected by memory bandwidth. In particular, vector processors perform multiple arithmetic operations in parallel, so they are more susceptible to the influence of memory bandwidth, and memory bandwidth is important. Therefore, in vector processor devices, memory bandwidth is increased by connecting a large number of memory channels and interleaving the channels. Additionally, in recent years, the use of DDR SDRAM has increased due to cost considerations. DDR SDRAM consists of multiple banks to increase memory bandwidth performance. As shown in Patent Document 1, in such a memory configured with a plurality of banks, interleaving is performed between the banks to increase the memory bandwidth.

Japanese Patent Application Publication No. 2002-342306

Here, a case will be described in which DDR SDRAM is used as a memory of a vector processor device. In this case, the vector processor device includes a plurality of memories each having a plurality of banks, and the vector processor is connected to the plurality of memories via one memory control device. For example, as shown in FIG. 1, one memory control device 100 includes a bank address generation section 101 and a memory address generation section 102, and the bank address generation section 101 includes, as shown in FIG. A bank address is generated by extracting the bank number from the physical address sent when the vector processor accesses the memory.

However, since the bank address generation unit 101 described above is common to a plurality of memories, bank conflicts occur between a plurality of sequential accesses to the memories, and memory bandwidth cannot be used efficiently. In other words, when bank conflict occurs in one memory, bank conflict occurs in other memories, and bank conflict occurs throughout multiple sequential accesses, creating the problem that memory bandwidth cannot be used efficiently. . On the other hand, in order to avoid bank conflicts between multiple sequential accesses to memory, it is necessary to adjust the memory space reservation by software, which makes the configuration complicated.

Therefore, an object of the present invention is to provide a memory control method, a memory control device, and a program that can solve the problems of a complicated configuration and an inability to use memory bandwidth efficiently.

A memory control method that is one form of the present invention includes:
A memory control method for controlling access to a plurality of memories each having a plurality of banks, the method comprising:
Generating a plurality of memory addresses that designate each of the plurality of memories as an access destination from a specified physical address, and a plurality of banks that designate each of the predetermined banks in the plurality of memories as an access destination from the physical address. generating a plurality of bank addresses that are different for each memory when generating addresses;
The structure is as follows.

Further, a memory control device that is one form of the present invention includes:
A memory control device that controls access to a plurality of memories each having a plurality of banks, the memory control device comprising:
Generating a plurality of memory addresses specifying each of the plurality of memories as an access destination from a specified physical address, and a plurality of bank addresses specifying each of the predetermined banks in the plurality of memories as an access destination from the physical address. generating a plurality of bank addresses that are different for each memory when generating the bank address;
The structure is as follows.

Further, a program that is one form of the present invention is
A memory control device that controls access to a plurality of memories each having a plurality of banks;
Generating a plurality of memory addresses specifying each of the plurality of memories as an access destination from a specified physical address, and a plurality of bank addresses specifying each of the predetermined banks in the plurality of memories as an access destination from the physical address. a process of generating a plurality of bank addresses that are different for each memory when generating a bank address;
to execute,
The structure is as follows.

Further, a vector processor device that is one form of the present invention includes
A vector processor, a plurality of memories each having a plurality of banks, and a memory control device that controls access to the memory,
The memory control device generates a plurality of memory addresses that designate each of the plurality of memories as an access destination from the physical address specified by the vector processor, and also generates a plurality of memory addresses that designate each of the plurality of memories as an access destination from the physical address, and generating a plurality of bank addresses that are different for each of the memories when generating a plurality of bank addresses each specifying a bank as an access destination;
The structure is as follows.

By being configured as described above, the present invention can efficiently utilize memory bandwidth.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram for explaining the background technology of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram for explaining the background technology of the present invention. 1 is a diagram showing the configuration of a vector processor device in Embodiment 1 of the present invention. 4 is a functional block diagram showing the configuration of the memory control unit disclosed in FIG. 3. FIG. 4 is a diagram illustrating an example of an address calculation method by the memory control unit disclosed in FIG. 3. FIG. 4 is a diagram illustrating an example of an address calculation method by the memory control unit disclosed in FIG. 3. FIG. 4 is a diagram illustrating an example of an address calculation method by the memory control unit disclosed in FIG. 3. FIG. 4 is a diagram illustrating an example of an address calculation method by the memory control unit disclosed in FIG. 3. FIG. 4 is a diagram illustrating an example of an address calculation method by the memory control unit disclosed in FIG. 3. FIG. FIG. 7 is a diagram showing the configuration of a memory control device in Embodiment 2 of the present invention.

<Embodiment 1>
A first embodiment of the present invention will be described with reference to FIGS. 3 to 9. As shown in FIG. 3, the vector processor device 1 of the present invention includes a vector processor 40, a memory network 30, a plurality of memory control units 10, and a plurality of memories 20. The vector processor 40 is connected to a plurality of memory control units 10 via the memory network 30, and each memory control unit 10 is connected to each memory 20. In the example of FIG. 3, for example, the memories 20 (numbers 0 to 3) are connected to the four memory control units 10 (numbers 0 to 3), respectively. Further, each memory 20 includes a plurality of banks 21, and is configured of, for example, DDR SDRAM. In the example of FIG. 3, each memory 20 includes, for example, eight banks 21 (numbered 0 to 7). Note that the vector processor device 1 functions as a memory control device in order to control access to a plurality of installed memories.

The memory control unit 10 is composed of an arithmetic unit, and includes a bank address generation unit 11 and a memory address generation unit 12, which are constructed by executing a program. The memory address generation unit 12 generates a memory address that designates the connected memory 20 as an access destination from a physical address according to a vector load instruction or a vector store instruction issued from the vector processor 40, as described later. Further, the bank address generation unit 11 generates a bank address that designates a bank in the connected memory 20 as an access destination from the physical address. In the present invention, as will be described later, each bank address generation unit 11 of a plurality of memory control units 10 generates different bank addresses (bank numbers) from the same physical address using different calculation methods.

Here, the method of generating each address by the bank address generation section 11 and memory address generation section 12 described above will be explained in detail. First, memory access is performed in response to a vector load instruction or a vector store instruction from the vector processor 40, and such memory access is performed using a physical address. At this time, in the vector load instruction and the vector store instruction, consecutive physical addresses are interleaved to each memory control unit 10 via the memory network 30, so the physical addresses sent to each memory control unit 10 are the same. . Note that, as shown in FIG. 5, the physical address includes, from the lower bit, an in-line address, a bank number, and an upper address.

Then, each memory address generation unit 12 that has received the physical address as described above generates a memory address by combining the upper address in the physical address and the in-line address, as shown in FIG. Therefore, each memory address generation unit 15 that receives the same physical address generates the same memory address, and designates the memory 20 connected to each one as the access destination.

Further, each bank address generation unit 11 that has received the physical address as described above uses the upper address in the physical address and the bank number to determine which address in the memory 20 connected to each bank address, as shown in FIG. A bank address that specifies the bank 21 as the access destination is generated. Specifically, each bank address generation unit 11 first generates a "bank number" that specifies the bank 21 from the "upper address" of the physical address using a different function (calculation method) for each connected memory 20. Generate intermediate data (modified data) with the same bit size as . That is, as shown in FIG. 5, first, the function "f _{memory number} (upper address)" generates different first data for each memory 20 connected from the upper address, and then uses the first data as needed. Accordingly, the data is divided into multiple parts to generate intermediate data. Then, each bank address generation unit 11 generates a bank address by performing a bit-by-bit exclusive OR of the generated "intermediate data" and the "bank number" included in the physical address.

Here, an example of bank address generation by the bank address generation section 11 included in each memory control section 10 (numbered 0 to 3) connected to each memory 20 will be described with reference to FIGS. 6 to 9. First, FIG. 6 shows an example of generation by the bank address generation unit 11 corresponding to the memory 20 with memory number 0. As shown in FIG. 6, first, the "upper address" is used as it is as first data, and intermediate data is generated by dividing the first data into the same bit size as the "bank number." Here, the first data is divided into three parts, but the number of divisions is just an example. Then, a bank address is generated by the exclusive OR of the intermediate data, which is each divided upper address, and the exclusive OR of the bank number.

Further, FIG. 7 shows an example of generation by the bank address generation unit 11 corresponding to the memory 20 with memory number 1. As shown in FIG. 7, for the memory 20 with memory number 1, first data is generated by rotating the "higher address" by 1 bit to the right. In other words, the least significant bit of the "upper address" is made the most significant bit, and the other bits are each shifted lower by one bit. Then, the first data generated by shifting one bit is divided into the same bit size as the bank number (for example, divided into three) to generate intermediate data, and the exclusive OR of each and the bank number is A bank address is generated by the sum.

Further, FIG. 8 shows an example of generation by the bank address generation unit 11 corresponding to the memory 20 with memory number 2. As shown in FIG. 8, for the memory 20 with memory number 2, the "upper address" is first rotated to the right by 2 bits to generate first data. In other words, the two least significant bits of the "upper address" are made the two most significant bits, and the other bits are each shifted two bits lower. Then, the first data generated by shifting 2 bits is divided into the same bit size as the bank number (for example, divided into 3) to generate intermediate data, and the exclusive OR of each and the bank number is A bank address is generated by the sum.

Further, FIG. 9 shows an example of generation by the bank address generation unit 11 corresponding to the memory 20 with memory number 3. As shown in FIG. 9, for the memory 20 with memory number 3, the "upper address" is first rotated to the right by 3 bits to generate first data. In other words, the least significant three bits of the "higher address" are made the most significant three bits, and the other bits are each shifted three bits lower. Then, the first data generated by shifting 3 bits is divided into the same bit size as the bank number (for example, divided into 3) to generate intermediate data, and the exclusive OR of each and the bank number is A bank address is generated by the sum.

As described above, in the present invention, intermediate data is generated for each of the plurality of memories 20 by using different functions for the same physical address, that is, by rotating different numbers of bits, and from such intermediate data. Generating bank address. Therefore, different bank addresses are generated for each of the plurality of memories 20, and bank conflicts between the plurality of sequential accesses to the memories 20 can be reduced. As a result, it is possible to improve memory bandwidth.

<Embodiment 2>
Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 10 is a block diagram showing the configuration of a memory control device according to the second embodiment. Note that this embodiment shows an outline of the configuration of the vector processor device described in the first embodiment.

As shown in FIG. 10, the memory control device 200 in this embodiment includes:
A memory control device 200 that controls access to a plurality of memories 210 each having a plurality of banks 211,
A plurality of memory addresses that designate each of the plurality of memories 210 as an access destination are generated from a specified physical address, and a plurality of banks that designate each of the predetermined banks in the plurality of memories as an access destination from the physical address. generating a plurality of bank addresses that are different for each memory when generating addresses;
It has the following structure.

Note that the functions of the memory control device 200 are realized by the memory control device 200 executing a program.

The memory control device 200 having the above configuration has the following features:
As a memory control method for controlling access to multiple memories each having multiple banks,
Generating a plurality of memory addresses that designate each of the plurality of memories as an access destination from a specified physical address, and a plurality of banks that designate each of the predetermined banks in the plurality of memories as an access destination from the physical address. generating a plurality of bank addresses that are different for each memory when generating addresses;
It operates to execute the process.

As described above, according to the present invention, different bank addresses are generated for each of a plurality of memories. Therefore, bank conflicts between multiple sequential accesses to memory can be reduced, and memory bandwidth can be improved.

<Additional notes>
Part or all of the above embodiments may also be described as in the following additional notes. Hereinafter, the outline of the structure of the memory control method, memory control device, and program according to the present invention will be explained. However, the present invention is not limited to the following configuration.

(Additional note 1)
A memory control method for controlling access to a plurality of memories each having a plurality of banks, the method comprising:
Generating a plurality of memory addresses specifying each of the plurality of memories as an access destination from a specified physical address, and a plurality of banks specifying each of the predetermined banks in the plurality of memories as an access destination from the physical address. generating a plurality of bank addresses that are different for each memory when generating addresses;
Memory control method.

(Additional note 2)
The memory control method according to appendix 1, comprising:
Each memory control unit connected to each of the memories generates the bank address, which is different for each of the memories, from the physical address.
Memory control method.

(Additional note 3)
The memory control method according to supplementary note 1 or 2,
generating the bank address, which is different for each memory, from the physical address using a different calculation method for each memory;
Memory control method.

(Additional note 4)
The memory control method according to any one of Supplementary Notes 1 to 3,
generating different modified data for each of the memories from the physical address, and generating different bank addresses for each of the memories from the transformed data;
Memory control method.

(Appendix 5)
The memory control method according to appendix 4, comprising:
sliding at least part of the data of the physical address for each memory to generate the deformed data that is different for each memory, and generate the bank address that is different for each memory from the deformed data;
Memory control method.

(Appendix 6)
The memory control method according to appendix 4 or 5,
generating a different bank address for each memory based on an address specifying the bank included in the physical address and the modified data;
Memory control method.

(Appendix 7)
The memory control method according to appendix 6, comprising:
generating a different bank address for each memory from an exclusive OR of an address specifying the bank included in the physical address and one or more data extracted from the modified data;
Memory control method.

(Appendix 8)
A memory control device that controls access to a plurality of memories each having a plurality of banks, the memory control device comprising:
Generating a plurality of memory addresses specifying each of the plurality of memories as an access destination from a specified physical address, and a plurality of bank addresses specifying each of the predetermined banks in the plurality of memories as an access destination from the physical address. generating a plurality of bank addresses that are different for each memory when generating the bank address;
Memory controller.

(Appendix 8-1)
The memory control device according to appendix 8,
A memory control unit connected to each of the memories,
Each of the memory control units includes a memory address generation unit that generates the memory address that specifies the connected memory as an access destination, and a bank address that specifies the predetermined bank in the connected memory as the access destination. a bank address generation unit that generates a bank address different from the bank address generated by the other memory control unit,
Memory controller.

(Appendix 8-2)
The memory control device according to Appendix 8-1,
The bank address generation unit of the memory control unit generates the bank address from the physical address using a calculation method different from the method used by the bank address generation units of other memory control units.
Memory controller.

(Appendix 8-3)
The memory control device according to appendix 8-1 or 8-2,
The bank address generation unit of the memory control unit generates modified data different from data generated by the bank address generation units of other memory control units from the physical address, and generates the bank address from the modified data. do,
Memory controller.

(Appendix 8-4)
The memory control device according to Appendix 8-3,
The bank address generation section of the memory control section uses at least part of the data of the physical address as it is or slides it to combine it with data generated by the bank address generation section of the other memory control section. generates the different modified data, and generates the bank address from the modified data;
Memory controller.

(Appendix 8-5)
The memory control device according to appendix 8-3 or 8-4,
The bank address generation unit of the memory control unit generates the bank address based on the address specifying the bank included in the physical address and the modified data.
Memory controller.

(Appendix 8-6)
The memory control device according to Appendix 8-5,
The bank address generation unit of the memory control unit generates the bank address from an exclusive OR of an address specifying the bank included in the physical address and one or more data extracted from the modified data. generate,
Memory controller.

(Appendix 9)
A memory control device that controls access to a plurality of memories each having a plurality of banks;
Generating a plurality of memory addresses specifying each of the plurality of memories as an access destination from a specified physical address, and a plurality of bank addresses specifying each of the predetermined banks in the plurality of memories as an access destination from the physical address. a process of generating a plurality of bank addresses that are different for each memory when generating a bank address;
A program to run.

(Appendix 9-1)
The program described in Appendix 9,
The memory control device further includes a memory control unit connected to each of the memories, and
a memory address generation unit that generates the memory address that specifies the memory connected to the memory control unit as an access destination; and the bank address that specifies the predetermined bank in the connected memory as the access destination. and a bank address generation unit that generates a bank address different from the bank address generated by another of the memory control units,
program for.

(Appendix 10)
A vector processor, a plurality of memories each having a plurality of banks, and a memory control device that controls access to the memory,
The memory control device generates a plurality of memory addresses that designate each of the plurality of memories as an access destination from the physical address specified by the vector processor, and also generates a plurality of memory addresses that designate each of the plurality of memories as an access destination from the physical address, and also generates a plurality of memory addresses from the physical address in the plurality of memories. generating a plurality of bank addresses that are different for each of the memories when generating a plurality of bank addresses specifying each bank as an access destination;
Vector processor device.

(Appendix 10-1)
The vector processor device according to appendix 10,
The memory control device includes a memory control unit connected to each of the memories,
Each of the memory control units includes a memory address generation unit that generates the memory address that specifies the connected memory as an access destination, and a bank address that specifies the predetermined bank in the connected memory as the access destination. a bank address generation unit that generates a bank address different from the bank address generated by the other memory control unit,
Vector processor device.

Note that the program can be stored and supplied to a computer using various types of non-transitory computer readable media. Non-transitory computer-readable media includes various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic recording media (e.g., flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (e.g., magneto-optical disks), CD-ROMs (Read Only Memory), CD-Rs, CD-R/W, semiconductor memory (for example, mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM), flash ROM, RAM (Random Access Memory)). The program may also be provided to the computer on various types of transitory computer readable media. Examples of transitory computer-readable media include electrical signals, optical signals, and electromagnetic waves. The temporary computer-readable medium can provide the program to the computer via wired communication channels, such as electrical wires and fiber optics, or wireless communication channels.

Although the present invention has been described above with reference to the above-described embodiments, the present invention is not limited to the above-described embodiments. The configuration and details of the present invention can be modified in various ways within the scope of the present invention by those skilled in the art.

1 Vector processor device 10 Memory control unit 11 Bank address generation unit 12 Memory address generation unit 20 Memory 21 Bank 30 Memory network 40 Vector processor 200 Memory control device 210 Memory 211 Bank

Claims (8)

A memory control method in which a plurality of memory control units control access to a plurality of memories each having a plurality of banks, the method comprising:
Each of the memory control units connected to each of the memories generates a memory address that designates the memory connected to the memory control unit as an access destination from a specified physical address, and generating a different bank address for each memory when generating a plurality of bank addresses each specifying a predetermined bank in the memory connected to the memory control unit as an access destination;
Memory control method. The memory control method according to claim 1 , comprising:
the memory control unit generates the bank address, which is different for each memory, from the physical address using a different calculation method for each memory;
Memory control method. The memory control method according to claim 1 or 2 ,
the memory control unit generates different modified data for each of the memories from the physical address, and generates the bank address that differs for each of the memories from the modified data;
Memory control method. 4. The memory control method according to claim 3 ,
the memory control unit generates the bank address, which is different for each memory, based on the address specifying the bank included in the physical address and the deformation data;
Memory control method. 5. The memory control method according to claim 4 ,
The memory control unit determines the bank address, which is different for each memory, from an exclusive OR of an address specifying the bank included in the physical address and one or more data extracted from the modified data. generate,
Memory control method. A memory control device having a plurality of memory control units that control access to a plurality of memories each having a plurality of banks,
Each of the memory control units connected to each of the memories generates a memory address specifying the memory connected to the memory control unit as an access destination from a specified physical address, and from the physical address. generating a different bank address for each memory when generating a plurality of bank addresses each designating a predetermined bank in the memory connected to the memory control unit as an access destination;
Memory controller. A memory control device having a plurality of memory control units that control access to a plurality of memories each having a plurality of banks;
Each of the memory control units connected to each of the memories generates a memory address specifying the memory connected to the memory control unit as an access destination from a specified physical address, and from the physical address. generating a different bank address for each memory when generating a plurality of bank addresses each designating a predetermined bank in the memory connected to the memory control unit as an access destination ;
A program to execute processing . comprising a vector processor, a plurality of memories each having a plurality of banks, and a memory control device having a plurality of memory control units that control access to the memory,
Each of the memory control units connected to each memory generates a memory address specifying the memory connected to the memory control unit as an access destination from the physical address specified by the vector processor. and generating a different bank address for each memory when generating a plurality of bank addresses each specifying a predetermined bank in the memory connected to the memory control unit as an access destination from the physical address. do,
Vector processor device.

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