JP5852090B2 - Instruction processing apparatus and instruction processing method thereof - Google Patents

Description

  The present invention relates to an instruction processing device and an instruction processing method thereof.

  The write command for the storage device (memory) includes a full write command for writing data having a full data width (for example, 8 bytes) that allows connection between the storage device and another device, and a part of the data. There are partial write instructions for rewriting (for example, 3 bytes out of 8 bytes), and generally the ratio of partial write instructions is large. Hereinafter, in the present application, such a partial write instruction is referred to as a “partial store instruction”. In order to execute this partial store instruction, the data at the address specified by the instruction is once read from the storage device, merged with the partial data to be partially written, and written back to the original storage device.

  In recent years, since the memory connected to the computer has increased, the memory controller manages the memory built in the computer in units called memory banks (also simply referred to as banks). The memory bank is a memory divided into a certain amount of capacity. When an access request to the memory is generated, the memory controller selects a target memory bank and increases the processing efficiency by accessing only the selected memory bank.

  In such a computer having a plurality of memory bank configurations, when a partial store instruction for the same address is frequently issued, the memory throughput performance deteriorates due to an increase in busy time for the same memory bank. As a method for improving this, Patent Document 1 and Patent Document 2 are designed to improve the memory throughput performance by reducing the number of memory accesses by merging store data designated by a plurality of partial store instructions for the same address. Disclosure technology is disclosed.

  However, if a load instruction for the same address is received after the partial store instruction, the same bank is accessed, and a busy state occurs in the same bank. As a result, the memory cannot be used efficiently, and the memory throughput performance is reduced.

  Here, as related technologies existing prior to the present application, there are, for example, the following patent documents.

  Patent Documents 3 and 4 disclose a technique for generating load data without waiting for execution of a store instruction when a load instruction for the same address follows the store instruction.

JP-A 63-091756 JP 63-103342 A JP 05-040629 A JP 2009-540411 A

  However, the techniques proposed in Patent Documents 3 and 4 are related to store instructions, and are not considered when a load instruction for the same address is received after a partial store instruction.

  Accordingly, the main object of the present invention is to provide an instruction processing device or the like that can improve memory throughput performance when a load instruction for the same address is received after a partial store instruction.

  In order to achieve the above object, an instruction processing apparatus according to the present invention comprises the following arrangement.

That is, the instruction processing device according to this description is
A memory whose storage area is determined by an address;
A store merge control circuit that receives a partial store instruction for a specific address of the memory and controls to store the content specified by the partial store instruction;
When the load instruction for the specific address is received after receiving the partial store instruction, the content specified by the partial store instruction stored under the control of the store merge control circuit, the content of the load instruction, And a store load instruction generation circuit for generating a store load instruction.

An instruction processing method according to the present invention for achieving the same object is as follows.
In response to a partial store instruction for a specific address of the memory whose storage area is determined by the address, the contents specified by the partial store instruction are stored in the storage device,
After receiving the partial store instruction, when receiving a load instruction for the specific address, based on the content specified by the partial store instruction stored in the storage device and the content of the load instruction, A store load instruction is generated.

  According to the present invention described above, there is an effect that it is possible to improve the memory throughput performance when a load instruction for the same address is received after a partial store instruction.

It is a block diagram which shows the structure of the instruction processing apparatus which concerns on the 1st Embodiment of this invention. It is a figure explaining the information table which concerns on the 1st Embodiment of this invention. It is a time chart explaining the effect which concerns on the 1st Embodiment of this invention.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

<First Embodiment>
FIG. 1 is a block diagram showing a configuration of an instruction processing apparatus 10 according to the first embodiment of the present invention.

  The instruction processing apparatus 10 according to the present embodiment includes a store merge control circuit 11, a store load instruction generation circuit 12, an instruction execution control circuit 13, an address pipe 14, a data pipe 15, an ECG 16, a memory 17, An ECC 18 and a selector 19 are included. A plurality of flip-flops shown in FIG. 1 are storage units for storing inputted information. A plurality of selectors shown in FIG. 1 are circuits that select information satisfying a predetermined condition from among a plurality of input information.

  The memory 17 is a semiconductor storage element (for example, DRAM (Dynamic Random Access Memory)) whose storage area is determined by an address.

  The store merge control circuit 11 is a circuit capable of merging the contents designated by the partial store instruction received by the instruction processing device 10 from the host device (external device) up to continuous 8 bytes. In this embodiment, it is possible to merge up to 8 bytes, but the present invention is not limited to this. The host device is, for example, an arithmetic device.

  The store merge control circuit 11 stores an information table 110 (not shown in FIG. 1, not shown in FIG. 1; see FIG. 2 shown below) that stores the contents designated by the partial store instruction or the contents after merging them. ). However, the information table 110 may not be provided in the store merge control circuit 11 as long as it can be referenced and updated by the store merge control circuit 11.

  FIG. 2 is a diagram illustrating the information table 110 according to the first embodiment of the present invention.

  The information table 110 includes an address 111, store data 112, and byte enable information 113. That is, the address 111, the store data 112, and the byte enable information 113 are associated in the information table 110 as shown in a table conceptually shown in FIG.

  The address 111 is an address on an 8-byte address boundary (that is, an address whose last 3 bits are 000). The area indicated by the address specified by the partial store instruction is included in an area of 8 bytes continuous from the area indicated by the address.

  Store data 112 is the content of updated data designated by a partial store instruction for an area of 8 bytes continuous from the area indicated by address 111.

  The byte enable information 113 is information indicating whether the store data 112 is valid or invalid (that is, updated or not updated) for each byte. Since the byte enable information 113 represents the validity or invalidity of one byte of the store data 112 by 1 bit, it is 8 bits in this embodiment.

  When the instruction processing apparatus 10 accepts a partial store instruction, the store merge control circuit 11 refers to the address 111 of the information table 110 so that an address of an 8-byte address boundary including the area indicated by the specified address exists. Search for what to do.

  When the designated address exists, for the entry including the address 111 in the information table 110, the store merge control circuit 11 adds the content of the updated data designated by the partial store instruction to the store data 112. Are merged (updated), and the byte enable information 113 is updated according to the merged contents.

  When the designated address does not exist, the store merge control circuit 11 sets the address 111, the store data 112, and the byte enable information in the unused entry of the information table 110 based on the contents designated by the partial store instruction. 113 is registered in association with it. When the entries have already been registered in all entries of the information table 110, the store merge control circuit 11 selects one entry, passes the contents of the entry to the instruction execution control circuit 13, and deletes the contents of the entry. The method for selecting an entry is not particularly limited. For example, there is a method for selecting an entry for which a value to be updated has been set for all the 8-byte data constituting the store data 112. The store merge control circuit 11 registers the address 111, the store data 112, and the byte enable information 113 in association with the entry from which the content has been deleted based on the content specified by the partial store instruction.

  When the instruction processing device 10 receives a load instruction, the store merge control circuit 11 includes an area indicated by the address specified by the load instruction in an area of 8 bytes from the area indicated by the address 111. Search for.

  When the designated address exists, the store merge control circuit 11 passes the contents of the entry found by the search to the store load instruction generation circuit 12 and deletes the contents of the entry.

  When the designated address does not exist, the store merge control circuit 11 passes the content included in the load instruction to the instruction execution control circuit 13 as it is.

  The store load instruction generation circuit 12 generates one store load instruction based on the information indicating the load instruction received from the store merge control circuit 11 and the contents of the partial store instruction registered in the information table 110 (FIG. 2). Is a circuit that generates

  The store load instruction is an instruction for performing a read-modify-write operation.

  That is, the store load instruction first reads data at a corresponding address and merges (updates) data to be written into the read data in order to generate an error correcting code (ECC). Then, the store load instruction completes execution of the store load instruction by adding an error correction code to the merged data and writing it in the memory 17. A known technique may be used as an error correction method using an error correction code.

  The instruction execution control circuit 13 is a circuit that controls the memory 17 to execute a store load instruction.

  The instruction execution control circuit 13 is a circuit that manages the busy state of the memory 17. The instruction execution control circuit 13 holds the time required for a request issued for each bank. The instruction execution control circuit 13 determines whether or not the memory bank to be accessed is busy by referring to the held time. If the determined result is not busy, the instruction execution control circuit 13 accesses the memory 17. In the busy state, the instruction execution control circuit 13 waits until the busy state is resolved in this circuit.

  The ECG (error correction code generation circuit) 16 is a circuit that generates an error correction code to be added to store data (that is, data to be written to the memory 17) when data is written to the memory 17. The ECC 18 is a circuit that, when data is read from the memory 17, corrects data when it can be corrected, and detects an error when data cannot be corrected. The ECC 18 may adjust the ECC unit (data correction unit) at the time of data correction to the number of bytes obtained by merging the contents specified by the partial store instruction. In the present embodiment, the content specified by the partial store instruction is merged up to 8 consecutive bytes, so the ECC unit (data correction unit) is 8 bytes.

  The address pipe 14 is a circuit for storing an address at which data is read from the memory 17 until a timing at which data is written back to the address in the case of a partial store instruction and a store load instruction.

  The data pipe 15 includes a circuit that stores store data and a circuit that modifies load data (data read from the memory 17) into store data (hereinafter referred to as a modify circuit). The modify circuit creates store data by modifying the load data based on the byte enable information 113.

  The selector 19 is a circuit used when a store load instruction is executed. The selector 19 selects the data modified by the data pipe 15 and returns it as load data to the host device.

  Next, the operation of the present embodiment will be described by taking as an example an instruction for partial store of data “XXX” in the 3 bytes from the beginning of the area of 8 bytes from address A. The store merge control circuit 11 indicates the contents of the partial instruction as “A” in the address 111 and “XXX -----” in the store data 112 as shown in the first entry in the information table 110 shown in FIG. The byte enable information 113 is registered in association with 0xE0. The “-” part is not referred to and may be any value. Further, “0x” indicates that the following alphanumeric character is expressed in hexadecimal.

  Thereafter, when the instruction processing device 10 receives a load instruction for address A, the address 111 of the information table 110 is referred to search for an entry having the address 111 of “A”. As a result of the search, since the address 111 of the partial store instruction registered in the first entry is “A”, the contents of the first entry are passed to the store load instruction generation circuit 12 and the contents of the entry are deleted. .

  The store load instruction generation circuit 12 generates one store load instruction based on the contents of the passed partial store instruction and the load instruction that causes the contents of the partial store instruction to be passed.

  The instruction execution control circuit 13 stores information indicating an address in the address pipe 14 and store data and enable information in the data pipe 15 for the store load instruction.

  Next, the instruction execution control circuit 13 confirms that the memory 17 is not busy, and first reads data from the memory address A for execution of the store load instruction.

  The ECC 18 performs an ECC check on the read data and corrects an error. The modification circuit modifies the corrected data based on the store data (“XXX -----”) and byte enable information (0xE0) stored in the data pipe 15. That is, the data for 3 bytes from the top is rewritten with the contents (“XXX”) for 3 bytes from the top of the store data.

  The ECG 16 adds an error correction code to the rewritten data.

  The instruction execution control circuit 13 writes the data after adding the error correction code to the address A which is the address stored in the address pipe 14.

  The selector 19 returns the modified data as load data to the higher-level device.

  As described above, the first embodiment has an effect of improving the memory throughput performance when a load instruction for the same address is received after a partial store instruction.

  The reason is that, when execution of a partial store instruction and a load instruction for the same address in the memory 17 is necessary, the instruction processing device 10 according to the present embodiment generates one store load instruction based on those instructions, This is because the generated store load instruction is executed. In other words, according to the instruction processing apparatus 10 according to the present embodiment, as shown in the time chart of FIG. 3, the partial store instruction and the load instruction are more partial than the time when the memory 17 is operated individually. According to the store load instruction generated based on the store instruction and the load instruction, the time required for executing the instruction can be shortened as compared with the background art.

DESCRIPTION OF SYMBOLS 10 Instruction processor 11 Store merge control circuit 12 Store load instruction generation circuit 13 Instruction execution control circuit 14 Address pipe 15 Data pipe 16 ECG
17 Memory 18 ECC
19 Selector 110 Information table 111 Address 112 Store data 113 Byte enable information

Claims (8)

A memory whose storage area is determined by an address;
A store merge control circuit that receives a partial store instruction for a specific address of the memory and controls to store the content specified by the partial store instruction;
When the load instruction for the specific address is received after receiving the partial store instruction, the content specified by the partial store instruction stored under the control of the store merge control circuit, the content of the load instruction, And a store load instruction generation circuit for generating a store load instruction based on the instruction processing apparatus. The store merge control circuit includes:
After receiving the partial store instruction and before receiving the load instruction, when the second partial store instruction for the address is received, the contents specified by the second partial store instruction are stored. The instruction processing apparatus according to claim 1, wherein the instruction processing apparatus controls to be stored after being merged with the content specified by the partial store instruction. The store merge control circuit includes:
An address of the memory to be processed by the partial store instruction;
Data having a length accessible to the memory including the contents to be updated by the partial store instruction at a time;
Among the data , information indicating a position to be updated by the partial store instruction,
3. The instruction processing apparatus according to claim 1, wherein the instruction processing apparatus stores the contents based on contents designated by the partial store instruction. The instruction processing apparatus according to claim 1, further comprising an instruction execution control circuit that executes the store load instruction for the memory. The instruction execution control circuit includes:
The busy state of the memory is managed, and when the memory to be processed by the store load instruction is busy, the store load instruction is executed after waiting until the busy state is resolved. The instruction processing apparatus according to claim 4 . In response to a partial store instruction for a specific address of the memory whose storage area is determined by the address, the contents specified by the partial store instruction are stored in the storage device,
After receiving the partial store instruction, when receiving a load instruction for the specific address, based on the content specified by the partial store instruction stored in the storage device and the content of the load instruction, An instruction processing method characterized by generating a store load instruction. When receiving a second partial store instruction for the address after receiving the partial store instruction and before receiving the load instruction, the contents designated by the second partial store instruction are stored in the memory. 7. The instruction processing method according to claim 6, wherein the instruction is stored after being merged with the content specified by the partial store instruction stored in the device. An address of the memory to be processed by the partial store instruction;
Data having a length accessible to the memory including the contents to be updated by the partial store instruction at a time;
Among the data , information indicating a position to be updated by the partial store instruction,
The instruction processing method according to claim 6 or 7, wherein the instruction is stored based on contents designated by the partial store instruction.

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