KR101967857B1 - Processing in memory device with multiple cache and memory accessing method thereof - Google Patents

Abstract

An intelligent semiconductor device is disclosed. The apparatus includes a computing device for performing a computing task; A multiple cache memory forming an upper layer in a memory hierarchy and a memory bank forming a lower layer in the memory hierarchy, wherein the computing device is selectively or simultaneously to the multiple cache memory through a plurality of independent channels Approach

Description

PROCESSING IN MEMORY DEVICE WITH MULTIPLE CACHE AND MEMORY ACCESSING METHOD THEREOF

The present invention relates to an intelligent semiconductor device, and more particularly, to a memory access technology of a computing device inside an intelligent semiconductor device.

In general, an intelligent semiconductor (Processing In Memory (PIM)) is a future semiconductor that adds a processor function to the DRAM (DRAM). In the past, bottlenecks frequently occurred as the processor and memory functions were completely separated and information flowed between them. PIM eliminates the overhead of computational work on the main processor and speeds up processing by eliminating information bottlenecks between the processor and memory.

Instructions processed by intelligent semiconductors are atomic operations that involve more than one memory access and operation.Instead of using a single large memory, it is possible to use several small memory sizes in terms of system performance. Big gain

Accordingly, the recent development of intelligent semiconductors has developed into a multi-processor structure based on single instruction multiple data processing (SIMD), and has developed into a hierarchical memory structure system in which intelligent semiconductors of SIMD structures are connected to a network. .

Intelligent semiconductors use internal or external cache memory to reduce the speed difference between DRAM and computing devices. However, cache memory management policies of existing computer systems have been developed with a focus on improving hit ratio using locality of data, and caches with such management policies and structures have limitations in maximizing performance and power consumption of intelligent semiconductors. .

An object of the present invention for solving the above problems is to provide an intelligent semiconductor that can maximize performance and power consumption according to the management policy and hardware structure of a new cache memory.

The problem to be solved in the present invention is not limited to those mentioned above, other problems not mentioned will be clearly understood by those skilled in the art from the following description.

An intelligent semiconductor device according to an aspect of the present invention for achieving the above object,

An intelligent semiconductor device having a processor function capable of performing a computational operation and a memory function capable of storing data, the apparatus comprising: a computational apparatus configured to perform the computational task; Multiple cache memories forming a higher layer in the memory hierarchy; And a memory bank forming a lower layer in the memory hierarchy, wherein the computing device selectively or simultaneously accesses the multiple cache memories through a plurality of independent channels.

According to another aspect of the present invention, there is provided a memory access method in an intelligent semiconductor device, the method including: receiving, by a computing device, an instruction packet; And selectively or concurrently accessing, by the computing device, multiple cache memories that form an upper layer in the memory hierarchy based on lower fields of an address value in the command packet.

According to the present invention, by changing the cache memory in the intelligent semiconductor to a multiple cache memory structure, it is possible to improve the performance of the intelligent semiconductor and at the same time reduce power consumption. It also solves the problem of sequentially accessing memory for processing a single instruction.

The effects of the present invention are not limited to those mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the following description.

1 is a block diagram schematically illustrating an internal configuration of an intelligent semiconductor device according to an embodiment of the present disclosure.
FIG. 2 is an example illustrating a data structure of an instruction packet input to the intelligent semiconductor device shown in FIG. 1.
3 is a block diagram schematically illustrating an internal configuration of the intelligent semiconductor module illustrated in FIG. 1.
FIG. 4 is a diagram schematically illustrating a method of accessing a multiple cache memory by using the multiplexer shown in FIG. 3.
5 is a graph showing experimental results comparing the performance and power consumption between the conventional intelligent semiconductor device and the intelligent semiconductor device of the present invention.
6 is a flowchart illustrating a memory access method in an intelligent semiconductor device according to an embodiment of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, advantages and features of the present invention, and methods of achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the following embodiments are provided to those skilled in the art to which the present invention pertains. It is merely provided to easily inform the configuration and effects, the scope of the present invention is defined by the description of the claims. Meanwhile, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, “comprises” and / or “comprising” refers to the presence of one or more other components, steps, operations and / or devices in which the mentioned components, steps, operations and / or devices are described. Or does not exclude addition.

1 is a block diagram schematically illustrating an internal configuration of an intelligent semiconductor device according to an embodiment of the present disclosure.

Referring to FIG. 1, an intelligent semiconductor device 100 according to an embodiment of the present disclosure may include a multiple cache memory designed between an arithmetic unit and a memory bank provided therein to maximize performance and power consumption. It is configured to include).

To this end, the intelligent semiconductor device 100 according to an embodiment of the present invention may be configured to include a router 110 and a plurality of intelligent semiconductor modules 120 to 150.

The router 110 may be a kind of communication interface for transferring a memory command packet 10 (hereinafter, referred to as a command packet) input from an external unit (not shown) to the plurality of intelligent semiconductor modules 120 to 150. In addition, the router 110 may function as an arbitration role to exchange global data between the external unit and the plurality of intelligent semiconductor modules 120 to 150.

Each of the plurality of intelligent semiconductor modules 120 to 150 is configured to include multiple caches instead of the existing single data buffer to reduce the speed difference between the computing device and the memory bank provided therein.

As will be described in detail below, the present invention proposes a hardware structure in which each of the plurality of intelligent semiconductor modules 120 to 150 in the intelligent semiconductor device 100 includes multiple cache memories.

The cache memory of a general computer system has been developed to improve the hit ratio of the cache by using the locality of data. However, the command packet 10 processed by the intelligent semiconductor device 100 is mostly composed of atomic operations including a memory access operation. In order for the intelligent semiconductor device 100 to process one command, Repeated memory access is inevitable in order to obtain data necessary for processing the instruction packet 10 as shown in FIG.

Therefore, the use of the multiple cache memory structure disclosed in the present invention, rather than the single data buffer structure used in the memory hierarchy of the existing computer system, is very advantageous in terms of system performance and power consumption.

For reference, the data structure of the instruction packet 10 used in the embodiment of the present invention may be configured with four fields F1, F2, F3, and F4, as shown in FIG. An opcode value indicating the type of operation OP is recorded in the field F1, a second source address value is recorded in the second field F2, and a first source in the third field F3. A value of an address (first source address) is recorded, and a destination address value is recorded in the fourth field F4. Hereinafter, the second to fourth fields are referred to as address fields.

Each of the address fields F2, F3, and F4 may be composed of four fields F5, F6, F7, and F8, as shown in FIG.

The tag value is recorded in the highest field (F5) containing the most significant bit (MSB), and the offset value is recorded in the least significant field (F8) containing the least significant bit (LSB). This is recorded.

An index value is recorded in the upper field F2 adjacent to the highest field F6, and each cache divided into a multiple cache memory structure described below in the lower field F7 adjacent to the lowest field F8. A Cache Number value identifying the memory is recorded.

The combination of the tag value and the index value is used as the address value of the corresponding main memory, that is, the memory bank.

The offset value is determined by the size of a cache block, which is a unit of data movement between the main memory (memory bank) and the cache memory, and the index indicates the number of cache slots in which the cache block is stored. The tag is used to compare the tag value stored in the cache slot to determine if the cache block stored in the cache slot is valid. For reference, the tag value, the offset value, and the index value are technical terms frequently encountered in computer engineering dealing with "cache in a memory hierarchy", and thus, further detailed description thereof will be omitted. Let's do it.

However, a cache number value recorded in the lower field F7 may be set so that the computing device 122 of FIG. 3 can select or simultaneously access the multiple cache memories. Note that it is used as the selection signal of the multiplexer (122-1 in FIG. 3) provided inside the 122.

3 is a block diagram schematically illustrating an internal configuration of one intelligent semiconductor module shown in FIG. 1.

Referring to FIG. 3, the intelligent semiconductor module 120 is configured to include a multiple cache memory structure. In detail, the intelligent semiconductor module 120 includes an arithmetic device 122 and a memory bank 126, and includes a multi-cache memory 124 designed between the arithmetic device 122 and the memory bank 126. It includes more.

Multiple cache memory 124 may be configured to include physically separate (or physically independent) n (n is a natural number of two or more) cache memories (# 0, # 1, ... # n-1).

The multiple cache memory 124 forms an upper layer in the memory hierarchy based on the computing device 122, and the memory bank 126 forms a lower layer in the memory hierarchy.

The arithmetic unit 122 is a device that performs arithmetic operations to process the instruction packet 10 input from an external unit. In the broad sense, the arithmetic unit 122 may be referred to as a processor. It may be called an 'arithmetic unit'.

Although not shown in the drawing, the operation device 122 may be configured to include an accumulator, an adder, a data register, a comparator, a status register, and the like to perform a specific operation.

In addition, the computing device 122 may be configured to include a multiplexer 122-1 to allow selective or simultaneous access to the multiple cache memory 124.

The computing device 122 may be configured to selectively or simultaneously access the multiple cache memories 124 using n independent channels 123 (n physically separated channels). .

It is possible to select or simultaneously access the multiple cache memories 124 by the arithmetic unit 122 by the multiplexer 122-1 provided in the arithmetic unit 122. For example, the multiplexer 122-1 is configured as an output terminal in the computing device 122, the output of the multiplexer 122-1 is designed with n outputs, and then the multiplexer 122-1 is designed. A plurality of cache memories (# 0, # 1, ... #n constituting the multi-cache memory 124 with the computing device 122 by connecting the n outputs of the < RTI ID = 0.0 > n < / RTI > -1) may be connected by independent n channels 123.

Although one multiplexer 122-1 is shown in the drawing, it may be implemented by two or more multiplexers. In addition, although the multiplexer 122-1 provided inside the arithmetic device 122 is illustrated in the drawing, it may be provided externally according to a design. When the multiplexer is provided externally, the input of the multiplexer is connected to the output terminal of the computing device.

As described above, the arithmetic unit 122 uses the n independent channels 123 connected to the multiplexer 122-1 provided therein, and the plurality of cache memories (# 0, # 1, ... #n). -1), the arithmetic unit 122 may selectively or concurrently access the plurality of cache memories # 0, # 1, ... # n-1 according to the operation of the multiplexer 122-1. It is possible.

In detail, the computing device 122 may selectively or simultaneously read / write operations (or Access). This means that the computing device 122 may interleave some or all of the cache memories among the plurality of cache memories # 0, # 1, ... # n-1.

On the other hand, the computing device 122 sequentially reads / writes (accesses) when the data of the currently executed instruction are not distributed in a plurality of cache memories # 0, # 1, ... # n-1. Can be performed.

The plurality of cache memories # 0, # 1, ... # n-1 and the memory bank 126 share one memory bus 125. Here, the memory bank 126 may be, for example, a DRAM bank.

FIG. 4 is a diagram schematically illustrating a method of accessing a multiple cache memory by using the multiplexer shown in FIG. 3.

Referring to FIG. 4, it is assumed that the cache memory is divided into four. Each cache memory (# 0, # 1, # 2, and # 3) is available as an n-way set associative cache, depending on the characteristics of the system to which it applies, and the number of cache memory to be partitioned and each cache memory. The address mapping scheme may vary according to the number of ways of the.

In the memory approach of FIG. 4, a cache number value constituting a lower field F7 is included in each address value (values written in F2, F3, and F4) of the instruction packet 10 shown in FIG. 2. An arithmetic device 122 of FIG. 3 is used as the selection signal 40 of the multiplexer 122-1 for selecting four cache memories # 0, # 1, # 2 and # 3, and an instruction packet ( In the address value F2, F3 and F4 of 10), the tag value and the index value constituting the top field F5 and the top field F6 are respectively the multiplexer 122. Used as input to -1).

Using a cache number value constituting a lower field F7 as a selection signal of the multiplexer within each address value (values written in F2, F3, and F4) of the instruction packet 10, Use of the lower field F7, which has a more frequent change in value than the uppermost field F5 or upper field F6, as a selection signal for distributed loading into several cache memories # 0, # 1, # 2 and # 3. This is because it is preferable. However, this may also be a variety of choices depending on the characteristics of the system.

As described above, the multiple cache memory designed in the intelligent semiconductor 100 of the present invention can read data necessary for processing one instruction at the same time, and by designing a smaller size of each divided cache memory by employing a plurality of divided cache memories. This significantly reduces the power consumption per data access.

In addition, as described above, the multiple cache memory structure designed in the intelligent semiconductor device 100 of the present invention is very effective in terms of system performance and energy saving, even though it is designed as a simple hardware structure.

FIG. 5 shows simulation results of comparing data buffer access time and power consumption with respect to an intelligent semiconductor using an existing data buffer and an exposed PIM using multiple cache memories according to the present invention. It is a bar graph. The parameters for memory were calculated using CACTI 5.3, and the workloads used in the experiment were SPEC CPU2006 and SPEC OMP2012.

As shown in FIG. 5, it can be seen from the simulation results that the intelligent semiconductor designed with multiple cache memories not only maintains existing performance but also provides more performance.

6 is a flowchart illustrating a memory access method in an intelligent semiconductor device according to an embodiment of the present disclosure. Hereinafter, a description overlapping with the description with reference to FIGS. 1 to 5 will be omitted or briefly described.

Referring to FIG. 6, first, in operation S610, a process of receiving a memory command packet 10 (hereinafter, referred to as a command packet) from an external device by an arithmetic device 122 included in the intelligent semiconductor device 100 is performed. Here, as shown in FIG. 2, the command packet 10 is divided into a field F1 in which an opcode value is largely recorded, and fields F2, F3, and F4 in which an address value is recorded, and the fields F2. , F3 and F4 are each divided into a field F5 in which a tag value is recorded, a field F6 in which an index value is recorded, a field F7 in which a cache number value is recorded, and a field F8 in which an offset value is recorded. Can be.

Subsequently, in step S620, the arithmetic unit 122 forms an upper layer in a memory hierarchy based on a lower field of an address value (a lower field in a field in which an address value is recorded) in the command packet. The process of selectively or concurrently accessing memory is performed. That is, the computing device 122 interleaves some or all of the plurality of cache memories constituting the multiple cache memories based on the lower field of the address value.

Although the present invention has been described above with reference to the embodiments, these are merely examples and are not intended to limit the present invention. It will be appreciated that various modifications and applications are not illustrated. For example, each component specifically shown in the embodiment of the present invention can be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

Claims (12)

In an intelligent semiconductor device having a processor function that can perform arithmetic operations and a memory function that can store data,
One computing device that performs the computing task;
A multiple cache memory connected to the one computing device through a plurality of independent channels and forming an upper layer in a memory hierarchy; And
A memory bank forming a lower layer in the memory hierarchy;
The one computing device,
A multiplexer connected to the plurality of independent channels,
The multiplexer selectively or simultaneously accesses the multiple cache memories via a plurality of independent channels, using a select signal of a cache number identifying the multiple cache memories in an instruction packet input from the outside to the computing device. Intelligent semiconductor device that will approach.
The memory system of claim 1, wherein the multiple cache memory includes:
An intelligent semiconductor device comprising a plurality of physically separated cache memory.
delete delete delete The method of claim 1, wherein the cache number is,
And written in a field adjacent to the lowest field in the command packet.
The memory system of claim 1, wherein the multiple cache memories and the memory banks comprise:
An intelligent semiconductor device connected by a common bus.
The apparatus of claim 1, wherein the one computing device includes:
And interleaving the multiple cache memories through a plurality of independent channels.
In a memory access method in an intelligent semiconductor device having a single computing device capable of arithmetic operation and memory forming a lower layer in the memory hierarchy,
Receiving, by the one computing device, an instruction packet; And
Selectively or simultaneously accessing the multiple cache memories forming an upper layer in the memory hierarchy based on a cache number identifying the multiple cache memories in the instruction packet by the one computing device Including,
The selectively or simultaneously approaching step,
Wherein the multiplexer included in the one computing device selectively or simultaneously accesses the multiple cache memories through a plurality of independent channels using the cache number as a selection signal. Memory approach in. delete delete delete

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