JPS62128342A - Memory access control system - Google Patents

Abstract

PURPOSE:To prevent the occurrence of a bus contention by making a multiplexer perform an address supplying, and the output of the valid signals of a bank and a block to each bank according to an input address. CONSTITUTION:The number of buses between a memory MSU and a memory controller MCU is the same as that of ports, and a multiplexer MPX is placed at each block in the MSU. A priority control circuit 205 checks only whether a memory access request at each port can be started up or not, and when it can be started up, it sets a request at a register MSAR, and transmits the memory access request to the MSU. The memory address registers MSAR 206-MSAR209 are used by all of the MSU blocks commonly, and are responded to each of the ports. The memory access request and the address set at the memory address register MSAR are sent to the MSU, and are branched with power gates 210-213, and are sent to memory blocks 218-221. Thereby, the memory access request from each port cannot compete with each other unless it is the access to the same bank.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory access control method for a vector processor, and is intended to achieve memory access without bus contention.

[Conventional technology]

In recent years, demand for vector processors has increased. This stems from the fact that in the fields of science and technology, there is a need for large-scale calculations that cannot be processed by general-purpose super-large computers.

A vector processor processes a large amount of vector data at high speed, and its memory access function is required to have a high-speed arithmetic unit and a high throughput to supply a large amount of data to the arithmetic unit.

Vector data is a collection of data, and each vector data consists of data called multiple elements. In Tsuho's vector processor, one vector data consists of N elements with element numbers θ to N-1, and one vector instruction causes all of these N11l elements to undergo the same processing. This will speed up the process. Each element is typically a piece of floating point, fixed point, or logical data.

Vector processor memory access requires a throughput that cannot be compared to that of ordinary general-purpose computers.
For this purpose, the memory control unit (MC) of the vector processor
(U, which controls memory access priority) is usually subject to special control. For example, in a normal general-purpose computer, even if it is a very large computer, the requests (requests, REQ) that can be accessed by the MCU are IRE in one cycle.
However, in vector processors, it is normal to allow access by multiple requests in l cycle.

In order to allow access by multiple requests in one cycle, it is necessary to have multiple ports in the MCU and to connect multiple address buses and data buses from the MCU to the memory (MSU, main storage unit).

An example is shown in FIG.

In FIG. 2, eight paths are stretched between the MCU and the MSU. These are address buses, but data buses are also not shown in the figure, but each MSU block MSU o ” M
It is attached to S U 7. This memory MSU is a bank (
Bank), the m1 solid becomes 1 block,
There are 8 blocks. Each bank is interleaved, banks 0, 1, 2... ...7 is block 0
．． 1, 2. −・・7 (MSUo, MSUl, MSU
2.・・・・・・M S U t ), bank 8゜9
．． 10. ...15 are blocks 0, 1, 2.・・・
...7, and so on.

A memory access request from a full processor is set in a memory access request register called a port.
Priority control is performed to determine whether memory access is possible. There are four ports 101-104 (these are A-
D system), memory access request (REQA-
D, which contains the address) is queued (REQ key
A-D) are created and taken in sequentially. The access request REQ that is decided to be adopted as a result of priority control is assigned to the register MSAR (main storage address register) connected to the corresponding MSU block according to the address to be accessed.
is set, and a memory access request is sent. For example, the address at 101 of board 1-A is MSU
If bank 0 of MSAH is to be accessed, the address of the port is assigned to bank 0 of MSAH by multiplexer 105.
06 and sent to MSU a. A part of the address sent to the memory block M S U o is branched by the power gate 116 and becomes an address for accessing each bank. The remainder of the address becomes a signal (valid signal) for selecting one of the banks 0 to 8m of the block. Although not shown, store data is also selected corresponding to each MSU block in the same way as addresses, and
Sent to SU block. Data read by MSU access is stored in the selected MSU internal tank MSU.
sent to.

[Problem that the invention seeks to solve]

In this memory access method, the address register MSAR
(or bus), contention is likely to occur and access is delayed;
There is a problem in that the amount of access processing cannot be increased much. For example, the address of a memory access request to a port is M
Bank 0 of S U a is accessed, and the address of the memory access request of port B is M S
If you want to access bank 8 of Uo, the old ^R
At 106, a conflict between ports A and B occurs. Therefore, a memory access request for either port A or port B is given priority processing by the multiplexer 105.
cycle is delayed. In this way, even though the configuration is such that multiple memory accesses can be executed at the same time, and even though the access target (bank) is not busy, the system is delayed for several cycles, resulting in a decrease in system performance. .

Vector processor memory accesses include: ■ Continuous access: accessing data stored at consecutive addresses in memory one after another, and ■ Equally spaced access: accessing data stored at evenly spaced addresses in memory. There are three types: (1) Interval specification access: Access is performed using an indirect address, and the addresses are random and have no regularity. In matrix calculations (hectare a1 calculation), each element in the row is multiplied by each element in the column, but if data is stored in memory in the row direction and the rask scan direction, each element in the row direction The access to retrieve is the above ■, and the access to retrieve each element in the column direction is the above ■.

When access is performed at a sufficient distance through equidistant access, and when access is performed using an indirect one-line fixed address, it is necessary to guarantee the order of stores in a series of store operations.

This is to avoid the problem that when the address of the lower element number and the address of the higher element number are equal and the store order is different, the result of the program will be different. This can be avoided by accessing in numerical order; the access numbered in the order of number 1-A must be activated before the access numbered +1.

The access order is 0.1, 2. . . . is sent to queues 140-143 and ports 101-104 as shown in FIG.

In this figure, EO, El, E2. . . . indicates the memory access request (E indicates the element).

If EO and El both access M S U o, El will not be activated, and E2 will also be delayed because El is not activated. E2 is , even if it accesses a different MSU block than El. thus,
When a conflict occurs in the address register MSAR, accesses are delayed, and if order is guaranteed, accesses that do not conflict are also delayed, resulting in a significant drop in performance. For example, if there is indirect specification access, there are 4 MSU blocks, 4 ports, and there is no order guarantee (there is no mutual interference of accesses between ports), the expected value P for starting accesses of 4 ports is P = 1 + 3/4 + 2/4 + 1/4 = 2
．． 5, and if there is order guarantee, P = 1 + 3/4 + 3/4 x 2/4 +
3/4 x 2/4 x 1/4 = 2.21. Since the maximum expected value is 4, the performance drop due to bus contention is significant, and if the order is guaranteed, the performance will drop even further. Guaranteed access order can be achieved by using multiple ports.
Loading multiple data with one memory access instruction/
As long as store access is performed, it is logically necessary and cannot be stopped.

In order to avoid such performance degradation, the present invention aims to provide a memory access method that does not cause bus contention.

[Means for solving problems]

The present invention utilizes a memory access control method for a vector processor that processes a large amount of data at high speed. A multiplexer is provided to supply addresses to each bank and bank and block valid signals, and multiple memory access request addresses inputted from multiple ports of the memory control device can be handled by the same block, except for those accessing the same bank. The input address is simultaneously input to each of the multiplexers to cause the multiplexer to supply an address to each bank and output a bank and block valid signal in accordance with the input address.

[Effect]

By bringing all the memory access request addresses of each port to the memory block and making it possible to individually set any of the request addresses for all banks using a multiplexer, access conflicts can be avoided unless the same block is accessing the same bank. The throughput of the memory access control system can be significantly improved.

〔Example〕

FIG. 1 shows an embodiment of the present invention, and parts similar to those in FIG. 2 are given the same reference numerals. Memory MSU is still a bank,
It has a block configuration, and the number of blocks is 4, with banks 0.1, 2... ... is block O (MSUo,
218), block 1 (MSU+.

219), Block 2 (MSU2, 220),
It will be placed in... Each block consists of one or several memory cards. The number of paths between the memory MSU and the memory control unit MCU is the same as the number of ports, and a multiplexer MPX is placed in each block of the MSU. The priority control circuit 205 only checks whether the memory access request of each port can be started, and if it is possible to start, sets the request to 'R' in the register MS, and sends the request to the MSU.
Sends a memory access request to. Memory address register (MSAR) 206 to 209 are those MS in Figure 2
It is slightly different from ARI O6~113, and in Figure 2 MS
In contrast to each U block, in FIG. 1, it is common to all MSU blocks and corresponds to each port. Note that this first
The figure also shows only the address system and does not show the data system.

The memory access request and its address sent to the memory address register MSAH are sent to the MSU, branched by power gates 210-213, and sent to memory blocks 218-221. Each memory block 218~
Some of the addresses sent to 221 are sent to multiplexer 21
4 to 217 to the corresponding bank, and the remainder of the address is used for block selection.

Note that there is provided a register for holding the above-mentioned addresses, I/A data, etc. for accessing each bank in one-to-one correspondence with each bank for a period of cycle time, but this is not shown.

As can be seen from FIG. 1, memory access requests from each port do not interfere with each other unless they access the same bank. For example, if each memory access request of port A and port B accesses bank O and bank 4 of memory block 218, both requests can perform memory access together without causing any conflict.

If memory access requests entering different ports access the same bank of the same memory block, this will cause a conflict and the multiplexer MPX will pass the address from each port to the same bank, creating confusion. There is a fear. This point is checked by the priority control circuit 205 of the MCU, and access requests from different ports to the same block and the same bank are given priority processing and one is delayed, and if the access order is guaranteed, other accesses are also delayed simultaneously. Do it like this.

The address for accessing the memory consists of an intra-bank address, a bank address (bank number), a block address (block number), etc. The intra-bank address is input to each bank simultaneously through multiplexer MPX to select a memory cell within the bank. The bank address and block address are decoded in a multiplexer, and the decoded output is supplied to each block and each bank to make the corresponding block and bank valid and the others invalid.

〔Effect of the invention〕

According to this access control method, all memory access request addresses of each port are brought to each memory block,
Since the address of any port can be individually set for all banks using a multiplexer, there is no conflict except for accesses to the same block and the same bank, and access processing performance can be improved. In the conventional method, conflicts occur if the blocks to be accessed are the same, and conflicts occur frequently when the memory capacity of the block is large (large number of banks), but with the method of the present invention, this does not occur and it is possible to use large blocks. I can do it. Further, the number of buses connected from the memory control unit MCU to the memory MSU is equal to the number of blocks in the conventional method, but in the method of the present invention, it is the same number as the number of ports, and this part can be simplified.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional example, and FIG. 3 is an operation explanatory diagram. In the drawing, MSU is memory, MCU is memory control unit, 21
8 to 221 are banks, MPX is a multiplexer, 101
~104 are ports.

Claims (1)

[Claims] In a memory access control method for a vector processor that processes large amounts of data at high speed, each block of memory is divided into many banks and interleaved to form a plurality of blocks. A multiplexer is provided to supply addresses to banks and bank and block valid signals, and multiple memory access request addresses input from multiple ports of the memory control device are handled by the same block, except for those accessing the same bank. A memory access control system characterized in that an input is simultaneously input to each of the multiplexers to cause the multiplexer to supply an address to each bank and output a bank and block valid signal in accordance with the input address.