JPS5960785A - Selection system for function block substrate - Google Patents

Selection system for function block substrate

Info

Publication number
JPS5960785A
JPS5960785A JP57169521A JP16952182A JPS5960785A JP S5960785 A JPS5960785 A JP S5960785A JP 57169521 A JP57169521 A JP 57169521A JP 16952182 A JP16952182 A JP 16952182A JP S5960785 A JPS5960785 A JP S5960785A
Authority
JP
Japan
Prior art keywords
address signal
memory
card
slot
cards
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57169521A
Other languages
Japanese (ja)
Other versions
JPS6243273B2 (en
Inventor
Tadashi Kaneko
正 金古
Toru Otsu
徹 大津
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57169521A priority Critical patent/JPS5960785A/en
Publication of JPS5960785A publication Critical patent/JPS5960785A/en
Publication of JPS6243273B2 publication Critical patent/JPS6243273B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store

Abstract

PURPOSE:To save the labor exchange of cards and to reduce the errors generated with exchange of cards by comparing a slot address signal with a substrate selecting address signal and permitting an access for a function block substrate with which the coincidence is obtained between both above-mentioned address signals. CONSTITUTION:A binary comparator of each memory compares a slot address signal with 4 bits (substrate selecting address signal) of a memory access address signal of 16 bits sent from the CPU side. Then the binary comparator enables the access of own memory card when the coincidence is obtained with above- mentioned comparison and has an access of each memory element within the own memory card by means of lower 12 bits of a memory access address. The memory card can be simply exchanged by just replacing it, and this eliminates completely the address setting of the card when the card is exchanged. In other words, an operation exactly equal to that so far carried out is effective despite replacement between memory cards CD0 and CD1. As a result, no address setting error is produced when the cards are exchanged.

Description

【発明の詳細な説明】 (1)発明の技術分野 本発明はパックパネルに接続された機能ブロック基板の
選択システムに関する。
DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a selection system for a functional block board connected to a pack panel.

(2)従来技術と問題点 同一種類の複数のメモリカード、I10制御用カード等
の機能ブロック基板(以下単にカードと称する)をパッ
クパネルに接続し、このうちの1つのカードをCPU側
から選択する場合、従来は次の如き方法が行われていた
。即ち、カード内にデコーダを設け、CPU側からパッ
クパネルを介して送り込まれるアドレスをデコードし、
そのデコード出力が自己のカードに相当するものである
ときに自己のカードのアク−ヒスをイネーブルとするも
のである。
(2) Conventional technology and problems Connect multiple memory cards of the same type, functional block boards (hereinafter simply referred to as cards) such as I10 control cards, etc. to the pack panel, and select one of these cards from the CPU side. In this case, the following methods were conventionally used. That is, a decoder is provided inside the card, and the address sent from the CPU side via the pack panel is decoded.
When the decoded output corresponds to the own card, the activation of the own card is enabled.

しかしながらこのような従来技術によると、各カード毎
に自己のアドレスをあらかじめ設冗しておく必要がある
。例えば、カードを・々ックノJ?ネルへ実装する際に
カード内デコーダの複数出力のうちの1本をピン等で短
絡させることにより自己のアドレス設定をしなくてはな
らない。
However, according to such conventional technology, it is necessary to provide each card with its own address in advance. For example, what about cards? When mounting the card on a channel, it is necessary to set its own address by short-circuiting one of the multiple outputs of the in-card decoder with a pin or the like.

このようにカード毎にアドレス設定をする従来技術によ
ると、カードを交換する際に新しいカードに同一のアド
レス設定を行なわなくてはならず、これは交換作業が煩
雑となるばかシでなく、アドレス設定の誤υを引き起す
恐れが多分にあった。
According to the conventional technology that sets the address for each card in this way, when exchanging cards, the same address must be set on the new card. There was a high risk of causing a setting error υ.

(3)発明の目的 従って本発明は従来技術の上述の問題点を解決するもの
であり、本発明の目的は、カード交換時の手間が簡便で
ありしかも交換時の誤9の発生しにくいカード(機能ブ
ロック基板)選択システムを提供することにある。
(3) Purpose of the Invention Therefore, the present invention solves the above-mentioned problems of the prior art, and an object of the present invention is to provide a card that is easy to use when exchanging cards and is less likely to cause errors when exchanging cards. (Functional block board) The purpose is to provide a selection system.

(4)発明の構成 上述の目的を達成する本発明の特徴は、同一種類の複数
の機能ブロック基板と、該各機能ブロック基板がそれぞ
れ挿入接続されるスロットを有するパックノJ?ネルと
、該パックパネルの各スロットに各スロット別にあらか
じめ設定した固定のスロットアドレス信号を供給する手
段と、該パックパネルの各スロットに選択すべき機能ブ
ロック基板を表わす基板選択用アドレス信号を供給する
手段とを備え、一方、前記各機能ブロック基板に、接続
したスロットから与えられる前記スロットアドレス信号
と前記基板選択用アドレス信号とを比較して両者の一致
を検出する一致検出回路を設け、一致が検出された機能
ブロック基板をアクセス可能とするようにしたことKあ
る。
(4) Structure of the Invention The features of the present invention that achieve the above-mentioned objects include a plurality of functional block boards of the same type and slots into which the respective functional block boards are inserted and connected. means for supplying a fixed slot address signal preset for each slot to each slot of the pack panel, and supplying a board selection address signal representing a functional block board to be selected to each slot of the pack panel. and a coincidence detection circuit for comparing the slot address signal applied from the connected slot with the board selection address signal and detecting a coincidence between the two. In some cases, the detected functional block board is made accessible.

(5)発明の実施例 以下図面を用いて本発明の詳細な説明する。(5) Examples of the invention The present invention will be described in detail below using the drawings.

図は本発明の一実施例の一部構成を表わしており、同図
において、BPはパックパネル、5LTo。
The figure shows a partial configuration of an embodiment of the present invention, and in the figure, BP is a pack panel and 5LTo.

5LT5.5LT2はパックパネルBpに設けられたス
ロット、CD、 l CD、 l CDよけ各スロット
にそれぞれ挿入接続された機能プロ、り基板、即ちカー
ドである。
5LT5.5LT2 is a functional board, that is, a card, which is inserted and connected to each of the slots provided in the pack panel Bp, namely, the CD, lCD, and lCD cover slots.

不実施例においてカードCD6 # CD/ a CD
2はそれぞれが多数のメモリIC素子を実装したメモリ
カードである。各メモリカードCD6 r CD7 p
 CDよは同一種類のものであり、互いに全く同じ構成
となっている。なお、図忙は3つのメモリカード及びス
ロット1が表わされていないが実際には多数あるものと
する。
Card CD6 #CD/a CD in non-example
2 are memory cards each having a large number of memory IC elements mounted thereon. Each memory card CD6 r CD7 p
The CDs are of the same type and have exactly the same configuration. Although three memory cards and slot 1 are not shown in the figure, it is assumed that there are actually many.

図において、さらにADRFiCPU側に接続されルア
トレス線であり、例えば16ビツトのアドレス信号が各
スロッ)K共通に送られる。また、5ADo、 5AD
1.5AD2は各スロット5LTol SI、T、 。
In the figure, a route address line is further connected to the ADRFi CPU side, and, for example, a 16-bit address signal is commonly sent to each slot (K). Also, 5ADo, 5AD
1.5AD2 is each slot 5LTol SI,T, .

5LT2毎にそれぞれ設定された一足のスロットアドレ
ス信号を発生するスロットアドレス信号発生回路であυ
、それぞれ互いに異なる4ビツトの2値信号を発生する
。例えば、5ADoはoooo’。
This is a slot address signal generation circuit that generates one set of slot address signals for each 5LT2.
, generate mutually different 4-bit binary signals. For example, 5ADo is oooo'.

SADは0001”、5AD2は0010’のスロット
アドレス信号をそれぞれ発生する。
SAD generates slot address signals of 0001'' and 5AD2 generates slot address signals of 0010'.

一方、メモリカード側には、各スロットにおいて前述の
アドレス線ADRK接続される16ビツト分の接続端子
及び接続線各スロットにおいてスロットアドレス信号発
生回路に接続される4ビツト分の接続端子及び接続線、
その他図示しないデータの入出力用端子等が設けられて
いる。さらに、各メモリカードSLT  、 SLT、
  、 SLT、には16ビットのメモリアクセス用ア
ドレスのうちの上位4ビツトのアドレスが送り込まれる
パイナリコンノぐレータC0Mo、 COM、  、 
C0M2が設けられている。これらのバイナリコン・臂
レータにはさらに、前述の4ビツトのスロットアドレス
信号が送υ込まれるように構成されている。各フン/9
レータC0Mo、 C0M1. C0M2の出力は、そ
れぞれのメモリカードのアクセスイネーブル端子に接続
されている。
On the other hand, on the memory card side, there are connection terminals and connection lines for 16 bits connected to the aforementioned address line ADRK in each slot, connection terminals and connection lines for 4 bits connected to the slot address signal generation circuit in each slot,
Other data input/output terminals (not shown) are also provided. Furthermore, each memory card SLT, SLT,
, SLT, are pinary controllers C0Mo, COM, , to which the upper 4 bits of the 16-bit memory access address are sent.
C0M2 is provided. These binary converters are further configured to receive the aforementioned 4-bit slot address signal. Each hun/9
Raters C0Mo, C0M1. The output of C0M2 is connected to the access enable terminal of each memory card.

斯くして、各メモリカードのパイナリコンノぜレータは
、CPU側から送られてくる16ビツトのメモリアクセ
ス用アドレス信号のうちの4ビツト(基板選択用アドレ
ス信号)と前述のスロットアドレス信号とを比較し、一
致した際に自己のメモリカードのアクセスをイネーブル
とし、メモリアクセス用アドレスの下位12ビツトによ
υ、その自己のメモリカード内の各メモリ素子のアクセ
スを行う。
In this way, the pinary converter of each memory card compares 4 bits (board selection address signal) of the 16-bit memory access address signal sent from the CPU side with the slot address signal described above. , when they match, access to its own memory card is enabled, and each memory element in its own memory card is accessed according to the lower 12 bits of the memory access address.

本実施例の如く構成することにより、メモリカードの交
換は単にカードの差し換えを行うだけで良く交換時にカ
ードのアドレス設定を行う必要が全くない。例えば図の
例ではメモリカードCDoとCD、とを入れ換えても今
までと全く同じ動作で行われる。従ってカード交換時の
手間が大幅に省け、また交換時のアドレス設定誤りも皆
無となる。
By configuring as in this embodiment, memory cards can be replaced by simply replacing the cards, and there is no need to set the address of the card at the time of replacement. For example, in the example shown in the figure, even if the memory cards CDo and CD are replaced, the same operation as before is performed. Therefore, the time and effort required when exchanging cards is greatly reduced, and there is no possibility of incorrect address setting when exchanging cards.

(6)発明の効果 以上詳細に説明したように本発明によれば、カード側に
は一致検出回路だけを設け、バックパネル側の各スロッ
ト毎に定めた一定のスロットアドレス信号と選択すべき
カードを表わすカード選択用アドレス信号との一致を上
記一致検出回路で検出するように構成しているため、カ
ード交換時に手間がかからず、また交換時のアドレス設
定誤シが全く発生しないという格別の効果が得られる。
(6) Effects of the Invention As explained in detail above, according to the present invention, only a coincidence detection circuit is provided on the card side, and a fixed slot address signal determined for each slot on the back panel side and a card to be selected are provided. Since the above-mentioned match detection circuit detects the match with the card selection address signal representing Effects can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

図は本発明の一実施例の一部構成図である。 B P−・・パックパネル、5LTo、 SLT、  
、 SLT、2・・・スロット、CD 、CD11CD
2・・・カード、ADR・・・アドレス線、5ADo、
 SAD、  、 5AD2−・・スロットアドレス信
号発生回路、C0Mo、 COM、  、 C0M2・
・・バイナリコン・ぐレータ。
The figure is a partial configuration diagram of an embodiment of the present invention. B P-...Pack panel, 5LTo, SLT,
, SLT, 2...slot, CD, CD11CD
2...Card, ADR...Address line, 5ADo,
SAD, , 5AD2-...Slot address signal generation circuit, C0Mo, COM, , C0M2-
...binary converter.

Claims (1)

【特許請求の範囲】[Claims] 1、同一種類の複数の機能ブロック基板と、該各機能ブ
ロック基板がそれぞれ挿入接続されるスロットを有する
パックノやネルと、該パックパネルの各スロットに各ス
ロット別にあらかじめ設定した固定のスロットアドレス
信号を供給する手段と、該パック・9ネルの各スロット
に選択すべき機能ブロック基板を表わす基板選択用アド
レス信号を供給する手段とを備え、一方、前記各機能ブ
ロック基板に、接続したスロットから与えられる前記ス
ロットアドレス信号と前記基板選択用アドレス信号とを
比較して両者の一致を検出する一致検出回路を設け、一
致が検出された機能ブロック基板をアクセス可能とする
ようにしたことを特徴とする機能ブロック基板選択シス
テム。
1. A plurality of functional block boards of the same type, a pack panel or panel having slots into which each functional block board is inserted and connected, and a fixed slot address signal set in advance for each slot in each slot of the pack panel. supplying means, and means for supplying a board selection address signal representing a functional block board to be selected to each slot of the pack/9 channel; A function characterized in that a coincidence detection circuit is provided that compares the slot address signal and the board selection address signal to detect a match between the two, and a functional block board for which a match is detected can be accessed. Block board selection system.
JP57169521A 1982-09-30 1982-09-30 Selection system for function block substrate Granted JPS5960785A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57169521A JPS5960785A (en) 1982-09-30 1982-09-30 Selection system for function block substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57169521A JPS5960785A (en) 1982-09-30 1982-09-30 Selection system for function block substrate

Publications (2)

Publication Number Publication Date
JPS5960785A true JPS5960785A (en) 1984-04-06
JPS6243273B2 JPS6243273B2 (en) 1987-09-12

Family

ID=15888042

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57169521A Granted JPS5960785A (en) 1982-09-30 1982-09-30 Selection system for function block substrate

Country Status (1)

Country Link
JP (1) JPS5960785A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62114053A (en) * 1985-11-13 1987-05-25 Yokogawa Electric Corp Information processor
JPS63298463A (en) * 1987-05-28 1988-12-06 Fanuc Ltd System bus system
JPS6488862A (en) * 1987-09-30 1989-04-03 Sony Corp Printed board circuit
JPH02112047A (en) * 1988-10-21 1990-04-24 Nec Corp Unit address setting system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54127632A (en) * 1978-03-27 1979-10-03 Nec Corp Memory unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54127632A (en) * 1978-03-27 1979-10-03 Nec Corp Memory unit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62114053A (en) * 1985-11-13 1987-05-25 Yokogawa Electric Corp Information processor
JPS63298463A (en) * 1987-05-28 1988-12-06 Fanuc Ltd System bus system
JPS6488862A (en) * 1987-09-30 1989-04-03 Sony Corp Printed board circuit
JPH02112047A (en) * 1988-10-21 1990-04-24 Nec Corp Unit address setting system

Also Published As

Publication number Publication date
JPS6243273B2 (en) 1987-09-12

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