CN112769457A - Cable testing device and cable testing method - Google Patents
Cable testing device and cable testing method Download PDFInfo
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- CN112769457A CN112769457A CN202011632405.9A CN202011632405A CN112769457A CN 112769457 A CN112769457 A CN 112769457A CN 202011632405 A CN202011632405 A CN 202011632405A CN 112769457 A CN112769457 A CN 112769457A
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Abstract
The application discloses a cable test device and a cable test method. The apparatus comprises: the main control equipment is used for sending a first control instruction; the slave control equipment is in communication connection with the master control equipment and comprises a first retiming chip, a test code generator and a tested active cable, wherein the first retiming chip is used for receiving a first control instruction and starting the test code generator in the first retiming chip in response to the first control instruction so as to send the test code stream of the preset code pattern generated by the test code generator to the tested active cable; and responding to the first control instruction to start an error code detector in the first retiming chip so as to detect the error code rate when the tested active cable transmits the test code stream. Through the method and the device, the problem that the data transmission performance of the high-speed active cable is difficult to detect in the related art is solved.
Description
Technical Field
The application relates to the technical field of error code detection, in particular to a cable testing device and a cable testing method.
Background
With the increase of the transmission rate of the high-speed serial interface, the transmission loss of the PCB medium is also increased, and the conventional Direct connection Cable (DAC) cannot gradually meet the data transmission requirement due to the large loss in the process of transmitting high-speed data. In order to meet the requirement of high-speed and long-distance data transmission, more and more Active Electrical Cables (AEC) are introduced in the related art, and a retiming chip is integrated in the Active cable to compensate for loss in data transmission, so as to meet the requirement of data transmission.
However, in cable detection, for DAC, in the related art, a simple error detector is often used to transmit a universal PRBS (Pseudo Random Bit Sequence) to perform a loopback test of the cable, and the high-speed signal transmission performance of the cable is confirmed by the error rate. For the AEC, due to the fact that a retiming chip is integrated in the cable and has a specific encoding rule for a specific protocol, a universal PRBS and other high-speed code patterns cannot be directly transmitted through the AEC, and difficulty is brought to performance verification and large-scale testing of the AEC.
Aiming at the problem that the data transmission performance of a high-speed active cable is difficult to detect in the related art, an effective solution is not provided at present.
Disclosure of Invention
The application provides a cable test device and a cable test method, which aim to solve the problem that the data transmission performance of a high-speed active cable is difficult to detect in the related technology.
According to one aspect of the present application, a cable testing device is provided. The cable test apparatus includes: the master control equipment is used for sending a first control instruction, wherein the first control instruction is used for instructing the start of a test code generator and an error code detector in a first retiming chip in the slave control equipment; the slave control equipment is in communication connection with the master control equipment and comprises a first retiming chip, a test code generator and a tested active cable, wherein the first retiming chip is used for receiving a first control instruction and starting the test code generator in the first retiming chip in response to the first control instruction so as to send the test code stream of the preset code pattern generated by the test code generator to the tested active cable; and responding to the first control instruction to start an error code detector in the first retiming chip so as to detect an error code rate when the tested active cable transmits the test code stream, wherein the tested active cable is provided with a second retiming chip and is used for transmitting the code stream of the preset code pattern, and the error code detector is used for detecting the error code rate when the tested equipment transmits the code stream of the preset code pattern.
Optionally, the first retiming chip further includes a data transmitting circuit, an input end of the data transmitting circuit is in communication connection with the test code generator, and an output end of the data transmitting circuit is connected with the first end of the tested active cable, and is configured to receive and convert the test code stream, and transmit the converted test code stream to the tested active cable; the first retiming chip further comprises a data receiving circuit, an input end of the data receiving circuit is connected with a second end of the tested active cable, an output end of the data receiving circuit is in communication connection with the error code detector, and the data receiving circuit is used for receiving and converting a target code stream output after the tested active cable transmits the test code stream and sending the target code stream to the error code detector.
Optionally, a second retiming chip is disposed in the active cable to be tested, the first retiming chip and the second retiming chip are of the same type, and both the first retiming chip and the second retiming chip are timer chips.
Optionally, the master control device communicates with the first retiming chip via an I2C bus.
Optionally, the preset code pattern is a code pattern defined by a preset protocol; the preset protocol is a USB3.2 protocol, and the preset code pattern is a CP9 code pattern defined by the USB3.2 protocol.
According to another aspect of the application, a cable testing method is provided, which is applied to any one of the above-mentioned cable testing devices. The method comprises the following steps: after receiving a first control instruction sent by the master control device, a first retiming chip in the slave control device controls a test code generator and an error code detector in the first retiming chip to start; generating a test code stream of a preset code pattern through a test code generator, and sending the test code stream to a tested active cable, wherein a second retiming chip is arranged in the tested active cable, and the first retiming chip and the second retiming chip are the same in type; and receiving a target code stream obtained after the tested active cable transmits the test code stream, and sending the target code stream to an error code detector so as to detect the error code rate when the tested active cable transmits the test code stream.
Optionally, before the second retiming chip in the active cable under test receives the test code stream, the transparent transmission control circuit in the second retiming chip is controlled to start by receiving a second control instruction sent by the main control device.
Optionally, the generating a test code stream of the preset code pattern by the test code generator, and sending the test code stream to the tested active cable includes: generating a test code stream of a preset code pattern through a test code generator, and sending the test code stream to a data sending circuit in a first retiming chip; and coding the test code stream through the data transmitting circuit, converting the coded code stream into a serial code stream, and transmitting the serial code stream to the tested active cable.
Optionally, receiving a target code stream obtained after the tested active cable transmits the test code stream, and sending the target code stream to the error code detector, so as to detect an error code rate when the tested active cable transmits the test code stream, including: receiving a target code stream through a data receiving circuit in a first retiming chip, performing clock data recovery on the target code stream through the data receiving circuit, converting a code stream obtained after recovery into a serial code stream, and decoding the serial code stream; and sending the decoded code stream to an error code detector, and determining an error rate based on the decoded code stream through the error code detector.
Optionally, sending the decoded code stream to an error detector, and determining, by the error detector, an error rate based on the decoded code stream includes: and comparing the decoded code stream with a stored preset code stream of a preset code pattern, and generating an error rate according to a comparison result.
According to the method, the master control equipment is adopted and used for sending a first control instruction, wherein the first control instruction is used for indicating and controlling the starting of a test code generator and an error code detector in a first retiming chip in the slave control equipment; the slave control equipment is in communication connection with the master control equipment and comprises a first retiming chip, a test code generator and a tested active cable, wherein the first retiming chip is used for receiving a first control instruction and starting the test code generator in the first retiming chip in response to the first control instruction so as to send the test code stream of the preset code pattern generated by the test code generator to the tested active cable; and responding to the first control instruction to start the error code detector in the first retiming chip so as to detect the error rate when the tested active cable transmits the test code stream, wherein the second retiming chip is arranged in the tested active cable, the tested active cable is used for transmitting the code stream of the preset code pattern, and the error code detector is used for detecting the error rate when the tested device transmits the code stream of the preset code pattern, so that the problem that the data transmission performance of the high-speed active cable is difficult to detect in the related technology is solved. The test code generator and the error code detector in the first retiming chip in the slave control device are started through the master control device, the active cable used for transmitting the code stream of the preset code pattern is detected, and therefore the effects of improving the efficiency and accuracy of detecting the data transmission performance of the high-speed active cable and reducing the detection cost are achieved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
FIG. 1 is a schematic view of a cable testing device provided according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a first retiming chip of a cable test equipment and a second retiming chip in an active cable under test provided in accordance with an embodiment of the present application;
FIG. 3 is a schematic diagram illustrating operation of a second retiming chip in an active cable under test according to an embodiment of the present disclosure;
FIG. 4 is an operational schematic diagram of a first retiming chip in a cable test equipment provided in accordance with an embodiment of the present application;
FIG. 5 is a flow chart of a cable testing method provided according to an embodiment of the present application;
FIG. 6 is a first schematic diagram of testing an active cable according to a cable testing method provided in an embodiment of the present application;
fig. 7 is a second schematic diagram of testing an active cable according to the cable testing method provided in the embodiment of the present application.
Detailed Description
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be used. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In order to solve the problem that it is difficult to detect the data transmission performance of the high-speed active cable in the related art, the following methods appear in the related art: the data transmission performance of the active cable is tested by adopting equipment for testing a specific protocol of the retiming chip, but the equipment is complex in structure and expensive, and the large-scale test requirement of the active cable is difficult to meet.
Based on this, the present application intends to provide a solution to the above technical problem, the details of which will be explained in the following embodiments.
For convenience of description, some terms or expressions referred to in the embodiments of the present application are explained below:
DAC: direct Attach Cable, Direct Cable.
AEC: active Electrical Cables, Active Cables.
PRBS: pseudo Random Bit Sequence, Pseudo Random binary Sequence.
BIST: the build-in Self Test is a technique for reducing the dependence on external Test equipment when a circuit is tested by implanting a circuit module for providing a circuit Self-Test function in the circuit design.
The embodiment of the present application further provides a cable testing apparatus, and it should be noted that the cable testing apparatus according to the embodiment of the present application may be used to execute the method for testing a cable provided in the embodiment of the present application. The cable testing device provided by the embodiment of the application is introduced below.
According to an embodiment of the present application, a cable testing device is provided.
FIG. 1 is a schematic view of a cable testing device according to an embodiment of the present application. As shown in fig. 1, the apparatus includes: a master control device 10 and a slave control device 20.
The master control device 10 is configured to send a first control instruction, where the first control instruction is used to instruct the test code generator and the error detector in the first retiming chip in the slave control device 20 to start.
Specifically, the main control device 10 may be a single chip microcomputer, instruction data (for example, first instruction data corresponding to a first control instruction) corresponding to the control instruction is stored in a memory of the single chip microcomputer, the single chip microcomputer is connected to an upper computer through a serial port line, and the single chip microcomputer is controlled by the upper computer to convert the instruction data into the control instruction and send the control instruction.
The master control device 10 sends a first control instruction to the slave control device 20, and optionally, in the cable test device provided in the embodiment of the present application, the master control device 10 communicates with the first retiming chip through the I2C bus.
Specifically, the master control device 10 sends a first control instruction to a first retiming chip in the slave control device 20 through the I2C bus to enable a test code generator and an error detector in the first retiming chip.
The slave control device 20 is in communication connection with the master control device 10, and includes a first retiming chip, configured to receive a first control instruction, and start a test code generator in the first retiming chip in response to the first control instruction, so as to send a test code stream of a preset code pattern generated by the test code generator to the active cable to be tested; and responding to the first control instruction to start an error code detector in the first retiming chip so as to detect an error code rate when the tested active cable transmits the test code stream, wherein the tested active cable is provided with a second retiming chip and is used for transmitting the code stream of the preset code pattern, and the error code detector is used for detecting the error code rate when the tested equipment transmits the code stream of the preset code pattern.
It should be noted that, the retiming chip is integrated in the active cable to be tested to compensate the high-speed code stream of the preset code pattern defined by the preset protocol, and the code stream of the generic PRBS code pattern of the error code detector in the related art, which is not the code stream of the code pattern defined by the preset protocol, cannot transmit the active cable to be tested, and therefore cannot test the transmission performance of the active cable to be tested.
The cable test device provided by the embodiment of the application is used for sending a first control instruction through the master control device 10, wherein the first control instruction is used for instructing the start of a test code generator and an error code detector in a first retiming chip in the slave control device 20; the slave control device 20 is in communication connection with the master control device 10, and includes a first retiming chip, configured to receive a first control instruction, and start a test code generator in the first retiming chip in response to the first control instruction, so as to send a test code stream of a preset code pattern generated by the test code generator to the active cable to be tested; and responding to the first control instruction to start the error code detector in the first retiming chip to detect the error rate when the tested active cable transmits the test code stream, wherein the tested active cable is provided with the second retiming chip, the tested active cable is used for transmitting the code stream of the preset code pattern, and the error code detector is used for detecting the error rate when the tested device transmits the code stream of the preset code pattern, thereby solving the problem that the data transmission performance of the high-speed active cable is difficult to detect in the related technology.
In order to implement sending of the test code stream and receiving of the code stream output by the tested cable, optionally, in the cable test device provided in the embodiment of the present application, the first retiming chip further includes a data sending circuit, an input end of the data sending circuit is in communication connection with the test code generator, and an output end of the data sending circuit is connected with the first end of the tested active cable, and is configured to receive and convert the test code stream, and send the converted test code stream to the tested active cable; the first retiming chip further comprises a data receiving circuit, an input end of the data receiving circuit is connected with a second end of the tested active cable, an output end of the data receiving circuit is in communication connection with the error code detector, and the data receiving circuit is used for receiving and converting a target code stream output after the tested active cable transmits the test code stream and sending the target code stream to the error code detector.
Specifically, the data sending circuit may include an encoding circuit, configured to encode a test code stream of a preset code pattern generated by the test code generator to obtain an encoded code stream; the data sending circuit also comprises a first shift register which is connected with the coding circuit and used for converting the coded code stream into a serial code stream to be sent to the tested active cable.
The data receiving circuit comprises an equalizing circuit and a control circuit, wherein the equalizing circuit is used for compensating signal attenuation in a target code stream to obtain a compensated code stream; the data receiving circuit also comprises a clock data recovery circuit which is connected with the equalization circuit and used for carrying out clock recovery and data recovery on the compensated code stream to obtain a recovered code stream; the data receiving circuit also comprises a second shift register which is connected with the clock data recovery circuit and is used for converting the recovered code stream into the parallel code stream; in addition, the data receiving circuit also comprises a decoding circuit which is used for decoding the parallel code stream to obtain a decoded code stream and inputting the decoded code stream into the error code detector.
In order to implement that the active cable to be tested is used for transmitting a code stream of a preset code pattern, and at the same time, the test code generator in the first retiming chip generates a test code stream of the preset code pattern, and the error code detector detects an error code rate of the code stream of the preset code pattern, optionally, in the cable test device provided in the embodiment of the present application, the first retiming chip and the second retiming chip are of the same type, and both the first retiming chip and the second retiming chip are retimer chips.
Specifically, a timer chip arranged in the active cable to be tested at least comprises a data receiving circuit, a transparent transmission control circuit and a data sending circuit so as to compensate the loss of the transmitted high-speed data with the preset code pattern. In addition, in order to reduce the dependence on external test equipment when testing the chip function in the production stage of the timer chip, the timer chip also has the BIST function, the BIST function refers to a technology of implanting a circuit module for providing a chip self-test function in the chip design, and in order to realize the error detection of the timer chip in the production stage of the timer chip, as shown in fig. 2, besides a data receiving circuit, a transparent transmission control circuit and a data transmitting circuit, at least a test code generator and an error detector can be implanted in the chip of the timer.
Specifically, a data receiving circuit and a data sending circuit in the timer chip are analog circuits, a transparent transmission control circuit, a test code generator and an error code detector are digital circuits, and the timer chip can receive an instruction of external control equipment so as to enable the digital circuits in the chip. As shown in fig. 3, when the timer chip normally works in the active cable to be tested, the transparent transmission control circuit is enabled, the transparent transmission mode is turned on, after the data receiving circuit receives the high-speed serial data of the preset code pattern, the transparent transmission control circuit performs data recovery (specifically including protocol and logic analysis and state confirmation) on the data of the preset code pattern, and sends out the recovered data through the data sending circuit, so as to realize the transmission of the data of the preset code pattern. And the error code test of the retimer chip in the production stage, that is, in the error code test before the retimer chip is implanted into the cable, as shown in fig. 4, the test code generator and the error code detector can be enabled, the BIST error code detection mode is started, and the error code test of the retimer chip is realized.
Therefore, the cable testing device in the embodiment of the present application, when the slave control device 20 is provided with the first retiming chip having the same type as the second retiming chip in the active cable to be tested, specifically, when the cable testing device is in operation, the master control device 10 enables the test code generator and the error detector in the first retiming chip to start the BIST error detection mode of the chip, since the first retiming chip in the slave control device 20 and the second retiming chip in the active cable to be tested have the same type, the test code stream of the preset code pattern is generated and sent out by the test code generator of the first retiming chip, the active cable to be tested can transmit the test code stream of the preset code pattern, and further, the error detector in the first retiming chip receives the code stream output by the active cable to be tested.
Through this application embodiment, adopt with being surveyed the retiming chip in the active cable the same to the realization can be on the volume production line of active cable to the test of being surveyed the transmission performance of active cable, carries out multichannel mistake test simultaneously, improves the error code efficiency of software testing of cable, reduces test cost.
The timer chip may process data of different code patterns, and optionally, in the cable test device provided in the embodiment of the present application, the preset code pattern is a code pattern defined by a preset protocol, the preset protocol is a USB3.2 protocol, and the preset code pattern is a CP9 code pattern defined by the USB3.2 protocol.
Specifically, the CP9 code pattern defined by the USB3.2 protocol is a 10Gbps code stream, the active cable to be tested may be a cable including a USB3.2 retiming chip, in the transparent transmission mode, the active cable to be tested may transmit the USB3.2 test code pattern CP9, the slave device 20 in the cable test device also has a USB3.2 retiming chip, and in the error code detection mode, the transmission of the code stream of the CP9 code pattern and the error code detection of the code stream of the CP9 code pattern are performed, thereby implementing the test of the transmission performance of the high-speed active cable.
Fig. 5 is a flowchart of a cable testing method according to an embodiment of the present application, which is applied to any one of the cable testing apparatuses. As shown in fig. 5, the method comprises the steps of:
step S502, after the first retiming chip in the slave control device receives the first control instruction sent by the master control device, the test code generator and the error code detector in the first retiming chip are controlled to start.
Specifically, the master control device may be a single chip, the slave control device includes a first retiming chip, and after the first retiming chip receives the first control instruction, the test code generator and the error code detector in the chip are enabled to start an error code detection mode of the first retiming chip.
Step S504, generating a test code stream of a preset code pattern through the test code generator, and sending the test code stream to the tested active cable, wherein the tested active cable is provided with a second retiming chip, and the first retiming chip and the second retiming chip are of the same type.
Specifically, in order to realize that the tested active cable transmits the code stream of the preset code pattern, the test code generator in the first retiming chip generates the test code stream of the preset code pattern, and the error code detector detects the error code rate of the code stream transmitting the preset code pattern, the first retiming chip which is the same as the second retiming chip in the tested active cable is adopted to construct the slave control device.
It should be noted that the first retiming chip in the slave control device and the second retiming chip in the active cable under test are the same type, and each of them at least includes a data transmitting circuit, a data receiving circuit, a transparent transmission control circuit, a test code generator and an error code detector, but the circuit modules enabled by the first retiming chip and the second retiming chip are different, and the operation modes are different.
Optionally, in the cable testing method provided in this embodiment of the present application, generating a test code stream of a preset code pattern by using the test code generator, and sending the test code stream to the tested active cable includes: generating a test code stream of a preset code pattern through a test code generator, and sending the test code stream to a data sending circuit in a first retiming chip; and coding the test code stream through the data transmitting circuit, converting the coded code stream into a serial code stream, and transmitting the serial code stream to the tested active cable.
Specifically, after generating a test code stream of a preset code pattern, an error detector in a first retiming chip sends the test code stream to a data sending circuit in the first retiming chip, wherein the data sending circuit comprises an encoding circuit for encoding the test code stream of the preset code pattern generated by a test code generator to obtain an encoded code stream; the data sending circuit also comprises a first shift register which is connected with the coding circuit and used for converting the coded code stream into a serial code stream to be sent to the tested active cable.
Optionally, in the cable testing method provided in the embodiment of the present application, before the second retiming chip in the active cable to be tested receives the test code stream, the transparent transmission control circuit in the second retiming chip is controlled to start by receiving a second control instruction sent by the main control device.
Specifically, the transparent transmission control circuit in the second retiming chip is controlled to start, so as to start the transparent transmission mode of the second retiming chip, after the data receiving circuit in the second retiming chip receives the high-speed serial data of the preset code pattern, the transparent transmission control circuit performs data recovery (specifically including protocol and logic analysis and state confirmation) on the data of the preset code pattern, and sends out the recovered data through the data sending circuit, so as to realize transmission of the data of the preset code pattern.
In an optional implementation manner, the cable testing method in this embodiment of the application may perform a transmission performance test on an active cable provided with a second retiming chip, as shown in fig. 6, a data receiving circuit of the second retiming chip receives a test code stream and sends the test code stream to a data sending circuit through a transparent transmission control circuit, and the data sending circuit sends the code stream to a first retiming chip in a slave control device.
In an optional implementation manner, the cable testing method in this embodiment may further perform a transmission performance test on an active cable provided with two second retiming chips, as shown in fig. 7, a data receiving circuit of the second retiming chip disposed at one end of the active cable receives a test code stream and sends the test code stream to a data sending circuit of the active cable through a transparent transmission control circuit, and the data sending circuit sends the code stream to a data receiving circuit of the second retiming chip disposed at the other end of the active cable to receive the test code stream, sends the test code stream to a data sending circuit of the active cable through the transparent transmission control circuit, and sends the code stream to a first retiming chip in the slave control device.
Step S506, receiving a target code stream obtained after the tested active cable transmits the test code stream, and sending the target code stream to the error code detector to detect the error code rate when the tested active cable transmits the test code stream.
Optionally, in the cable testing method provided in this embodiment of the present application, receiving a target code stream obtained after the tested active cable transmits the test code stream, and sending the target code stream to the error code detector, so as to detect an error rate when the tested active cable transmits the test code stream, includes: receiving a target code stream through a data receiving circuit in a first retiming chip, performing clock data recovery on the target code stream through the data receiving circuit, converting a code stream obtained after recovery into a serial code stream, and decoding the serial code stream; and sending the decoded code stream to an error code detector, and determining an error rate based on the decoded code stream through the error code detector.
Specifically, the data receiving circuit comprises an equalizing circuit, and after receiving a target code stream obtained after the tested active cable transmits a test code stream, the equalizing circuit compensates signal attenuation in the target code stream to obtain a compensated code stream; the data receiving circuit also comprises a clock data recovery circuit which is connected with the equalization circuit and used for carrying out clock recovery and data recovery on the compensated code stream to obtain a recovered code stream; the data receiving circuit also comprises a second shift register which is connected with the clock data recovery circuit and is used for converting the recovered code stream into the parallel code stream; in addition, the data receiving circuit also comprises a decoding circuit which is used for decoding the parallel code stream to obtain a decoded code stream and inputting the decoded code stream into the error code detector.
Optionally, in the cable testing method provided in the embodiment of the present application, sending the decoded code stream to an error detector, and determining, by the error detector, an error rate based on the decoded code stream includes: and comparing the decoded code stream with a stored preset code stream of a preset code pattern, and generating an error rate according to a comparison result.
According to the cable testing method provided by the embodiment of the application, after a first retiming chip in the slave control device receives a first control instruction sent by the master control device, a test code generator and an error code detector in the first retiming chip are controlled to start; generating a test code stream of a preset code pattern through a test code generator, and sending the test code stream to a tested active cable, wherein a second retiming chip is arranged in the tested active cable, and the first retiming chip and the second retiming chip are the same in type; the target code stream obtained after the tested active cable transmits the test code stream is received, and the target code stream is sent to the error code detector so as to detect the error rate when the tested active cable transmits the test code stream, and the problem that the data transmission performance of the high-speed active cable is difficult to detect in the related technology is solved. The test code generator and the error code detector in the first retiming chip in the slave control device are started through the master control device, the active cable used for transmitting the code stream of the preset code pattern is detected, and therefore the effects of improving the efficiency and accuracy of detecting the data transmission performance of the high-speed active cable and reducing the detection cost are achieved.
It should be noted that the steps illustrated in the flowcharts of the figures may be performed in a computer system such as a set of computer-executable instructions and that, although a logical order is illustrated in the flowcharts, in some cases, the steps illustrated or described may be performed in an order different than presented herein.
The embodiment of the application also provides a nonvolatile storage medium, wherein the nonvolatile storage medium comprises a stored program, and the program controls the equipment where the nonvolatile storage medium is located to execute a cable test method during running.
The embodiment of the application also provides an electronic device, which comprises a processor and a memory; the memory has computer readable instructions stored therein and the processor is configured to execute the computer readable instructions, wherein the computer readable instructions when executed perform a cable testing method. The electronic device herein may be a server, a PC, a PAD, a mobile phone, etc.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In a typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include forms of volatile memory in a computer readable medium, Random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). The memory is an example of a computer-readable medium.
Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The above are merely examples of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (10)
1. A cable test apparatus, comprising:
the master control equipment is used for sending a first control instruction, wherein the first control instruction is used for instructing the start of a test code generator and an error code detector in a first retiming chip in the slave control equipment;
the slave control equipment is in communication connection with the master control equipment, comprises the first retiming chip and is used for receiving the first control instruction, responding to the first control instruction and starting a test code generator in the first retiming chip so as to send a test code stream of a preset code pattern generated by the test code generator to the tested active cable; and responding to the first control instruction to start an error code detector in the first retiming chip so as to detect an error code rate when the tested active cable transmits the test code stream, wherein a second retiming chip is arranged in the tested active cable, the tested active cable is used for transmitting the code stream of the preset code pattern, and the error code detector is used for detecting the error code rate when the tested equipment transmits the code stream of the preset code pattern.
2. The cable test device of claim 1, wherein the first retiming chip further comprises a data transmitting circuit, an input terminal of the data transmitting circuit is communicatively connected to the test code generator, and an output terminal of the data transmitting circuit is connected to the first terminal of the active cable under test, and is configured to receive and convert the test code stream, and transmit the converted test code stream to the active cable under test;
the first retiming chip further comprises a data receiving circuit, wherein the input end of the data receiving circuit is connected with the second end of the tested active cable, and the output end of the data receiving circuit is in communication connection with the error code detector, and is used for receiving and converting a target code stream output after the tested active cable transmits the test code stream, and sending the target code stream to the error code detector.
3. The cable test device of claim 1, wherein the first retiming chip and the second retiming chip are of a same type, and both the first retiming chip and the second retiming chip are timer chips.
4. The cable test device of claim 1, wherein the master control device communicates with the first retiming chip via an I2C bus.
5. The cable test device of claim 1, wherein the predetermined pattern is a pattern defined by a predetermined protocol, wherein the predetermined protocol is a USB3.2 protocol, and wherein the predetermined pattern is a CP9 pattern defined by the USB3.2 protocol.
6. A cable testing method applied to the cable testing apparatus of any one of claims 1 to 5, comprising:
after receiving a first control instruction sent by a master control device, a first retiming chip in a slave control device controls a test code generator and an error code detector in the first retiming chip to start;
generating a test code stream of a preset code pattern through the test code generator, and sending the test code stream to a tested active cable, wherein a second retiming chip is arranged in the tested active cable, and the first retiming chip and the second retiming chip are the same in type;
and receiving a target code stream obtained after the tested active cable transmits the test code stream, and sending the target code stream to the error code detector so as to detect the error code rate when the tested active cable transmits the test code stream.
7. The cable testing method according to claim 6, wherein before the second retiming chip in the active cable to be tested receives the test code stream, a second control instruction sent by the main control device is received to control a transparent transmission control circuit in the second retiming chip to start.
8. The cable testing method of claim 6, wherein generating a testing code stream of a preset code pattern by the testing code generator and sending the testing code stream to the tested active cable comprises:
generating the test code stream of the preset code pattern through the test code generator, and sending the test code stream to a data sending circuit in the first retiming chip;
and coding the test code stream through the data sending circuit, converting the coded code stream into a serial code stream, and sending the serial code stream to the tested active cable.
9. The cable testing method of claim 6, wherein receiving a target code stream obtained after the tested active cable transmits the test code stream, and sending the target code stream to the error code detector to detect an error rate when the tested active cable transmits the test code stream comprises:
receiving the target code stream through a data receiving circuit in the first retiming chip, performing clock data recovery on the target code stream through the data receiving circuit, converting the code stream obtained after recovery into a serial code stream, and decoding the serial code stream;
and sending the decoded code stream to the error code detector, and determining the error rate based on the decoded code stream through the error code detector.
10. The cable testing method of claim 9, wherein sending the decoded codestream to the error detector, and determining, by the error detector, an error rate based on the decoded codestream comprises:
and comparing the decoded code stream with the stored preset code stream of the preset code pattern, and generating an error rate according to a comparison result.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011632405.9A CN112769457A (en) | 2020-12-31 | 2020-12-31 | Cable testing device and cable testing method |
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| CN202011632405.9A CN112769457A (en) | 2020-12-31 | 2020-12-31 | Cable testing device and cable testing method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114006631A (en) * | 2021-09-17 | 2022-02-01 | 苏州浪潮智能科技有限公司 | Cable testing device and method based on code pattern signal verification |
| CN114006834A (en) * | 2021-10-30 | 2022-02-01 | 杭州迪普信息技术有限公司 | Debugging method and device for high-speed signal equipment |
| CN114389751A (en) * | 2021-12-14 | 2022-04-22 | 北京无线电计量测试研究所 | Automatic equalization method and system for error code test equipment |
| CN117112477A (en) * | 2023-08-02 | 2023-11-24 | 成都电科星拓科技有限公司 | Normalization implementation method for PCIe (peripheral component interconnect express) re-timer verification |
-
2020
- 2020-12-31 CN CN202011632405.9A patent/CN112769457A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114006631A (en) * | 2021-09-17 | 2022-02-01 | 苏州浪潮智能科技有限公司 | Cable testing device and method based on code pattern signal verification |
| CN114006834A (en) * | 2021-10-30 | 2022-02-01 | 杭州迪普信息技术有限公司 | Debugging method and device for high-speed signal equipment |
| CN114389751A (en) * | 2021-12-14 | 2022-04-22 | 北京无线电计量测试研究所 | Automatic equalization method and system for error code test equipment |
| CN114389751B (en) * | 2021-12-14 | 2024-03-12 | 北京无线电计量测试研究所 | Automatic equalization method and system for error code test equipment |
| CN117112477A (en) * | 2023-08-02 | 2023-11-24 | 成都电科星拓科技有限公司 | Normalization implementation method for PCIe (peripheral component interconnect express) re-timer verification |
| CN117112477B (en) * | 2023-08-02 | 2024-05-28 | 成都电科星拓科技有限公司 | Normalization implementation method for PCIE RETIMER verification |
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