JPS6177468A - Memory constitution for picture data of facsimile equipment - Google Patents

Abstract

PURPOSE:To attain the reduction in the hardware by forming an RAM accessed directly by a CPU as a toggle buffer so as to be used for a picture data memory. CONSTITUTION:One line picture data read by a CCD sensor 15 is transferred to an RAM 4 of an RAM 14 by a DMA controller 12 in terms of DMA, then a picture data before one line is subject to DMA transfer to a coder 16 by other channel of a DMA controller 12 from the RAM 5 in parallel. Since the RAMs 4, 5 are switched at each one line picture data so as to write/read the data continuously, a read pulse, a write pulse a switch such as DATABUS and a write route are not required.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a configuration of an image data memory in a facsimile machine.

(Prior Art) Until now, there have been no suitable known references disclosing the technology in this field, especially the technology related to the present invention, but the one shown in Figure 2 below provides a general overview of the technology. It is understood that

FIG. 2 is a diagram showing the structure 11FI of the image data memory in the conventional facsimile machine.

In the figure, l is the CPU, 2 is the program ROM (
3 is a RAM that can be directly accessed by the CPU (hereinafter referred to as ttAM(3)), and 4.5 is an external It8M and address controller (hereinafter referred to as RAM(t)) that forms a toggle buffer (hereinafter referred to as FXToggle Buffer). , RAM(2)), 6
7 is a CCD sensor for reading image data; 7 is an encoder for converting the image data into code; and switch 8.9.10 for switching the route between each section. .

First, one line of image data read by the CCD sensor 6 is written to the RAM (7) 4 via the switches 8 and 9. On the other hand, asynchronously with this operation, RAM (2)
5, the image data of one line/previous is read out via the switch 10 and encoded by code 257.

These two operations, writing and reading, were performed continuously for 111L by alternately switching RAM(/)./, [tAM(,?)j by a switch 9°IO.

You can also add characters such as letters to this Toggle Bu.
When writing to ffe'r, ROM, ? The character patterns stored in the computer were edited on the RAM (?C) and transferred via the switch 8.9.

(Problems to be Solved by the Invention) However, in the circuit with the above configuration, the ToggleBu
READ /P to configure ffer, WR
There is a drawback that the hardware of the ITE = LUS, DATABUS, etc. switch, and the character writing route switch is complicated.

(Means for Solving the Problems) The present invention has been made in order to eliminate the drawback that the Toggle Buffer switch described above becomes complicated. RAM accessed directly by tl-Tog
It is configured to be used as an image data memory as a gleBuffer. This allows the simplified picture to obtain memory for data.

(Function) The RAM according to the present invention is divided into two by software address switching, and
For example, 1 rai/:+! is read by a CCD sensor. ii (When C9 data is DMA-transferred to one I and AM by the DMA controller, in parallel, the image data one line before from the other IζAM is DMA-transferred to the encoder by the other channel of the DMA controller. In this way, for each line of image data, writing and reading are continuously performed by switching between two RAMs.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 11 is a CPU, 12 is a DMA controller,
13 is ROM, 74 is RA that is directly accessed by CPU
M(4) and RAM<5), 15 is a CCD sensor,
16 is an encoder, and 17 is a data bus for data transfer between each section.

The RAM 74 is divided into two by software address switching into RAM (4) and RAMC5).
For example, one line of image data read by the COD sensor 15 is stored in the DAM.
When DMA transfer is performed by the controller I2 to the RAM (4) I4, in parallel, image data from one run before is transferred from the RAM (5) 14 by DMA to the encoder 16 by another channel of the DMA controller 12, and so on. RAM (4) 14, RA for each line of image data
Writing and reading are performed continuously by switching M(5)14.

(Effects of the Invention) As explained above, according to the present invention, since the RAM directly accessed by the CPU is used as the memory for image data, existing general-purpose ICs (DMA controllers, etc.)
can be used.

In addition, by software address switching, Tog
Since it forms gle Buffer, external RAM
The amount of hardware needed to switch between READ JR, ITE-J, etc., which was required when configuring the Toggle Buffer, can be significantly reduced. moreover,
Toggle the character pattern stored in the ROM section
Since it can be edited directly on eBuffer, there is no need for a write route for this character to ToggleBuffer, and there are advantages such as hardware simplification.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of the configuration of an image data memory in a conventional facsimile machine. 11...CPU, t:z...DMA controller,
13...ROM, 74...RAM (4) and RAM
(5), 15... CCD sensor, 16... encoder,
17...Data bus.

Claims (1)

[Claims] A memory configuration for image data of a facsimile machine, characterized in that the facsimile machine uses a DMA controller in combination, a RAM that is directly accessed by a CPU is formed as a toggle buffer, and is used as a memory for image data.