JPH03268967A - Control circuit of dot matrix printer - Google Patents

Abstract

PURPOSE:To improve printing speed by a method wherein when a read control signal from a character pattern memory of a microprocessor is detected, a signal conversion circuit which sends a write control signal to an image memory is estabilished. CONSTITUTION:When a command from a processor is reading out from a memory 2, an enable signal (d) is outputted from a decoder 7 to the memory 2. When it is a writing command to an image memory 3, a selection signal (e) is outputted from a control circuit 4. A comparator 8 includes a NAND circuit 14 having a signal (d) and a signal (e) as input and when either thereof becomes active, it outputs a signal (f) which makes the memory 3 active. Further, when a data (b) is within a brake point XH and a stop point YH which are stored in registers 9, 10 and the signal (d) is active, a selection signal (g) is outputted from a NOR circuit 15 to the control circuit 4. When the control circuit 4 receives the signal (f) for making the memory 3 active, it converts the signals (f) to an enable signal (h) to be sent to the memory 3. When the control circuit 4 receives the signal (g), it converts the signal (g) to a write signal (i) to be sent to the memory 3. Thereby, data transfer time can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control circuit for a dot matrix printer, and particularly to a transfer control circuit for character pattern data.

[Prior Art] Conventionally, when transferring data from a character pattern memory to an image memory in a control circuit of a dot matrix printer, a microprocessor is used as shown in the jl and j2 routes in FIG. 2 and in FIG. The conventional method was to read character pattern data from character pattern memory 2 and then write it to image memory 3.

[Problem to be solved by the invention] The conventional data transfer method described above has two functions: reading and writing.
Since two operations are required, it takes one hash cycle for the microprocessor to read data from the character pattern memory, and one hash cycle for writing it to the image memory, so it has the disadvantage that it takes at least two bus cycles.

SUMMARY OF THE INVENTION An object of the present invention is to provide a control circuit for a dot matrix printer that can perform two operations, reading and writing, in one bus cycle when transferring data from a character pattern memory to an image memory.

[Means for Solving the Problems] When the control circuit of the dot matrix printer of the present invention detects a read control signal for the character pattern memory, it performs signal conversion to send the write control signal of character pattern data on the data bus to the image memory. Has a circuit.

[Function] When the microprocessor issues a read control signal for character pattern data onto the data bus to the character pattern memory and the character pattern is read out onto the data bus, the write control signal converted by the signal conversion circuit , the character pattern data is written into the image memory.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the control circuit of the dot matrix printer of the present invention, FIG. 2 is a diagram showing the flow of data, FIG. 3 is a logic circuit diagram of the address comparison circuit 8, and FIG. 4 is an image A memory map of the character pattern memory 2 showing areas transferred to the memory 3, and FIG. 5 is a read/write time chart.

As shown in FIG. 1, the control circuit of this embodiment is provided as a signal conversion circuit that converts a read control signal for the character pattern memory 2 into a write control signal for the image memory 3, or as a logic circuit within the address comparison circuit 8. The detailed configuration consists of a microprocessor 1 that controls data transfer by outputting data a, address data b, and control signal C to a data bus 13, an address bus 14, and a control signal line 15, respectively, and a large number of A character pattern memory 2 in which character patterns are stored, and an image memory 3 in which read character patterns are written.

An address decoder 7 inputs address data b and a control signal C and sends an output enable signal d for output control to the character pattern memory 2; an address decoder 7 inputs address data b and a control signal C and controls writing to the image memory 3; The address control signal control circuit 4 sends the write enable signal and the write signal i, and the address data b and output enable 15 d are output from the address control signal control circuit 4 to activate the image memory 3. The address comparison circuit 8 receives the signal e and sends the write active signal f of the image memory 3 or the character pattern memory partial selection signal g to the address control signal control circuit 4. Further, the address comparison circuit 8 includes a register 9 as shown in FIG.
．． 10, comparators 11, 12, NOR circuits 13, 15, and NAND circuits 14.Registers 9 and 10 contain area boundaries when character patterns to be sent to image memory 3 are limited to a predetermined area of character pattern memory 2. The values, namely the break point address xH and the stop point address YH (FIG. 4), are pre-stored via the data bus 13.

Next, the operation of this embodiment will be explained.

In the case of an instruction from the microprocessor 1 or reading pressure from the character pattern memory 2, the output enable signal d is output from the address decoder 7 to the character pattern memory 2, and in the case of an old instruction to the image memory 3, the address Image memory selection 45 from control signal control circuit 4
No. e is output. The address comparison circuit 8 includes a NAND circuit 14 that receives an output enable signal d and an image memory selection signal e, and outputs a signal f that activates the image memory 3 when either one becomes active. Address data b is within the range of break points X, 4 and stop point YH stored in register 9.10, and output enable signal d
is active, the character pattern memory partial selection signal g is sent to the NOR circuit 1 to the address control signal control circuit 4.
Output from 5. Address control signal control circuit 4
When receiving the signal f that activates the image memory 3, it is used as the enable signal of the image memory 3, and when receiving the character pattern memory partial selection signal g, it is used as the write signal i of the image memory 3. , respectively converted and sent to the image memory 3. Therefore, while the read signal of the character pattern memory 2 is output from the microprocessor 1 and the data of the read character pattern 2 is on the data bus 13, the enable signal and write signal i are also output to the image memory 3. Therefore, the character pattern data is written into the image memory 3 in one step without going through the microprocessor 1, as shown in FIG. 2 and in FIG.

E. Effects of the Invention As explained above, the present invention provides a signal conversion circuit that sends a write control signal to the image memory when a read control signal from the character pattern memory of the microprocessor is detected. When the character pattern data is read out from the character pattern memory onto the data bus, the character pattern data is written to the image memory in one bus cycle, and compared to the conventional case where the data is once transferred via the microprocessor, the character pattern data is written to the image memory in one bus cycle. The data transfer time from the pattern memory to the image memory is reduced to about half, which has the effect of significantly increasing printing speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the control circuit of the dot matrix printer of the present invention, FIG. 2 is a simplified diagram of the data flow, FIG. 3 is a logic circuit diagram of the address comparison circuit 8, and FIG. 4 is a character A memory map of the pattern memory 2, FIG. 5 is a time chart of this embodiment, and FIG. 6 is a time chart of a conventional control circuit. 1--Microprocessor, 2--Character pattern memory, 3--Image memory, 4--Address control signal control circuit, 7--Address decoder, 8--Address comparison circuit, 9.10--Register, 11. 12--Comparator, 13, 15--NOR circuit, 14--NAND circuit, 16--Data bus, 17--Address bus, 18--Control signal line.

Claims (1)

[Claims] 1. A dot matrix that sequentially reads out character patterns stored in a character pattern memory onto a data bus in response to read/write control signals from a microprocessor and writes the character patterns in an image memory as a print image. A dot matrix printer characterized in that the printer control circuit includes a signal conversion circuit that sends a write control signal for character pattern data on a data bus to the image memory when a read control signal for the character pattern memory is detected. control circuit.