JPS6270056A - High-speed printing apparatus in dot type serial printer - Google Patents

High-speed printing apparatus in dot type serial printer

Info

Publication number
JPS6270056A
JPS6270056A JP60210642A JP21064285A JPS6270056A JP S6270056 A JPS6270056 A JP S6270056A JP 60210642 A JP60210642 A JP 60210642A JP 21064285 A JP21064285 A JP 21064285A JP S6270056 A JPS6270056 A JP S6270056A
Authority
JP
Japan
Prior art keywords
read
cpu
memory
write memory
dot
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60210642A
Other languages
Japanese (ja)
Inventor
Kiyoshi Takahashi
潔 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60210642A priority Critical patent/JPS6270056A/en
Publication of JPS6270056A publication Critical patent/JPS6270056A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enable a high-speed printing, by a method wherein a CPU which receives printing data from a host unit and transforms it into a dot-pattern for writing in a memory is actuated simultaneously with a CPU which shares the memory and reads the written dot-pattern to control the action of mechanism portions. CONSTITUTION:When a CPU 1 selects a read/write memory 5 according to a memory switching signal 2, an address selector 3 connects the address bus of the CPU 1 to the read/write memory 5 and release the address bus of a CPU 11 from the read/write memory 5. On the other hand, according to the memory switching signal 2, a data bus buffer 7 opens and the data bus of the CPU 1 is connected to the read/write memory 5 as well as the CPU 1 is perfectly disconnected from a read/write memory 6 and writes the dot-pattern in the read/write memory 5. Upon completion of writing, the CPU 1 switches over the memory switching signal 2. The CPU 11 opens a buffer 8 according to a data bus buffer switching signal 12 and connects the data bus thereof to the read/write memory 5 to read the dot-pattern, thus controlling mechanism portions 14-16 according to the data of dot-pattern.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はドツト式シリアルプリンタに関し、特に印字デ
ータ処理装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dot type serial printer, and particularly to a print data processing device.

〔従来の技術〕[Conventional technology]

従来、ドツト式シリアルプリンタは1つのCPUで上位
装置から印字データを受信し、そのデータをトンドパタ
ーンに展開し、そのドラトノやターンに基づき各機構部
を動作させて印字を行っていた。
Conventionally, a dot-type serial printer receives print data from a host device using one CPU, develops the data into a tone pattern, and prints by operating each mechanical section based on the dot pattern or turn.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のドツト式シリアルプリンタは1つのCP
Uで上位装置からの印字データを受信し、そのデータを
ドットノ’?ターンに展開し、そのドツトパターンに基
づき機構部を制御し印字を行っていたため、−行の印字
を終了するまで次の行の印字データがドラトノやターン
に展開できず、この印字データを処理している間は印字
動作が一時停止するため、全体的な印字速度が低下する
という欠点がある。
The conventional dot serial printer mentioned above has one CP.
Receives print data from the host device at U and sends the data to dotno'? Because the printing was performed by controlling the mechanism based on the dot pattern, the print data of the next line could not be developed into the dots or turns until printing of the - line was completed, and this print data could not be processed. Since the printing operation is temporarily stopped during the printing process, there is a drawback that the overall printing speed decreases.

本発明は前記問題点を解消し、印字速度を高速化する印
字装置を提供するものである。
The present invention solves the above problems and provides a printing device that increases printing speed.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のドツト式シリアルプリンタの高速印字装置は上
位装置からの印字データを受信し、そのデータをドツト
パターンに展開し、メモリに書き込む第1のCPUと、
そのメモリからドラトノやターンを読み出し、その読み
出し結果により印字ヘッドの横送り、用紙送り、印字ヘ
ッドの励磁機構部などを制御する第2のCPUと、前記
2つのCPUが共有してドツトパターンを書き込み又は
読み出すことが可能な2つのメモリとを有することを特
徴とするものである。
The high-speed printing device for a dot-type serial printer of the present invention includes a first CPU that receives print data from a host device, develops the data into a dot pattern, and writes it into a memory;
The second CPU reads dot patterns and turns from the memory, and controls the horizontal feed of the print head, the paper feed, the excitation mechanism of the print head, etc. based on the read results, and the two CPUs share the dot pattern or write the dot pattern. It is characterized by having two memories that can be read.

〔実施例〕〔Example〕

次に1本発明の一実施例について図面を参照して説明す
る。第1図は本発明の一実施例の回路構成を示すブロッ
ク図である。本発明装置は上位装置13から印字データ
を受信しそのデータをドツトパターンに展開しリードラ
イトメモリ5.又は6、K書き込む第1のCPUIと、
リードライトメモリ5゜又は6からドツト−やターンを
読み出し、そのデータに基づき印字ヘッドの横送り、用
紙送り、印字ヘッドの励磁機構部14〜16を制御する
第2のCPUIIより成る。
Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the circuit configuration of an embodiment of the present invention. The device of the present invention receives print data from the host device 13, develops the data into a dot pattern, and reads/writes the data into the read/write memory 5. or 6, the first CPUI to write K;
It consists of a second CPU II which reads dots and turns from the read/write memory 5° or 6, and controls the horizontal feed of the print head, paper feed, and excitation mechanism sections 14 to 16 of the print head based on the data.

まず、CPUIはメモリ切換信号2によりリードライト
メモリ5,6のどちらかを選択する。例えばリードライ
トメモリ5を選択したとすると、アドレスセレクタ3は
CPUIのアドレスバスをリードライトメモリ5に接続
し、CPUIIのアドレスバスをリードライトメモリ5
から開放する。同時洸アドレスセレクタ4はCPUIの
アドレスバスをリードライトメモリ6から開放し、CP
UIIのアドレスバスをリードライトメモリ6に接続す
る。又このメモリ切換信号2によりデータバス・バッフ
ァ7が開き、CPU1のデータバスがす〜ドライドメモ
リ5に接続され、同時にバッファ9が閉じてCPUIの
データバスがリードライトメモリ6から開放される。こ
の状態において、CPUIはリードライ−トメモリ6か
ら完全に切放されて、リードライトメモリ5にドツトパ
ターンを書込む。書込み終了後、CPUIはメモリ切換
信号2を切換え、上述とは逆にアドレス・ぐス、データ
バスをリードライトメモリ5から切放し、リードライト
メモリ6に接続し、次の印字行のドラトノやターンをリ
ードライトメモリ6に書き込む動作に入る。
First, the CPU selects either read/write memory 5 or 6 using memory switching signal 2. For example, if the read/write memory 5 is selected, the address selector 3 connects the CPUI address bus to the read/write memory 5, and connects the CPUII address bus to the read/write memory 5.
Release from. The simultaneous address selector 4 releases the CPUI address bus from the read/write memory 6, and
Connect the UII address bus to the read/write memory 6. In addition, the data bus buffer 7 is opened by this memory switching signal 2, and the data bus of the CPU 1 is connected to the dry memory 5. At the same time, the buffer 9 is closed and the data bus of the CPU 1 is released from the read/write memory 6. In this state, the CPUI is completely disconnected from the read/write memory 6 and writes a dot pattern into the read/write memory 5. After writing is completed, the CPU switches the memory switching signal 2, and contrary to the above, disconnects the address, bus, and data bus from the read/write memory 5, connects it to the read/write memory 6, and starts the doratono and turn of the next print line. The operation of writing to the read/write memory 6 begins.

CPUIIはこのメモリ切換信号2によりCPUIがリ
ードライトメモリ5にドツト・ぞりTンを書込みリード
ライトメモリ5からアドレスバス、データバスを開放し
たのを確認後、データバスバッファ切換信号12により
ノぐツファ8を開き、CPUIIのデータバスをリード
ライトメモリ5に接続し、バッファ10を閉じてリード
ライトメモリ6を開放し、リードライトメモリ5からド
ツトパターンを読み出し、そのデータに基づき、印字ヘ
ッドの横送り、用紙送り又印字ヘッドの励磁などの機構
部14〜16の制御を行なう。
After confirming that the CPU II has written a dot in the read/write memory 5 and released the address bus and data bus from the read/write memory 5 using the memory switching signal 2, the CPU II switches the memory using the data bus buffer switching signal 12. Open the buffer 8, connect the CPU II data bus to the read/write memory 5, close the buffer 10, release the read/write memory 6, read the dot pattern from the read/write memory 5, and based on the data, print the dot pattern next to the print head. It controls the mechanical units 14 to 16 such as feeding, paper feeding, and excitation of the print head.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は上位装置からの印字データ
を受信しドツトパターンに展開し、メモリに書き込むC
PUと、そのメモリを共有し書かれたドツトパターンを
読み出し、そのデータに基づき機構部の動作を制御する
CPUの2つのCPUを同時に動作させ、印字データを
処理させることにより、高速で印字できる効果がある。
As explained above, the present invention receives print data from a host device, develops it into a dot pattern, and writes it into memory.
The effect of high-speed printing is achieved by operating two CPUs at the same time: the PU and the CPU that shares the memory, reads the written dot pattern, and controls the operation of the mechanism based on that data, and processes the print data. There is.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の回路構成を示すブロック図である。 1・・・上位装置からデータを受信するCPU、2・・
・メモリ切換信号、3,4・・・アドレスセレクタ、5
,6・・・リードライトメモリ、?、8,9,10.・
・・データバスバッファ、11・・・機構部を制御する
CPU、12・・・データバスバッファ切換信号、13
・・・上位装置、14・・・印字ヘッド機構部、15・
・・印字ヘッド横送り機構部、16・・・用紙送り機構
部。
FIG. 1 is a block diagram showing the circuit configuration of the present invention. 1...CPU that receives data from the host device, 2...
・Memory switching signal, 3, 4...address selector, 5
,6...Read/write memory, ? , 8, 9, 10.・
...Data bus buffer, 11...CPU that controls the mechanism section, 12...Data bus buffer switching signal, 13
... Host device, 14... Print head mechanism section, 15.
... Print head horizontal feed mechanism section, 16... Paper feed mechanism section.

Claims (1)

【特許請求の範囲】[Claims] (1)上位装置からの印字データを受信し、印字文字を
ドットパターンに展開する第1のCPUと、印字ヘッド
の横送り、用紙送り、印字ヘッドの励磁など各機構部を
展開されたドットパターンに基づき制御する第2のCP
Uと、前記2つのCPUが共有してデータを読み書き可
能な2つのリードライトメモリとを有することを特徴と
するドット式シリアルプリンタの高速印字装置。
(1) The first CPU receives print data from the host device and develops the printed characters into a dot pattern, and each mechanical section, such as horizontal feed of the print head, paper feed, and excitation of the print head, converts the printed characters into the developed dot pattern. Second CP to control based on
1. A high-speed printing device for a dot-type serial printer, characterized in that it has a U and two read/write memories that can be shared by the two CPUs to read and write data.
JP60210642A 1985-09-24 1985-09-24 High-speed printing apparatus in dot type serial printer Pending JPS6270056A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60210642A JPS6270056A (en) 1985-09-24 1985-09-24 High-speed printing apparatus in dot type serial printer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60210642A JPS6270056A (en) 1985-09-24 1985-09-24 High-speed printing apparatus in dot type serial printer

Publications (1)

Publication Number Publication Date
JPS6270056A true JPS6270056A (en) 1987-03-31

Family

ID=16592687

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60210642A Pending JPS6270056A (en) 1985-09-24 1985-09-24 High-speed printing apparatus in dot type serial printer

Country Status (1)

Country Link
JP (1) JPS6270056A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0193372A (en) * 1987-10-05 1989-04-12 Hitachi Medical Corp Enlarging recording method for data
JPH01225560A (en) * 1988-03-04 1989-09-08 Fujitsu Ltd Magnet driving circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0193372A (en) * 1987-10-05 1989-04-12 Hitachi Medical Corp Enlarging recording method for data
JPH01225560A (en) * 1988-03-04 1989-09-08 Fujitsu Ltd Magnet driving circuit

Similar Documents

Publication Publication Date Title
JPS6270056A (en) High-speed printing apparatus in dot type serial printer
JPS61250722A (en) Printer
JPS59164163A (en) Printer apparatus with off-line printing mechanism
JP2716087B2 (en) Output device
JPS61129969A (en) Printing control device
JPS61131119A (en) Page memory managing system
KR200146385Y1 (en) Inkjet printer system of dual bus structure for bus switch
JP2550997B2 (en) Printer
JP3098435B2 (en) Control system for multiple thermal heads
JPH04220365A (en) Printer
JPH0533913B2 (en)
JP2688731B2 (en) Print output controller
JP3027849B2 (en) Printing device
JP2630114B2 (en) High-speed two-printer controller
JPH04216983A (en) Printing device
JPS6334932Y2 (en)
JPH09216424A (en) Printer
JPH03268967A (en) Control circuit of dot matrix printer
JPS6163461A (en) Printer buffer
IL148001A (en) Raster generation system and method of processing raster data
JPH0560426B2 (en)
JP2002137460A (en) Print system and storage control method
JPH0280265A (en) Control unit of bit map memory
JPH05309875A (en) Printing treatment device
JPS6238931A (en) Printing device