KR930007044B1 - Circuit for mapping address - Google Patents

Abstract

The circuit is for utilizing memory space efficiently by mapping a RAM space of 640 KB - 1 MB overlapped to ROM on most significant level of logical address space and the other space on the logical address space one to one. It includes a register for storing the most significant K bit of logical address space, an address detector for detecting the logical address to be mapped or not, and an address converter for converting the logical address of n bit to physical address of n bit.

Description

Address mapping circuit

1 is a block diagram of a conventional general memory control block.

2 is a block diagram illustrating a memory control block for performing a conventional mapping function.

FIG. 3 shows memory mapped by the mapping function of FIG. 2 when the capacity of RAM is 1MB.

FIG. 4 is a memory map showing that the mapping function of FIG. 2 is mapped when the amount of RAM exceeds 1MB.

5 is a block diagram of a memory control block of the present invention.

6 is a block diagram of the address mapping circuit of FIG.

7 is an address mapping circuit diagram of the present invention.

8 is a memory map showing a case where the RAM is mapped to a logical address space of 2MB to 2.384MB when the capacity of RAM is 2MB according to the present invention.

* Explanation of symbols for main parts of the drawings

1: ROM address combining unit 2: ROM control unit

3,3 ': RAM control unit 4, 4': RAM address multiplexer

5: 1MB to 1.384MB address detection unit 6: address detection unit

7: register 8: address detection unit

9: Address conversion unit XNR1 to XNR4: EXNOR gate

XOR1 to XOR2: EXOR gate NA1 to NA6: NAND gate

1 NV1 to 1 NV6: Inverter AND: AND gate

NOR1, NOR2: NOR Gate

The present invention relates to a memory control circuit, and more particularly, to an address mipping circuit for mapping an area of RAM overlapping a ROM.

In a computer system, a main memory device is divided into a random access memory (RAM) and a read only memory (ROM). In general, ROM stores programs and RAM is used to store data, variable variables, and other data that require easy updating. However, when an address (hereinafter referred to as a logical address) coming from a central processing unit (CPU) is an address in which an ROM address and an RAM address overlap, it is impossible to map the address.

FIG. 1 shows a general memory control block which is not mapped in the related art, and includes a ROM address detection unit 1 for detecting a ROM address from an address bus and a ROM control output in response to an output signal R of the ROM address detection unit. And a ROM controller (3) for generating a RAM control output for one-to-one correspondence of addresses from the address bus to an address area of the RAM in response to the always-output signal (R). It was impossible to map regions of overlapping RAM, so the memory regions could not be utilized efficiently.

In order to solve this problem, in conventional IBM PCs and compatible models, the ROM address space area is 640 KB to 1 MB, and the 640 KB to 1 MB RAM area that overlaps the ROM is mapped to a logical address space of 1 MB to 1.384 MB. It was.

2 is a block diagram of a memory control block for performing a conventional mapping function, wherein a ROM address detection section 1 for detecting an address of a ROM from an address bus and an address of 1MB to 1.384MB are detected from the address bus. A detection unit 5 for controlling the ROM, a ROM control unit 2 for controlling the ROM in response to the control signal R of the ROM address detection unit, and the address in response to the control signal R and an output signal of the detection unit. RAM control unit 3` which controls the RAM by a signal from a bus. When an address of 1MB to 1.384MB is detected by the detection unit 5 from the address bus, the RAM control unit 3` is 640KB to 1MB. Areas of RAM were selected and mapped.

Therefore, in the case of mapping by the memory control block of FIG. 2, as shown in FIG. 3, when the capacity of RAM is 1MB, the memory area is efficiently mapped by mapping the 640KB to 1MB of RAM overlapping the ROM to 1MB to 1.384MB. Could use. However, as shown in FIG. 4, even when the capacity of the RAM exceeds 1 MB, the 640 KB to 1 MB of RAM overlapping with the ROM is mapped to 1 MB to 1.384 MB, which makes it impossible to use the RAM area above 1 MB.

Accordingly, an object of the present invention is to provide an address mapping circuit that effectively utilizes a memory area by mapping a RAM of 640KB to 1MB overlapping with a ROM to the top of a logical address space and mapping one area of another RAM to one of a logical address space. To provide.

In order to achieve the above object, the address mapping circuit of the present invention includes a ROM address detecting unit for detecting an address of a ROM from an address bus, a ROM control unit for generating a ROM control output in response to an output signal of the ROM address detecting unit, and A system having a RAM control unit for generating a RAM control output for one-to-one correspondence of an address from an address bus to an address area of a RAM in response to an output signal, wherein the register stores a most significant K bit of an n-bit logical address space. And an address detecting unit for detecting whether or not to be mapped with the input n-bit logical address, and converting a logical address of n bits into an n-bit physical address at all times in response to an output signal of the address detecting unit. Address translation input to control unit It is characterized by having a part.

Hereinafter, a configuration of an address mapping circuit of the present invention will be described with reference to the accompanying drawings.

5 is a block diagram of the memory control block according to the present invention, and the address mapping circuit 6 is further provided in the conventional general memory control block of FIG.

FIG. 6 shows the address mapping circuit 6. The register 7 stores the most significant K bits of the logical address space, the logical address entered from the address bus, and the output value of the register. And an address detector 8 for generating FLAG, and an address converter 9 for converting the logical address into a physical address of RAM to be mapped in response to the control output signal FLAG.

FIG. 7 is a circuit diagram of one embodiment incorporating blocks of the address mapping circuit of FIG. 6 for application to a system having a 24-bit address bus having a system RAM capacity of 2 MB and a ROM area of 640 KB to 1 MB. .

The address mapping circuit of FIG. 7 maps the logical addresses 200000H to 25FFFFH to physical addresses 0A0000H to in order to map 640KB to 1MB of RAM superimposed on the ROM into 2MB to 2.384MB, which is the uppermost space of the logical address, so as not to overlap the ROM. 0FFFFFH).

The address conversion table is as follows.

The address detecting section 8 for detecting whether or not the address to be mapped in the above address change table is the most significant bit of the logical address space stored in the registers B23, B22, B21, and B20 and the logical address of the logical address. Input the most significant bit (A23, A22, A21, A20) and if A23 = B23, A22 = B22, A21 = B21, A20 = B20

X = Y = Z = P = 1,

Three bits (A19, A18, A17) of the logical address

Back side

The logical expression of Q = 1 must be satisfied.

When X = Y = Z = P = Q = 1, a control output FLAG is generated to change the logical addresses A23 to A17 to physical addresses iA23 to iA17, and address conversion when FLAG = 0. Ie FLAG = Must satisfy the logical expression of. In other words,

FLAG =

Must satisfy the logical expression of. In addition, the address conversion circuit 9

i) FLAG = 1

iA23 = A23, iA22 = A22, iA21 = A21, iA20 = A20

iA19 = A19, iA18 = A18, iA17 = A17

ii) FLAG = 0

iA23 = iA22 = iA21 = iA20 = 0

iA19 = 1

iA18 = A17 + A18

iA17 =

By i) ii)

iA23 = A23FLAG... … … … … … … … … … … … … … … … … … … … … … (One)

iA22 = A22FLAG... … … … … … … … … … … … … … … … … … … … … … (2)

iA21 = A21 FLAG... … … … … … … … … … … … … … … … … … … … … … (3)

iA20 = A20 FLAG... … … … … … … … … … … … … … … … … … … … … … (4)

iA19 = A19FLAG + … … … … … … … … … … … … … … … … … … … … (5)

iA18 = A18FLAG + ( A17 + A18 ) … … … … … … … (6)

iA17 = A19FLAG + · … … … … … … … … … … … … … … … … (7)

It is represented by the logical expression of.

Simplify the equations 5), 6) and 7)

iA19 = A19 + = … … … … … … … … … … … … … … … … … (5)

iA18 = A18 ( + FLAG) + ( ) = A18 … (6)

iA17 = FLAG… … … … … … … … … … … … … … … … … … … … … … (7)

(The above expressions are simplified by the Karnaugh map).

7 is a circuit diagram for implementing the above logic expression. The address detecting unit 8 is composed of four EXNOR gates XNOR1 to XNOR4 and generates a node Q = 1 to generate nodes X = Y = Z = P = 1. In order to do this, one AND gate (AND) and one NOR gate (NOR2) are configured. In order to satisfy the logic expression of control output FLAG = X, Y, Z, P, Q, one NAND gate NA1 was configured. The address converting circuit 9 has four NAND gates NA2 to NA5 and four inputs for inputting the control output FLAG and each bit of the logical addresses A23 to A20 to satisfy the logic expressions (1) to (4). Four inverters INV1 to INV4 for inputting the outputs of the NAND gates NA2 to NA5 were configured. In order to satisfy the expression (5), the inverter consists of an inverter INV5 that inverts the logical address A19 and a NAND gate NA6 that inputs the output of the inverter INV5 and the control output FLAG. To satisfy the input, the inverter INV6 which inverts the control output FLAG and the logical address A17 and the NOR gate NOR1 and the logical address A18 which input the outputs of the control output FLAG and the inverter INV6 are inputted. And an EXOR gate (XOR2) for inputting the output of the inverter (INV6) and the control output (FLAG) to satisfy the expression (7).

FIG. 8 shows a memory map showing the case where the address mapping circuit of FIG. 7 is applied to the memory control block diagram of FIG. 5 and mapped to a logical address space of 2M to 2.384MB when the capacity of the system RAM is 2MB.

Therefore, in the address mapping circuit of the present invention, when the capacity of the system RAM exceeds 1 MB, the existing RAM existing in the range of 1 MB to 1.384 MB overlaps with the mapped RAM, and improves the conventional disadvantage of not using the RAM above 1.384 MB. Therefore, RAM can be efficiently utilized by mapping ROM and overlapped RAM to the logical address top space regardless of the amount of system RAM, and mapping other RAM one-to-one with the logical address space.

The present invention is not limited to the above embodiments, and various modifications and applications are possible within the spirit and scope of the present invention.

Claims (8)

A ROM address detection section for detecting the address of the ROM from an address bus, a ROM control section for controlling the ROM in response to a control signal of the address detection section, and a logical address from the address bus in response to a control signal of the ROM address detection section. In a system having a RAM for one-to-one correspondence to an address of a RAM, a register for storing the most significant K bits of an n-bit logical address space and whether the input n-bit logical address should be mapped or not are detected. And an n-bit physical address converting unit for the n-bit logical address in response to an output signal of the address detecting unit. 2. The apparatus of claim 1, wherein the address detecting unit comprises: a first comparing unit comparing each of the most significant K bits in the n-bit logical address; a second comparing unit comparing the nK bits in the n-bit logical address; And a control unit for generating a control output by combining the outputs of the first comparing unit and the second comparing unit. 3. The address mapping circuit according to claim 2, wherein the first comparison section includes an EXNOR gate for inputting each bit of the K bits and each bit of the K bits of the register. 4. The address mapping circuit according to claim 3, wherein the second comparator comprises an AND gate for inputting the upper two bits of the n-K bits, and a NOR gate for inputting the output of the AND gate and the lower one bit. The address mapping circuit according to claim 4, wherein the control unit includes a NAND gate for inputting outputs of the K EXNOR gates and outputs of the NOR gates. The address mapping circuit according to claim 1, wherein the address conversion section comprises a first conversion section for converting each bit of the K bits and a second conversion section for converting each bit of the n-K bits. 7. The address mapping circuit according to claim 6, wherein the first conversion section comprises a NAND gate for inputting each bit of the K bit and an output of the address detection section, and an inverter for inputting the output of the NAND gate. . The display device of claim 7, wherein the second converter comprises: a first inverter for inputting the upper 1 bit of the n-K bit, a NAND gate for inputting an output of the inverter and an output of the address detection unit; A second inverter for inputting the lower 1 bit of the n-K bit, an NOR gate for inputting the output of the inverter and the output of the address detector, an EXOR gate for inputting the output of the NOR gate and the middle 1 bit of the n-K bit; And an EXOR gate for inputting the output of the second inverter and the output of the address detector.