KR920010427A - Address mapping circuit - Google Patents

Address mapping circuit Download PDF

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KR920010427A
KR920010427A KR1019900018132A KR900018132A KR920010427A KR 920010427 A KR920010427 A KR 920010427A KR 1019900018132 A KR1019900018132 A KR 1019900018132A KR 900018132 A KR900018132 A KR 900018132A KR 920010427 A KR920010427 A KR 920010427A
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address
bit
output
inputting
bits
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KR930007044B1 (en
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정재훈
민병언
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김광호
삼성전자 주식회사
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

내용 없음.No content.

Description

어드레스 맵핑 회로Address mapping circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제5도는 본 발명의 메모리 제어 블록 구성도이고,5 is a configuration diagram of a memory control block of the present invention.

제6도는 제5도의 어드레스 맵핑 회로의 블록 구성도이고,FIG. 6 is a block diagram of the address mapping circuit of FIG.

제7도는 본 발명의 어드레스 맵핑 회로도이다.7 is an address mapping circuit diagram of the present invention.

Claims (8)

어드레스 버스로 부터 ROM의 어드레스를 검출하기 위한 ROM 어드레스 검출부와, 상기 어드레스 검출부의 제어신호에 응답하며 ROM을 제어하기 위한 ROM 제어부와, 상기 ROM 어드레스 검출부의 제어신호에 응답하여 어드레스 버스로 부터의 논리적 어드레스를 RAM의 어드레스로 일대일로 대응시키기 위한 RAM을 구비한 시스템에 있어서, n비트의 논리적 어드레스 공간의 최상위 K비트를 저장하는 레지스터와, 상기 입력되는 n비트의 논리적 어드레스가 맵핑되어야 할 것인지 아닌지를 검출하기 위한 어드레스 검출부와, 상기 어드레스 검출부의 출력 신호에 응답하여 상기 n비트의 논리적 어드레스를 n비트의 물리적 어드레스로 변환하는 어드레스 변환부를구비하는 것을 특징으로 하는 어드레스 맵핑 회로.A ROM address detection section for detecting an address of the ROM from an address bus, a ROM control section for controlling the ROM in response to a control signal of the address detection section, and a logical address from the address bus in response to a control signal of the ROM address detection section. In a system having RAM for one-to-one correspondence of addresses to RAM addresses, a register for storing the most significant K bits of an n-bit logical address space and whether or not the input n-bit logical address should be mapped or not should be mapped. And an address converting section for detecting and an address converting section for converting the n-bit logical address into an n-bit physical address in response to an output signal of the address detecting section. 제1항에 있어서, 상기 어드레스 검출부는 상기 n비트의 논리적 어드레스 중의 최상위 K비트를 각각 비교하는 제1비교기부와, 상기 n비트의 논리적 어드레스중의 n-K비트를 비교하는 제2비교부와, 상기 제1비교부와 상기 제2비교부의 출력을 조합하여 제어출력을 발생하는 제어부를 구비한 것을 특징으로 하는 어드레스 맵핑회로.2. The apparatus of claim 1, wherein the address detecting unit comprises: a first comparator unit for comparing the most significant K bits of the n bits of logical addresses, a second comparator for comparing the nK bits of the n bits of logical addresses; And a control unit for generating a control output by combining an output of the first comparing unit and the second comparing unit. 제2항에 있어서, 상기 제1비교부는 상기 K비트의 각비트와, 상기 레지스터의 K비트의 각 비트를 입력하는 EXNOR 게이트를 구비한 것을 특징으로 하는 어드레스, 맵핑회로.3. The address and mapping circuit according to claim 2, wherein the first comparison section includes an EXNOR gate for inputting each bit of the K bits and each bit of the K bits of the register. 제3항에 있어서, 상기 제2비교부는 상기 n-K 비트의 상위 2비트를 입력하는 AND 게이트와, 상기 AND 게이트의 출력과 하위 1비트를 입력하는 NOR 게이트를 구비한 것을 특징으로 하는 어드레스 맵핑회로.4. The address mapping circuit according to claim 3, wherein the second comparator comprises an AND gate for inputting the upper two bits of the n-K bits, and a NOR gate for inputting the output of the AND gate and the lower one bit. 제4항에 있어서, 상기 제어부는 상기 K개의 EXNOR 게이트의 출력과 NOR 게이트의 출력을 입력하는 NAND 게이트를 구비한 것을 특징으로 하는 어드레스 맵핑회로.The address mapping circuit according to claim 4, wherein the control unit includes a NAND gate for inputting outputs of the K EXNOR gates and outputs of the NOR gates. 제1항에 있어서, 상기 어드레스 변환부는 상기 K비트의 각 비트를 변환하는 제1변환부와, 상기 n-K 비트의 각 비트를 변환하는 제2변환부를 구비한 것을 특징으로 하는 어드레스 맵핑회로.The address mapping circuit according to claim 1, wherein the address conversion section comprises a first conversion section for converting each bit of the K bits and a second conversion section for converting each bit of the n-K bits. 제6항에 있어서, 상기 제1변환부는 상기 K비트의 각 비트와 상기 어드레스 검출부의 출력은 각각 입력하는 NAND 게이트와, 상기 NAND 게이트의 출력을 입력하는 인버터를 구비한 것을 특징으로 하는 어드레스 맵핑회로.7. The address mapping circuit according to claim 6, wherein the first conversion section comprises a NAND gate for inputting each bit of the K bit and an output of the address detection section, and an inverter for inputting an output of the NAND gate, respectively. . 제7항에 있어서, 상기 제2변환부는 상기 n-K 비트의 상위 1비트를 입력하는 제1인버터와 상기 인버터의 출력과 상기 어드레스 검출부의 출력을 입력하는 NAND 게이트; 상기 n-K 비트의 하위 1비트를 입력하는 제2인버터와 상기 인버터의 출력과 상기 어드레스 검출부의 출력을 입력하는 NOR 게이트와 상기 NOR 게이트의 출력과 상기 n-K 비트의 중위 1비트를 입력하는 EXOR 게이트; 상기 제2인버터의 출력과 상기 어드레스 검출부의 출력을 입력하는 EXOR 게이트를 구비한 것을 특징으로 하는 어드레스 맵핑회로.8. The display device of claim 7, wherein the second converter comprises: a first inverter for inputting the upper 1 bit of the n-K bit, a NAND gate for inputting an output of the inverter, and an output of the address detection unit; A second inverter for inputting the lower 1 bit of the n-K bit, an NOR gate for inputting the output of the inverter and the output of the address detector, an EXOR gate for inputting the output of the NOR gate and the middle 1 bit of the n-K bit; And an EXOR gate for inputting the output of the second inverter and the output of the address detector. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900018132A 1990-11-09 1990-11-09 Circuit for mapping address Expired - Fee Related KR930007044B1 (en)

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Application Number Priority Date Filing Date Title
KR1019900018132A KR930007044B1 (en) 1990-11-09 1990-11-09 Circuit for mapping address

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Application Number Priority Date Filing Date Title
KR1019900018132A KR930007044B1 (en) 1990-11-09 1990-11-09 Circuit for mapping address

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KR920010427A true KR920010427A (en) 1992-06-26
KR930007044B1 KR930007044B1 (en) 1993-07-26

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