JPS6032221B2 - Address translation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an address translation method in an information processing apparatus employing a virtual memory method, and more particularly to a control method for invalidating address translation pairs on an address translation buffer.

Many information processing devices have an independent address space (this is called virtual memory), and by writing programs using addresses on this virtual memory, you can be aware of the limitations of main memory capacity. This makes it possible to create programs without having to do anything.

Generally, virtual memory is divided into multiple segments, and each segment is made up of a number of pages. This page on virtual memory is called a logical page. On the other hand, the main memory is also divided into a large number of pages (these are called real pages), and it is possible to allocate a logical page on the virtual memory to any real page position on the main memory. When a certain logical page on the above virtual memory is allocated to a certain real page position on main memory, when a memory request is made, the address on the virtual memory (this is called a logical address) is actually allocated on the main memory. It is necessary to convert it to the address of the actual page location (this is called a real address).

This is address translation. In general, a segment table (S) is used to convert logical addresses to real addresses on main memory.
T), page table (PT) is used. PT contains the logical page address within that segment and the main memory I for each segment.
This is a table that maps the real page addresses on J, and ST
is a table showing the position of the PT table in the virtual memory for each virtual memory. FIG. 1 shows a general address conversion process using a segment table and a page table. In FIG. 1, 1 indicates a logical address, and 2 indicates a real address obtained by address conversion. 3 is a register that holds the start address of ST of the virtual memory to which the currently running program belongs (this is called SBR), and the virtual memory is switched by:
This is done by changing the contents of this SBR3.

This method is generally called a multiple virtual memory method.
4 is a segment table (ST), and 5 is a page table (PT).

A plurality of these STs and PTs are prepared so that a plurality of users can program each other without being aware of the addresses used by other users. Address translation is performed as follows. First, the entry address of ST4 is obtained by adding the start address of ST4 held in SBR3 and the segment field of logical address 1, and then the start address of PT5 is obtained by referring to the corresponding entry of ST4. Next, the start address of PT5 and the page field of logical address 1 are added to obtain the entry address of PT5, and the corresponding entry of PT5 is then referenced to obtain the real page address. Next, this real page address and the displacement field of logical address 1 (address within the real page) are combined to obtain a real address. By the way, ST4, P in Figure 1
T5 is placed on the main memory, and each time a memory request is made,
Obtaining the real address by referring to ST4 and PT5 takes too much time.

Therefore, conversion pairs of logical addresses (logical page addresses) and real addresses (real page addresses) that have been converted before are usually stored in a high-speed buffer memory within the CPU, and subsequent access to the same logical page is In this method, the real page address is obtained directly from the high-speed buffer memory, thereby speeding up the address conversion. This high-speed buffer memory is called an address translation buffer (ATB). FIG. 2 shows the address translation process using the ATB. In FIG. 2, 6 is the ATB, which consists of multiple entries, each entry containing one logical page address, the corresponding real page address, and a validity indicator indicating the validity of the address translation pair. bit (V bit) is stored. 7 is a TLB entry control unit, and 8 is a comparison circuit.

To explain the operation of FIG. 2, based on the segment field and page field of logical address 1, and the contents of SBR3, the TLB entry control unit 7 controls the logical page address, real page address, and V of the corresponding entry of TLB6.
Read the bit.

Comparison circuit 8 compares the logical page address read from TLB 6 with the upper bit of logical address 1, and sets the output line to "1" when the two match. If a match is found in the comparison circuit 8 and the V bit of the corresponding entry in the TLB 6 is "1", the real page address read from the TLB 6 and the displacement field of the logical address are combined to form the real address 2. do. On the other hand, if the comparison circuit 8 does not find a match, the real address is determined by the address conversion process shown in FIG. At this time, the translated pair of logical page address and real page address obtained is stored in the corresponding entry of TLB 6 and used for subsequent access to the same entry. Now, the S that holds the start address of the ST
When the contents of the BR are rewritten by a program or the like, the virtual memory is switched.

Therefore, at this time, it is necessary to invalidate the address translation pair stored in the ATB (it is necessary to reset the validity indicating bit (V bit) of each entry in the ATB). However, the system space occupied by the operating system in the virtual memory is a space commonly used by each user, and even if the virtual memory is switched, the address translation information remains the same. Therefore, in high-performance information processing devices, the following method is used to reduce the overhead when switching virtual memories. [1] The address space used by the operation system and the address space used by the user program are completely separated, and the ATB is also divided into an area used by the operation system and an area used by the user program. , A method of invalidating only the ATB area used by the user program, but not invalidating the ATB area used by the operating system, when switching virtual memory (Special Seki No. 50-30435).

'2} The segment continuation indication bit (SSI
bit) and set the ST SSI bit corresponding to the segment allocated to the operating system to “1”.
When the virtual memory is switched, the SSI bit is “1”
A method that does not invalidate the ATB entry. Among these, method '1} uses hardware to create system space (
Address space) is partitioned into one for the operating system and one for the user program, so if you expand the system space used by the operating system, the overhead when switching virtual memory increases and throughput decreases. be.

For this reason, method '2) above is mainly employed in general-purpose information processing apparatuses running various operating systems. FIG. 3 shows an example of ST, PT, and ATB entries of an information processing apparatus employing the method [2} above, where A is an ST entry, mouth is a PT entry, and C is an ATB entry. Note that SF indicates a segment fault bit, and PF indicates a page fault bit.
However, conventionally, by switching the virtual memory mentioned above, the ATB
When invalidating the above address translation pair, check the SSI bit for each entry in the ATB, and
When the bit was "1", the V bit was not changed, and when the SSI bit was "0", the V bit was reset.

As described above, since the contents of the SSI bit are checked for each entry in the ATB, the conventional method has the disadvantage that it takes a long time to invalidate the address translation pair on the ATB. The present invention solves the above-mentioned conventional drawbacks and reduces the time required to invalidate address translation pairs on the ATB when virtual memory is switched. The SSI bits of all entity IJs belonging to one block are divided into
1 on the ATB when invalidating the above address translation pair.
According to the state of the SSI bit of an entry, it can be determined whether or not to invalidate address translation pairs stored in all entries of the block to which the entry belongs.

FIG. 4 is a diagram for explaining one embodiment of the present invention, in which 10' is a virtual memory, 20 is an ATB, and the ATB 20 is a diagram for explaining an embodiment of the present invention.
corresponds to ATB6 in FIG.

In this example, virtual memory 0 has four segments 11
, 12, 13, 14, and correspondingly A
The TB 20 is divided into four blocks 21, 22, 23, and 24. Although each block of the ATB 20 has a plurality of entries, only entries 201, 201, 203, and 204 of the block 20 are shown in FIG. ATB
It is the same as in the prior art that each entry in each of the 20 blocks has the configuration shown in FIG. 3C. However, the address translation pairs regarding segments 11, 12, 13, and 14 of the virtual memory 10 are the corresponding blocks 21, 22 of the ATB 20, respectively.
, 23, 24. As a result, the third entry of each entry belonging to one block of ATB20
The states of the SSI bits shown in Figure C are all the same. When invalidation of an address translation pair on the ATB is instructed due to virtual memory switching, the contents of the first entry 201 of the block 21 of the ATB 20 are first read and the state of its SSI bit is tested.

If SSI="0", the V bits of all entries 201, 202, 203, and 204 belonging to block 2 are reset, and the address translation pairs stored in each entry of block 21 are invalidated. On the other hand, if SSI="1", all entries 201, 20 belonging to block 21
V bits 2, 203, and 204 are not changed. 22,2
Similarly, for 3, for example, the SS of the first entry
Depending on the state of the I bit, it is determined whether or not to invalidate the address translation pairs stored in all entries of the corresponding block.

FIG. 5 is a diagram for explaining another embodiment of the present invention, in which 20 is an ATB, 31, 32, 33, and 34 are ATBs.
This is a latch that holds the state of the SSI bit provided corresponding to each block 21, 22, 23, and 24.

That is, in FIG. 5, a latch for holding the SSI bit is provided for each block of the ATB instead of providing SSI bits in all entries in each block of the ATB. When storing the address conversion pair of the logical address and real address obtained by referring to ST and PT on the main memory in the corresponding entry of the corresponding block of the ATB 20, the state of the SSI bit is simultaneously stored in the latch 31 corresponding to the block. ,32,3
3, 34. For example, the address translation pair for segment 11 of virtual memory 0 in FIG.
When storing in the entry 201 belonging to block 21 of segment 20, at the same time, the state of the SSI bit of the ST entry regarding the segment 11 is stored in the latch 3 corresponding to block 21.
Store in 1. When invalidation of the address translation pair on the ATB is instructed by virtual memory switching, the latch 31,
Depending on the state of the SSI bits stored in 32, 33, and 34, the corresponding blocks 21, 22, and 2 of the ATB 20
It is determined whether or not to invalidate the address translation pair stored in 3 and 24. For example, the SS stored in latch 31
If the state of the I bit is “0”, the ATB 20 is turned off. All entries 201, 202, 203, belonging to block 21
The V bit of 204 is reset to invalidate the address translation pair stored in each entry. On the other hand, latch 31
If the state of the SSI bit stored in A is “1”, then
The V bits of all entries belonging to the corresponding block 21 of the TB 20 are not changed. As described above, in the present invention, it is possible to determine whether or not to invalidate multiple address translation pairs stored in one block of the ATB by testing the SSI bit once.
It is possible to reduce the time required to invalidate address translation pairs on the TB.

Furthermore, in the present invention, all address translation pairs related to one segment of virtual memory are stored in one block of ATB, so by adding a circuit to reset the V bit of an entry belonging to any one block on ATB, ,
Only address translation pairs for a specified segment of virtual memory can be disabled.

As a result, when an ST entry is rewritten by a program, conventionally all address translation pairs on the ATB are invalidated, but in the present invention, only the address translation pairs related to the segment corresponding to the rewritten ST entry are invalidated. This makes it possible to reduce the overhead when rewriting the ST entry. Note that in Figures 4 and 5, the virtual memory is divided into four segments, but even if the number of segments increases, by increasing the number of blocks in the ATB according to the number of segments, all entries belonging to one block can be divided. The SSI bits have the same contents, and the same machine as this example has 1
By testing the SSI bit twice, it can be determined whether or not to invalidate a plurality of address translation pairs stored in one block of the ATB.

As described above, according to the present invention, the time required to invalidate address translation pairs on the ATB due to virtual memory switching can be shortened, so that the performance of the information processing device can be improved.

Furthermore, by adding a circuit for resetting the V bit of an entry belonging to only one arbitrary block on the ATB, it is possible to reduce the overhead caused by invalidating the ATB when rewriting the ST entry by a program.

[Brief explanation of the drawing]

Figure 1 is a diagram for explaining the address translation process using a segment table and page table, Figure 2 is a diagram for explaining the address translation process using an address translation buffer, and Figure 3 is a diagram for explaining the address translation process using an address translation buffer.
This figure shows an example of the structure of entries in a segment table, a page table, and an address translation buffer, and FIGS. 4 and 5 are diagrams for explaining one embodiment of the present invention. 1...Logical address, 2...Real address, 3...Control register, 4...Segment table, 5
...Page table, 6...Address translation buffer (
ATB), 7...ATB control section, 8...
・Comparison circuit, 1 0...Virtual memory, 11-14・
...Virtual memory segment, 20...
ATB, 2 1~2 4...ATB block, 2
0 1-204...ATB entry. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Scope of Claims] 1. Address translation method in which address translation information of logical addresses and real addresses is stored in an address translation buffer, and when a logical address is given, a corresponding real address is obtained faster than the address translation buffer. In the step, the address translation buffer is divided into a plurality of blocks corresponding to the plurality of divided segments of the virtual memory, and address translation information of address equality for each segment of the virtual memory is stored in the corresponding block of the address translation buffer. However, when the invalidation of the address translation information of the address translation buffer is instructed, the invalidation control information held by one of the address translation information of the address translation buffer causes the block in which the address translation information exists to be invalidated. An address translation method characterized by determining whether or not to invalidate all address translation information. 2. In the address translation method according to claim 1, a latch is provided for holding invalidation control information corresponding to each block of the address translation buffer, and when invalidation of the address conversion information is instructed, An address translation method characterized by determining whether or not to invalidate all address translation information stored in a corresponding block of an address translation buffer based on invalidation control information held in a latch.