JPH0612330A - Storage control system - Google Patents
Storage control systemInfo
- Publication number
- JPH0612330A JPH0612330A JP4188889A JP18888992A JPH0612330A JP H0612330 A JPH0612330 A JP H0612330A JP 4188889 A JP4188889 A JP 4188889A JP 18888992 A JP18888992 A JP 18888992A JP H0612330 A JPH0612330 A JP H0612330A
- Authority
- JP
- Japan
- Prior art keywords
- space
- area
- address
- tlb
- common
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
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- Memory System Of A Hierarchy Structure (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は多重仮想空間における共
有領域と空間ごとに個別の管理とアドレス変換に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to individual management and address conversion for each shared area and space in multiple virtual spaces.
【0002】[0002]
【従来の技術】従来の多重仮想空間の管理方式は、空間
に固有の領域と空間で共有されている領域に対して、同
一のアドレス変換機構でおこなっていた。2. Description of the Related Art In the conventional management method of multiple virtual spaces, the same address conversion mechanism is used for a region unique to the space and a region shared by the space.
【0003】[0003]
【発明が解決しようとする課題】従来の技術では、空間
に固有のアドレス変換情報と空間に共通のアドレス変換
情報を同じTLB領域で管理している。このため、空間
の切替えを行なうとき、TLB領域内の情報を無効にし
ている。この結果、空間の切替えの頻度が多い情報処理
装置では、アドレス変換情報を求める処理が頻繁にな
り、性能を落す原因になっている。In the conventional technique, the address translation information unique to the space and the address translation information common to the space are managed in the same TLB area. Therefore, the information in the TLB area is invalidated when the space is switched. As a result, in an information processing device in which the space is frequently switched, the processing for obtaining the address conversion information becomes frequent, which causes a drop in performance.
【0004】一部の情報処理装置では、空間ごとに識別
子を持たせ切替え前の空間と切替え後の空間のアドレス
変換情報の区別をつけ、同時に複数の空間のアドレス変
換情報を保持できるようなアドレス変換機構を採用して
いる。しかし、複数の空間で共通のアドレス変換情報で
あっても識別子が異なるため、異なるアドレス変換情報
としてTLB領域に設定しなければならず、TLB領域
の効率的な利用をさまたげている。また、識別子で区別
できる空間数よりも多い仮想空間に切り替わるときは、
TLB領域の情報を無効にせざるおえないという問題が
あった。In some information processing devices, an address is provided for each space so that the address translation information of the space before switching and the address translation information of the space after switching can be distinguished and the address translation information of a plurality of spaces can be held at the same time. Uses a conversion mechanism. However, even if the address translation information is common in a plurality of spaces, the identifiers are different, so that different address translation information must be set in the TLB area, which hinders efficient use of the TLB area. Also, when switching to a virtual space that is larger than the number of spaces that can be distinguished by the identifier,
There was a problem that the information in the TLB area had to be invalidated.
【0005】本発明は上述の問題点に鑑みて空間固有の
TLB領域と空間固有のTLB領域を異なる方式で管理
し、空間切替えやアドレス変換の効率を改善できる記憶
管理方式を提供することを目的としている。In view of the above problems, it is an object of the present invention to provide a storage management system capable of managing a space-specific TLB area and a space-specific TLB area by different methods and improving the efficiency of space switching and address conversion. I am trying.
【0006】[0006]
【課題を解決するための手段】プログラムを実行するア
ドレス空間である論理空間が、メモリの実装されている
アドレス空間である物理空間と異なりうる情報処理装置
の論理空間内アドレスを物理空間内アドレスに変換する
機構を持ち、論理空間内アドレスと物理空間内アドレス
の対応情報であるアドレス変換情報の一部を高速に参照
できる領域であるTLB領域に格納している情報処理装
置において、複数の論理空間に関して同一のアドレス変
換情報を持つTLB領域と、論理空間ごとに固有のアド
レス変換情報を持つTLB領域を区別して管理すること
を特徴としている。A logical space which is an address space for executing a program may be different from a physical space which is an address space in which a memory is mounted. A plurality of logical spaces are provided in an information processing device that has a mechanism for converting and stores a part of the address conversion information, which is the correspondence information between the addresses in the logical space and the addresses in the physical space, in the TLB area, which is an area that can be referred to at high speed. With respect to, the TLB area having the same address translation information and the TLB area having unique address translation information for each logical space are distinguished and managed.
【0007】[0007]
【作用】上記構成によれば、情報処理装置の論理空間内
アドレスをメモリの実装されている物理空間内アドレス
に変換する機構を持ち、アドレス変換情報の一部を高速
に参照できるTLB領域に格納している情報処理装置
で、複数の論理空間に関して同一のアドレス変換情報を
持つTLB領域と、論理空間ごとに固有のアドレス変換
情報を持つTLB領域を、アドレス情報によって区別し
異なる方式で管理できるので、空間切替えアドレス変換
の効率を改善することができる。According to the above structure, the information processing apparatus has a mechanism for converting an address in the logical space into an address in the physical space in which the memory is mounted, and a part of the address conversion information is stored in the TLB area which can be referred to at high speed. In the information processing apparatus, the TLB area having the same address translation information for a plurality of logical spaces and the TLB area having the unique address translation information for each logical space can be managed by different methods by distinguishing them by the address information. The efficiency of space switching address conversion can be improved.
【0008】[0008]
【実施例】以下本発明の一実施例について図を参照して
説明する。An embodiment of the present invention will be described below with reference to the drawings.
【0009】図1は本発明の一実施例による記憶管理方
式の構成図である。FIG. 1 is a block diagram of a storage management system according to an embodiment of the present invention.
【0010】図1において、多重仮想空間全体10に
は、空間共通領域12と複数の空間固有領域が存在し、
そのうち1つのみが現在参照可能な空間固有領域11で
ある。本実施例の情報処理装置1は空間共通TLB領域
2と空間固有TLB領域3とを持つ、いずれのTLB領
域の各エントリ4にも仮想アドレス5とそれに対応する
物理アドレス6の対が格納されている。アドレス変換情
報は、空間共通のアドレス変換情報7と空間固有のアド
レス変換情報8の2種類ある。空間固有のアドレス変換
情報8は、存在する多重仮想空間の数だけ存在する。現
在参照可能な空間固有領域のアドレス変換情報を参照し
ている変数CAS9を設ける。In FIG. 1, the entire multi-virtual space 10 has a space common area 12 and a plurality of space unique areas.
Only one of them is the spatially unique area 11 that can be currently referenced. The information processing apparatus 1 of the present embodiment has a space common TLB area 2 and a space unique TLB area 3, and each entry 4 of any TLB area stores a pair of a virtual address 5 and a corresponding physical address 6 therein. There is. There are two types of address translation information: address translation information 7 common to the space and address translation information 8 unique to the space. The space-specific address translation information 8 exists as many as the number of existing multiple virtual spaces. A variable CAS9 that refers to the address conversion information of the currently peculiar space specific area is provided.
【0011】つぎに動作について説明する。Next, the operation will be described.
【0012】仮想アドレスが空間固有の領域内のアドレ
スか空間共通領域内のアドレスかを判定する方法とし
て、本実施例では論理空間のアドレスを用いる。すなわ
ち、論理空間内のアドレスが16進数で0x40000
000以上のとき、そのアドレスは空間共通であり、空
間共通のアドレス変換情報7で仮想アドレスと物理アド
レスの対応付けをおこなっている。0x4000000
0未満のときは、CAS9が参照する空間固有のアドレ
ス変換情報8で仮想アドレスと物理アドレスの対応付け
をおこなっている。これらのアドレス変換情報は仮想ア
ドレスをキーとして、参照する表形式になっている。As a method for determining whether the virtual address is an address within a space-specific area or an address within a space common area, an address in a logical space is used in this embodiment. That is, the address in the logical space is 0x40000 in hexadecimal.
When it is 000 or more, the address is common to the space, and the virtual address is associated with the physical address by the address conversion information 7 common to the space. 0x4000000
When it is less than 0, the virtual address and the physical address are associated with each other by the space-specific address conversion information 8 referred to by the CAS 9. These pieces of address conversion information are in a tabular form that is referred to by using the virtual address as a key.
【0013】情報処理装置は仮想アドレス(32bi
t)を物理アドレス(32bit)に変換する際にTL
B領域を参照し、対応する仮想アドレスを持つエントリ
を探す、対応するエントリが存在すれば、そのエントリ
に記された物理アドレスでメモリを参照する。The information processing apparatus uses a virtual address (32bi
TL when converting t) to a physical address (32 bits)
The area B is referred to search for an entry having the corresponding virtual address. If the corresponding entry exists, the memory is referred to by the physical address described in the entry.
【0014】対応するエントリがTLB領域に存在しな
い場合、空間共通の領域内のアドレスであれば空間共通
のアドレス変換情報7を参照し、仮想アドレスに対応す
る物理アドレスを求め、その対を空間共通TLB領域2
に設定する。When the corresponding entry does not exist in the TLB area, if the address is within the area common to the space, the address translation information 7 common to the space is referred to, the physical address corresponding to the virtual address is obtained, and the pair is commonly used in the space. TLB area 2
Set to.
【0015】仮想アドレスが空間固有の領域内のアドレ
スであれば空間固有のアドレス変換情報8を参照し、仮
想アドレスに対応する物理アドレスを求め、その対を空
間固有TLB領域3に設定する。If the virtual address is an address within the space-specific area, the space-specific address conversion information 8 is referred to, the physical address corresponding to the virtual address is obtained, and the pair is set in the space-specific TLB area 3.
【0016】空間を切替えるとき、空間固有TLB領域
3のみを情報を無効にする。When switching the space, the information is invalidated only in the space-specific TLB area 3.
【0017】このように空間固有TLB領域3が使用す
るTLB領域を限定することで、空間共通TLB領域2
を有効にしたまま、空間の切替えが可能になり、この結
果、空間の切替えの効率と切替後の空間参照の効率を向
上させることができる。By thus limiting the TLB area used by the space-specific TLB area 3, the space-common TLB area 2
It is possible to switch the space while keeping the effective, and as a result, it is possible to improve the efficiency of the space switching and the efficiency of the spatial reference after the switching.
【0018】実施例では、TLBの構成、アドレスの区
間を限定したが、これらは、本発明の本質ではない、ま
た、実施例では、空間固有TLB領域3と空間共通TL
B領域2を完全に分離したが、これらのTLB領域の一
部が重なっているような構成、あるいは、空間固有TL
B領域が空間共通TLB領域に包含されているような構
成も可能である。Although the TLB structure and the address section are limited in the embodiment, these are not the essence of the present invention. In the embodiment, the space-specific TLB area 3 and the space-common TL are also included.
Although the B region 2 is completely separated, the TLB regions are partially overlapped with each other, or the space-specific TL is
A configuration in which the B area is included in the space common TLB area is also possible.
【0019】[0019]
【発明の効果】本発明は空間共通のTLB領域と空間固
有のTLB領域を異なる方式で管理することを許してい
るため、空間の切替え時に空間共通のアドレス変換情報
を保存することが可能なTLB領域の管理を行なえる。
その結果、空間切替えの効率やアドレス変換の効率を改
善するという効果がある。According to the present invention, the TLB area common to the space and the TLB area unique to the space are allowed to be managed by different methods. You can manage the area.
As a result, there is an effect that the efficiency of space switching and the efficiency of address conversion are improved.
【図1】本発明の一実施例による記憶管理方式の構成図
である。FIG. 1 is a configuration diagram of a storage management system according to an embodiment of the present invention.
1 情報処理装置 2 空間共通TLB領域 3 空間固有TLB領域 4 TLBのエントリ 5 仮想アドレス 6 物理アドレス 7 空間共通アドレス変換情報 8 空間固有アドレス変換情報 9 CAS 10 多重仮想空間全体 11 現在参照可能な空間固有領域 12 空間共有領域 1 Information Processing Device 2 Space Common TLB Area 3 Space Unique TLB Area 4 TLB Entry 5 Virtual Address 6 Physical Address 7 Spatial Common Address Translation Information 8 Space Unique Address Translation Information 9 CAS 10 Entire Virtual Virtual Space 11 Current Unique Space Unique Area 12 Space sharing area
Claims (1)
る論理空間が、メモリの実装されているアドレス空間で
ある物理空間と異なりうる情報処理装置の論理空間内ア
ドレスを物理空間内アドレスに変換する機構を持ち、論
理空間内アドレスと物理空間内アドレスの対応情報であ
るアドレス変換情報の一部を高速に参照できる領域であ
るTLB領域に格納している情報処理装置において、複
数の論理空間に関して同一のアドレス変換情報を持つT
LB領域と、論理空間ごとに固有のアドレス変換情報を
持つTLB領域を区別して管理することを特徴とする記
憶管理方式。1. A mechanism for converting an address in a logical space of an information processing device into an address in a physical space, where a logical space as an address space for executing a program may be different from a physical space as an address space in which a memory is installed. In the information processing device, which has the same address for a plurality of logical spaces, stores a part of the address conversion information, which is the correspondence information between the addresses in the logical space and the addresses in the physical space, in the TLB area, which is an area that can be referred to at high speed. T with conversion information
A storage management method characterized by separately managing an LB area and a TLB area having unique address translation information for each logical space.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4188889A JPH0612330A (en) | 1992-06-24 | 1992-06-24 | Storage control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4188889A JPH0612330A (en) | 1992-06-24 | 1992-06-24 | Storage control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0612330A true JPH0612330A (en) | 1994-01-21 |
Family
ID=16231661
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4188889A Pending JPH0612330A (en) | 1992-06-24 | 1992-06-24 | Storage control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0612330A (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5558874A (en) * | 1978-10-23 | 1980-05-01 | Mitsubishi Electric Corp | Information processing system |
JPS5755581A (en) * | 1980-09-19 | 1982-04-02 | Nippon Telegr & Teleph Corp <Ntt> | Address converting system |
JPS62192832A (en) * | 1986-02-20 | 1987-08-24 | Fujitsu Ltd | Address converting system |
JPS63269242A (en) * | 1987-04-27 | 1988-11-07 | Fujitsu Ltd | Address conversion system |
-
1992
- 1992-06-24 JP JP4188889A patent/JPH0612330A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5558874A (en) * | 1978-10-23 | 1980-05-01 | Mitsubishi Electric Corp | Information processing system |
JPS5755581A (en) * | 1980-09-19 | 1982-04-02 | Nippon Telegr & Teleph Corp <Ntt> | Address converting system |
JPS62192832A (en) * | 1986-02-20 | 1987-08-24 | Fujitsu Ltd | Address converting system |
JPS63269242A (en) * | 1987-04-27 | 1988-11-07 | Fujitsu Ltd | Address conversion system |
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