JPH0690686B2 - Address translation index invalidator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a central processing unit in an information processing device, and more particularly to an address translation indexing mechanism of the central processing unit adopting a multiple virtual storage system.

2. Description of the Related Art Conventionally, a central processing unit that employs a multiple virtual memory system causes exceptions and interrupts during instruction execution, task switching,
When the virtual address space was switched at the same time, it was necessary to erase the address translation index mechanism (TLB).

The following two methods can be considered as the erasing method.

First: Erase all entries in TLB.

The method of erasing the 2: 1 entry, checking whether it belongs to the virtual space switched by the microprogram, and erasing if it does.

FIG. 6 is a block diagram of the above-mentioned first method. In FIG. 6, a 16-entry full-associative TLB is assumed. In FIG. 6, when the virtual space is switched, the reset signal 608 becomes active by the micro instruction, the reset terminal of the all validity bit 609 of the associative memory becomes active, and the all validity bit 609 is cleared.

FIG. 7 is a block diagram of the second method. In this figure
16-entry full-associative TLB is assumed. In FIG. 7, the validity bit 711 of the associative memory can be reset independently by each microinstruction. When the virtual space is switched, the virtual address of each entry of the TLB is read by the microprogram, and if the virtual address is different from the new virtual space, the clear microinstruction corresponding to the entry is issued and the microinstruction decoder 709 is used. Decoding is performed and one of the reset signals 710 of the corresponding validity bit 711 is made active to clear the corresponding validity bit 711.

The above is repeated for all TLB entries.

Problems to be Solved by the Invention In the above method 1, the TLB is changed every time the virtual space is switched.
Since all the entries are deleted, the TLB performance (bit rate) decreases. On the other hand, switching between virtual spaces does not take time.

On the other hand, in the above-mentioned method 2, it takes time to erase because it is controlled by the microprogram. That is, it takes time to switch the virtual space. However, the bit rate of TLB does not drop as much as the method of 1.

Thus, in the past, the TLB had only a function to clear all entries or a function to clear one entry.
The bit rate of the TLB is reduced by clearing all, and it takes time to clear if the microprogram of the central processing unit selectively clears each entry.

Therefore, the present invention intends to provide an address translation indexing mechanism invalidating device capable of clearing unnecessary entries of the TLB at high speed.

According to the present invention, according to the present invention, in an information processing apparatus that employs a multiple virtual storage system and is provided with an address translation indexing mechanism, an actual entry corresponding to a matching entry is matched by a virtual address match comparison function during address translation. In addition to the means to read the address,
For each entry of the address translation indexing mechanism, a match comparing means for a part of the virtual address is provided, and the match comparing means for a part of the virtual address simultaneously and in parallel with each entry, matches the part of the virtual address. There is provided an address translation look-up mechanism invalidating device characterized by invalidating only virtual addresses and real addresses stored in the address translation look-up mechanism corresponding to.

Effect In the present invention, since the dedicated hardware for selectively clearing unnecessary entries in the TLB is provided, unnecessary entries in the TLB can be cleared at high speed.

Embodiment An embodiment of the address translation indexing mechanism invalidating device according to the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a diagram showing a process of address conversion in the embodiment of the present invention.

In FIG. 1, reference numeral 101 is a register (VAR) for storing a virtual address, and VAR101 has four registers (ATR0-3) for storing a base address and a length of an area table. 102 is attached. VAR10
1 is field 103 that specifies ATR0-3 of VAR101 and VA
Field 104 that specifies the area number of R101 and VAR101
Has a field 105 for designating the page number of the VAR 101 and a field 106 for indicating the in-page offset of the VAR 101. The area table register 102 and ATR0-3 are
It has a field 107 indicating the area table base address.

Area table 109, which has a maximum of 1024 entries, has reference number 108
The area table entry has a structure as shown in FIG.

The page table 111 with a maximum of 256 entries has a reference number 110
The page table entry has a structure as shown in.

Reference number 112 is a field indicating the page table base of the area table entry, and reference number 113 is a field indicating the actual page number of the page table entry. Further, a main storage device 114 is provided.

FIG. 2 is a block diagram of the address translation look-up mechanism (TLB) in the embodiment of the present invention.

In FIG. 2, the bus 201 for transferring the virtual address to the TLB is coupled to the register VAR202 for temporarily storing the virtual address. The VAR202 has a field 203 for specifying the section number of the virtual address and a field 204 for specifying the in-page offset of the virtual address.
Have others.

On the other hand, the bus 205 for designating the register address for reading / writing each entry in the TLB is coupled to the decoder 206 for decoding the register address, and the information 207 decoded by the address decoder 206 is:
It is connected to the associative memory (hereinafter abbreviated as RM) 208 that clears each section.

The RM 208 outputs the reset signal 209 of the validity bit of the associative memory AM 211 described later. This AM211 has a bit 210 indicating the validity of the content of each entry of the AM211.

When "1", the entry is valid, when "0", the entry is invalid.

A part of the VAR202 other than the in-page offset is bus 212
It is connected to M211. This AM211 stores a portion other than the in-page offset of the virtual address, compares the portion other than the in-page offset of the virtual address stored in the VAR202 at the time of address translation, and if a match signal 213
Is an associative memory (abbreviated as AM) for sending to DM214.

The DM 214 is a memory for storing a real address corresponding to the virtual address stored in the AM 211. DM21
4 is bus 2 for transferring the value of register RAR to DM214
15 are combined. The bus 215 is used for address translation /
It is coupled to a register (hereinafter abbreviated as RTR) 216 for temporarily storing a real address when reading / writing the DM 214. The RAR 216 is coupled to the in-page offset field 204 of the VAR 202 and is further coupled to the bus 218 for transferring the real address to the RAR.

FIG. 3 shows an associative memory RM and AM in the embodiment of the present invention.
It is a block diagram of.

In FIG. 3, the bus 301 that specifies the register address when reading / writing each entry of the TLB is
It is coupled to the input of decoder 302 which decodes the register address. The information 303 decoded by the decoder 302 is connected to the associative memories RM _{0 to} RM ₁₅ 304 for clearing in units of sections.

The reset signal 305 output by each RM 304 is a validity bit V ₀ indicating the validity of the content of each entry of the associative memory AM.
~ Input to V ₁₅ 306. When the validity bit 306 is "1", the entry is valid, and when it is "0", the entry is invalid.

The bus 307 for transferring a portion other than the in-page offset of the virtual address from the VAR202 is read / write /
It is coupled to an associative memory AM308 for coincidence comparison. This AM308 is AM. A portion other than the in-page offset of the virtual address is stored, and at the time of address conversion, it is compared with the portion other than the in-page offset of the virtual address stored in VAR, and if they match, a match signal 309 is sent to DM 214.
The coincidence signals 309 are connected to a gate 310 which logically sums the decode information of the address decoder and the coincidence signal of AM,
The OR output signal is output to DM via the bus 311.

FIG. 4 is a diagram showing the configuration of validity bits and other bits of the associative memory in the embodiment of the present invention.

In FIG. 4 (a), the validity bit includes a word line 401 that specifies an AM entry when reading / writing the AM, and a match signal line 402 that is output during address conversion.
And a data line 403 for read / write / match comparison to AM and a reset signal 404 of a validity bit are connected.

FIG. 4B shows a bit other than the validity bit of the associative memory, in which a word line 405 that specifies an AM entry when reading / writing the AM,
A match signal line 406 output during address conversion and a data line 407 for read / write / match comparison with AM are connected.

FIG. 5 is a detailed view of the bits shown in FIG. 4 (b),
As shown in the figure, it is configured by connecting MOSFETs. The bits shown in the figure are a data line 501 for reading / writing / matching comparison with the AM, a word line 502 for specifying an AM entry when reading / writing the AM, and a match signal line 503 output during address conversion. And are connected, and
The coincidence signal line 503 is connected to the bit via a comparator (exclusive OR) 504 that performs coincidence comparison during address conversion.

FIG. 10 is a diagram showing an example of a multiple virtual address space in the embodiment of the present invention.

In FIG. 10 (a), reference numeral 1001 indicates a virtual space. One virtual space is 4 gigabytes.

Reference numeral 1002 indicates a section, and one section is 1 gigabyte.

Reference numeral 1003 indicates an area, and one area is 1 megabyte.

Reference numeral 1004 indicates a page, and one page is 4 kilobytes.

In FIG. 10 (b), reference numeral 1005 is a field for designating the section number of the virtual address. reference number
Reference numeral 1007 is a field for designating the area number of the virtual address, and reference numeral 1007 is a field for designating the page number of the virtual address. Reference numeral 1008 is a field for designating an in-page offset of the virtual address.

First, the structure of the virtual space and the process of address conversion will be described with reference to FIGS. 1 and 10.

In this embodiment, as shown in FIG. 10 (a), one virtual space consists of four sections. One virtual space has a size of 4 GB, and one section has a size of 1 GB. One section consists of 1024 areas. The area has a size of 1 megabyte. 1
One area consists of 256 pages. The page has a size of 4 kilobytes.

FIG. 10B shows the structure of each field of the virtual address. The field 1005 for designating the section number has 2 bits, and the field 1006 for designating the area number has 8 bits. Also, specify the page number field 10
07 is 10 bits, and field 1008 that specifies the page offset is 12 bits.

In this embodiment, a paging type virtual memory system is adopted,
A virtual address register VAR101 and area table registers ATR0-3102 are built in the central processing unit, and an area table 109 and a page table 111 are set in the main memory.
Area table 109 is composed of area table entry 108 and page table 111 is page table entry 1
Composed of 10.

In a normal address translation, a virtual address is latched in VRA 202 via bus 201.

Bits 31-30 (hereinafter abbreviated as section numbers) of the virtual address are fields 103 for designating one of ATR0-3 and select ATR0-3.

The designated ATR0-3 indicates the hase address and length of the area table, and it is checked whether bits 29-20 of VAR (hereinafter abbreviated as area number) are within the designated length range. . Area table if within range
Area table entry 1 specified by the area number of 109
Read 08.

The read area table entry shows the base address and length of the page table. Bit 19 of VAR202
Check whether -12 (abbreviated as page number below) is within the specified range. If it is within the range, the page table entry 110 designated by the page number of the page table 111 is read.

The page table entry read is the real page number 11
3 shows the actual page number and VAR bits 11-0.
(Hereinafter, abbreviated as in-page offset) 106 is configured to form a real address to access the data of the main storage device 114.

Here, interrupts, exceptions, etc. occur and tasks are switched,
When the virtual address space is switched at the same time, the value of ATR0-3 is changed, and the area table to be referred when the address is changed,
The page table is switched.

The above is the process of address translation, but if the above table is referred to each time the main memory device is accessed, the performance of the central processing unit decreases. For this reason, an address translation lookaside mechanism (TLB) is usually used. TLB is AM21 as shown in Fig.2.
1, DM214 can store up to 16 pairs of virtual addresses and real addresses recently referenced, and frequently referenced virtual addresses can be translated at high speed by TLB.

Next, the operation of the TLB will be described with reference to FIG.

In the normal address translation, the virtual address 201 is transferred to the VAR 202 by the bus. Of the virtual addresses stored in the VAR202, the part other than the in-page offset is transferred to the AM211 by the bus 212, and a match comparison is performed with the virtual address and real address pair stored in the AM211.
Is sent to DM214. The DM 214 reads the real address of the entry corresponding to the match signal 213, outputs it to the bus 215, and stores it in the RAR 216. Then, the real address is configured together with the offset 204 in the base of VAR202, and the bus 218
Is output to.

Details of the timing are shown in FIG. As can be seen from the timing chart of FIG. 8, address conversion using this TLB is performed in 2 clocks. If you don't hit the TLB,
The area program and page table are read, TLBs are replaced, and addresses are converted by the microprogram of the central processing unit. At this time, the address conversion time is required to be 10 times or more longer than when the TLB bit is set.

By storing the virtual address pair and the real address pair in the TLB in this way, the address conversion is significantly speeded up. Although this TLB has a small capacity (16 entries in this embodiment), the recently referenced virtual address and real address pair are stored (LRU algorithm), and the bit is 97-99% TLB depending on the local reference property of the program. .

However, tasks are switched due to interrupts, exceptions, etc.
When the virtual address space is also switched, the values of ATR0-3 are also changed, and the area table and page table referred to during address conversion are also switched. At this time, the information stored in the TLB is that of the previous virtual address space, and it is necessary to clear the contents of the TLB. Conventionally, all the entries in the TLB have been cleared, but in the present invention, only the entries in the TLB belonging to the ATR whose value has changed among ATR0-3 are cleared. It is known that the TLB bit rate decreases by about 1% when all entries are cleared every 10,000 reference times. In order to prevent the reduction of the bit rate, in the present invention, the value is changed instead of clearing all the entries.
Only the TLB entries that belong to the ADR are cleared (hereinafter abbreviated as section clear).

The operation of this TLB section clear with reference to FIGS. 2 and 8 will be described.

In FIG. 2, the RM 208 is an associative memory that stores a field specifying one of ATR0-3 of VAR202, bits 31-30 (section number), and has a function of performing coincidence comparison with the section number of VAR202. This RM208 has a match signal 209 AM21
1 Validity bit 210 connected to reset terminal.
Here, RM208 is bit 31 of the virtual address stored in AM211.
Same as -30 (sequential number), it is designed to store a copy.

When the virtual address space is switched, the value of ATR0-3 of the old virtual address space and the value of ATR0-3 of the new virtual address space are compared by the microprogram of the central processing unit to detect the ATR whose value has changed. Belongs to an ATR with this value changed
It clears the TLB entry.

First, the ATR number (section number) whose value has changed is transferred to the VAR 202 via the VA bus 201. The section number stored in the VAR 202 is transferred to the RM 208 via the bus 203. RM208 is the section number sent from bus 203
The section numbers stored in each entry of RM208 are compared, and if they match, the match signal 209 is activated and A
It is sent to the reset terminal of the validity bit of M211 and the validity bit of the corresponding entry of AM211 is reset.

Details of the timing are shown in FIG. As shown in this figure, 2 to clear the entries of TLB belonging to one section.
A clock is needed. This is significantly faster than clearing one entry at a time by the microprogram of the central processing unit, and at this time, ATR0-3 rather than clearing all TLBs.
It goes without saying that the performance (bit rate) of the TLB is better by clearing only the TLB entry belonging to the ATR whose value has changed.

Second Embodiment Next, a second embodiment of the present invention will be described. FIG. 11 is a block diagram showing the structure of a TLB using the second embodiment of the present invention.

An example of invalidating the TLB entry that matches the VAR section number in the first embodiment has been shown, but this may be the area number. In the second embodiment, the TLB is cleared by this area number.

A field for designating BIT29-20 (area number) of VAR1102 coupled to bus 1101 for transferring a virtual address to TLB is connected to RM1108, and RM1108 stores the area number.

When clearing the TLB, the area number of VAR1102 and RM1108
If the Airy numbers in the above are compared and they match, the match signal 1109
AM1111 validity bit 1110
Reset the virtual address stored in the corresponding TLB,
Clear the real address pair. This second embodiment can also speed up TLB clearing in area units.

EFFECTS OF THE INVENTION As described above, according to the present invention, at the time of switching the virtual address space, the value of ATR0-3 is changed rather than clearing all TLB.
Clearing only the TLB entries that belong to TR increases the probability that valid TLB entries will remain, thus improving TLB performance (bit rate).

Further, by providing the section clear dedicated hardware in the TLB, it is faster than clearing by the microprogram of the central processing unit, and the time required for virtual address space switching is shortened.

Thus, it is possible to speed up the invalidation of the address translation index mechanism without lowering the performance (bit rate) of the TLB.

[Brief description of drawings]

FIG. 1 is a diagram showing a process of address conversion in the embodiment of the present invention. FIG. 2 is a block diagram showing the structure of the TLB in the embodiment of the present invention. FIG. 3 is a block diagram showing the structure of the associative memory of the TLB in the embodiment of the present invention. FIG. 4 is a diagram showing configurations of validity bits and other bits of the associative memory of the TLB in the embodiment of the present invention. FIG. 5 is a transistor-level diagram showing the 1-bit configuration of the TLB associative memory in the embodiment of the present invention. FIG. 6 is a block diagram showing the structure of a TLB in one conventional example. FIG. 7 is a block diagram showing the structure of a TLB in another conventional example. FIG. 8 is a timing chart showing the timing of TLB address conversion in the embodiment of the present invention. FIG. 9 is a timing chart showing the TLB section clear timing in the embodiment of the present invention. FIG. 10 is a diagram showing the structure of a multiple virtual address space in the embodiment of the present invention. FIG. 11 is a block diagram showing the structure of the TLB in the second embodiment of the present invention. [Main reference number] 202 …… Register for storing virtual address VAR 203 …… Field 203 for specifying section number of virtual address 203 204 …… Field 205 for specifying page offset of virtual address …… Register Address decoder 208 ... Associative memory (R
M) 210 ... Bit indicating the validity of the contents of each entry 211 ... Associative memory AM 214 ... Memory (DM) 216 ... real for storing the real address corresponding to the virtual address stored in AM Address register RAR

Claims (1)

[Claims] 1. In an information processing apparatus adopting a multiple virtual storage system and having an address translation indexing mechanism, in addition to a means for reading a real address corresponding to a matching entry by a virtual address match comparison function at the time of address translation, the address For each entry of the translation look-up mechanism, a match comparison means for a part of the virtual address is provided, and the match comparison means for a part of the virtual address corresponds to an entry that matches a part of the virtual address simultaneously and in parallel with each entry. An address translation indexing mechanism invalidating device, which invalidates only virtual addresses and real addresses stored in the address translation indexing mechanism.