JPS62242239A - Data transfer system - Google Patents

Abstract

PURPOSE:To shorten time for transfer at the time of swap-out at the time of transferring data from physical stack to logical stack by transferring only data of entry for which data are rewritten out of physical stack entry to logical stack. CONSTITUTION:A change flag memory 2 that indicates whether data are rewritten or not is provided corresponding to each entry of physical stack 1. A transfer circuit 5 transfers data of one block or less of logical stack at the time of transfer from the logical stack on a main memory 6 to the physical stack 1, that is, swap-in. At the time of transfer from the physical stack 1 to logical stack, that is, swap-out, only stack entry rewritten by information of entry of the change flag memory 2 out of data of one block or less of the physical stack are written in corresponding logical stack entry on the main memory 6. Thus, time for data transfer from the physical stack to logical stack can be shortened.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figure 9) Problems to be solved by the invention Means for solving the problems (Figure 1) Working examples (Figure 1) (Figures 2 to 8) Effects of the Invention [) Already Required] The present invention provides a data processing system that performs virtual stack control, when data is transferred from a physical stack to a logical stack, when data is rewritten during physical stack entry. By transferring data only for entries to the logical stack, the transfer time during swap-out is shortened.

[Industrial application field]

The present invention relates to a data transfer system, and particularly to a central processing unit CP.
U, memory control unit M In a data processing system composed of SC, main storage unit MSU, etc., when performing virtual stack control using the hardware stack (physical stack) of the central processing unit and the logical stack on the main storage unit. This relates to a data transfer method between a physical stack and a logical stack.

[Conventional technology]

In the virtual stack method, as shown in Figure 9, a logical stack is provided on the main storage device, a hardware stack, that is, a physical stack is provided in the central processing unit, and data on this physical stack is used during data processing. , When the required stack does not exist on the physical stack, the data on this physical stack is returned to the logical stack, and the necessary data is moved from the logical stack onto the physical stack. Note that although the example in FIG. 9 is a case in which the number of blocks in the physical stack is one to simplify the explanation, the physical stack is usually configured with a plurality of blocks.

And the logical stack is divided into blocks of the same size.
(generally n=2"") and one of the logical stacks
The size of the block is equal to one block of the physical stack.

The logical stack area is used from address 0, which is the head of the logical stack, to the maximum address max of block n, and the valid data of the logical stack is from address O to the entry pointed to by the stack top pointer,
The areas are block 0-n-2 and block n, -1
area A (from the first entry of the block containing the stack top to the entry pointed to by the stack top pointer). Furthermore, in the logical stack area, area B (stack top pointer +1
(from the entry indicated by n to the entry with the highest address in the block including the top of the stack) and block n are invalid data areas.

Therefore, the area where it is necessary to transfer between the logical stack and the physical anti-tack in block units is the block O-n
-2 and area A of block n-1.

[Problem that the invention seeks to solve]

Conventionally, blocks 0 to n-2 are transferred between the logical stack and the physical stack in block units;
Regarding No. 1, the transfer between the stacks was performed only to the area.

Incidentally, although there is no need to transfer data to this area that has not been rewritten in the physical stack because it exists on the logical stack, both the rewritten and unrewritten data are in the area A.
Since all of the data was transferred from the physical stack to the logical stack, there was a problem in that it took a long time to transfer this data.

An object of the present invention is to provide a data transfer method that reduces the transfer time when transferring data from a physical stack to a logical stack in this way, in order to solve the above-mentioned problems.

[Means for solving problems]

In order to achieve the above object, in the present invention, as shown in FIG. between the register 3 where the logical stack pointer (PTR) is set, the register 4 where the logical stack top pointer (STP) is set, the physical stack (STK) 1 and the logical stack on the main memory 6. A transfer circuit 5 for transferring data, and an address register 7 for addressing the main memory 6 are provided.

The transfer circuit 5 performs transfer from the logical stack on the main memory 6 to the physical stack 1, that is, swap-in (SWap i
n), the data amount of one block or less of the logical stack is transferred, and the data is transferred from the physical stack l to the logical stack, that is, swap out (SWap o
ut), among the data in one block or less of the physical stack, only the stack entry that has been rewritten by the information in the entry in the change flag memory 2 is written to the corresponding logical stack entry in the main memory 6. It's crowded.

[Effect]

Since a rewritten entry in the physical stack 1 can be identified by the change flag, only this rewritten entry can be transferred from the physical stack 1 to the logical stack, thereby reducing the data transfer time from the physical stack to the logical stack.

〔Example〕

An embodiment of the present invention will be described based on FIGS. 2 to 8.

Fig. 2 is a configuration diagram of an embodiment of the present invention, Fig. 3 is an explanatory diagram of a circuit for performing virtual stack control in one block, Fig. 4 is an explanatory diagram of the operation of the control section, and Fig. 5 is an illustration of the stack extended. FIG. 6 is an explanatory diagram when the stack shrinks. FIG. 7 is an explanatory diagram of the operation when NoTFOUNDP occurs. FIG. 8 is an explanatory diagram when the stack shrinks.
FIG. 3 is an explanatory diagram of the operation when oTFOUNDS occurs.

In FIG. 2, the same reference numerals as in FIG. 1 indicate the same parts, and the number of physical stacks in the figure is l.

In the figure, 1 is a physical stack with a virtual stack control function, and if there is a stack entry addressed by the logical stack pointer held in register 3 and the logical stack top pointer held in register 4, data will be stored. Output to register 8, if not, N0TFO
The change flag memory 2 outputs the UND signal and holds a flag that is either "0" if the corresponding stack entry has not been rewritten, or "1" if it has been rewritten.

The transfer unit 5 includes a register (BLK) 9 that holds a logical stack block number (1 to n in FIG. 9) and a count register (COUNT) 10 that indicates an address within the logical stack block. a comparator that outputs a CARRY signal when STP at 11<
(BLK/C0UNT), a control circuit 12 that comprehensively controls data transfer during swap-in or swap-out, and a control circuit 12 that outputs a STOP signal when
) and the start address (STKBASE) of the logical stack held in the register 13.
and (BLK/C0UNT) to obtain the logical stack address (STKADD) on the main memory 6.

The control circuit 12 is a circuit that transfers data during swap-in or swap-out, and is a circuit that transfers data during swap-in or swap-out.
START) signal.

At this time, if the mode (MODE) signal is "o", a swap-in operation is performed, and if it is "1", a swap-out operation is performed. This control circuit 12 includes a count and a
When either the carry (CARRY) signal from the register 10 or the stop (STOP) signal from the comparator 11 is input, an END signal is output, and the operation of the circuit is stopped.

In addition, the control circuit 12 outputs a count set (COUNTSET) signal for clearing the count register 1° to zero, a count up (COUNTUP) signal for incrementing the count register 10, that is, controlling it by +1.

The register 13 holds the start address (STKBASE) of the logical stack on the main memory 6.

The adder 14 uses the logical stack start address (STKBASE) held in the register 13, the logical stack block number BLK and the logical stack block number held in the count register IO connected to the register 9, respectively.
The logical stack address (STKADR) on the main memory 6 is obtained by performing an addition operation with the intra-block address.

Next, the present invention shown in FIG. 2 will be explained in detail.

Here we will look at the physical stack, including the logical stack top.
The block is called Stack Top Pro Tsuk.

1. Initial setting When starting up the system, the CPU microprogram writes the logical stack start address (
STKBASE), and a value indicating that the logical stack is unused, for example, all zeros, is set in register 4.

2. Swap-in operation ■CPU microprogram swaps to register 9.
The logic stack block number to be read is set, and the MODE signal - "OJ" and 5TART signals are input to the control circuit 12. At this time, if the control circuit 12 is in a stopped state, the control circuit 12 is activated by these signals. , performs the following operations.

■The control circuit 12 inputs C0UN to the count register 10.
Output the TSET signal and set the count value to zero.

■-1 Next, the control circuit 12 inputs the start address 5 of the logical stack held in the register 13 to the address register 7.
TKBASE, register 9 and count register 10
The sum of the concatenated values (STKBAS+(BLK/C0
UNT)) is set as the address value of the main memory 6.

(2) As will be described later, when the 5TOP signal or the CARRY signal is input manually, the -2 control circuit 12 outputs an END signal, enters a stopped state, and completes the swap-in operation.

Here, the 5TOP signal indicates that the swapped in block is the stack top block, and the transfer was performed from the first entry of the stack top block to the stack entry pointed to by the stack top pointer set in register 4. Show that. Further, the CARRY signal indicates that one stack block has been swapped in.

■The control circuit 12 writes the data of the logical stack/entry addressed by the address register 3 as one entry of the physical stack 1 addressed by the concatenated value of the register 9 and the count register 10, and also - Set change flag CFLAG in flag memory 2 to zero. Control circuit 12 then outputs a C0UNTUP signal which increments count register 10 by l-(+1).

■By repeating the operations of ■-1, ■-2, and ■ until the stop condition of ■-2 occurs, the block having the logical stack block number held by the register 9 is transferred from the main memory 6 to the physical stack 1. Swap in.

3. Access to the physical stack When the CPU microprogram accesses the physical stack 1 for data processing, the stack entry addressed by the logical block placed in register 3 and the stack top pointer set in register 4. is on physical stack 1, when reading, only one entry of physical stack 1 is read, and when writing, the write data is written to one entry of physical stack 1, and the corresponding change flag memory 2 is changed. - Set the flag CFLAGI entry to "1".

However, if the stack entry addressed by register 3 and register 4 is not on physical stack 1, then
Regardless of whether the CPU microprogram is reading or writing, it outputs a N0TFOUND signal indicating that the stack entry requested to be accessed by the CPU microprogram is not on the physical stack.

4. Swap out operation ■CPU microprogram swaps to register 9.
Set the logical stack prosock number to output to,
Also, the MODE signal rlJ and the 5TART signal are input to the control circuit 12. At this time, if the control circuit 12 is in a stopped state, the control circuit 12 is activated by these signals and performs the following operations.

■The control circuit 12 inputs C0UNT to the count register 10.
Output the SET signal and make the count value zero.

■-1 Next, the control circuit 12 inputs the start address 5 of the logical stack held in the register 13 to the address register 7.
TKBASE, register 9 and count register 10
The sum of the concatenated values of (STKBASE+ (BLK
/C0UNT)) is set as the address value of the main memory 6. and said register 9 and count register 10
The physical stack 1 entry addressed by the concatenated value 1 (BLK/C0UNT) is set in the data register 8, and the corresponding change flag CFLAGI entry in the change flag memory 2 is read.

Control circuit 12 also outputs a C0UNTUP signal that increments count register 10 (+1).

■-2 At this time, the control circuit 12 receives the 5TOP signal or C
When the ARRY signal is input, the control circuit 12 outputs the END signal, enters a stopped state, and ends the swap out operation. Here, the STOP signal indicates that the swapped out block is the stack top block, and the transfer is performed from the first entry of the stack top block to the stack entry pointed to by the stack top pointer set in register 4. Show that. Also CA
The RRY signal indicates that one stack block has been swapped out. Further, if the read change flag CFLAGO value is "0", then the process (2)-1 is executed. And change flag C
If the FLAGO value is "1", execute the next step (2).

(2) That is, if the value of the change flag CFLAG is "1", the control circuit 12 writes the data set in the data register 8 to the entry of the logical stack addressed by the address register 7.

■In this way, ■-1, ■-2. By repeating the operation (2) until the condition (2) -2 occurs, the block with the logical stack block number held in register 9 is transferred to its rewritten change flag CFLAG rlJ.
Only those that can be swapped out can be swapped out.

Next, a circuit for controlling a virtual stack using one physical stack block will be explained based on FIG.

In FIG. 3, PTRU and PTRL are the upper register and lower register of register 3 in FIG.
5TPU and 5TPL are the upper register and lower register of register 4 in FIG. 2, BLK and C0U.
NT is register 9 and count register 10 in FIG. The bit width of each of these registers is P
TRU=STPU-BLK, PTRL-3TPL=CO
It has something to do with UNT. and PTRU,,5TPU.

BLK is a register that holds the block number of the logical stack, and PTRL, 5TPL, and C0UNT are registers that hold addresses within the logical stack block.

MPX is a multiplexer, and the physical stack l and change flag memory 2 are connected to the PTPL, 5T
Addressed by PL or C0UNT.

CTL is a control unit that generates the following two types of write signals: a CPUWR signal indicating when to write data to the physical stack 1 addressed by the CPU microprogram to the register PTR and register STP;
Or, during the swap-in operation of the control circuit 12 shown in FIG. Accordingly, it operates according to FIG. These two signals are never input at the same time.

5TKBLK is a register that holds a logical stack block number, and normally the same contents as the register BLK are stored.

CMPP is a comparator, and registers PTRtJ and PTRL indicating the pointer of the stack that exists in the work area are
5T due to rewriting the PU microprogram.
When KBLK#PTRU, a N0TFOUNDP signal indicating logical block number mismatch is output.

CMPS is a comparator, and the logic block mismatches due to the expansion and contraction of the stack-to-knob pointer, that is, 5
When TKBLK#5TPU, a N0TFUNDS signal indicating a mismatch of logical block numbers is output.

OR is a logical sum circuit, which calculates the logical sum of the N0TFOUNDP signal and the N0TFOUNDS signal and outputs N0TFOU.
Output as ND signal.

In this way, register 5TKBLK and register PT
If RU and 5TPU are different, that is, accessing a logical stack block that is not in the physical stack l, N
A 0TFOUND signal is output. Also register 5TK
When BLK and registers PTRU and 5TPU match, that is, when accessing a logical stack block in physical stack 1, reading and writing of physical stack 1 is possible.

Furthermore, the N0TPOIJND signal is a cause of an interrupt at the CPU microprogram level, and the N0TFOUN
When the D signal is output, an interrupt occurs, and after eliminating the cause of the interrupt in the interrupt processing routine, the process returns to the original process and continues the process. In this case, since the logical blocks do not match, swap out or swap in processing will be performed.

At this time, if NoTFOUUNDP occurs, the processing according to the flow shown in FIG. 5 is performed, and if NOTF○UNDS occurs, the processing according to the flow shown in FIG. 6 is performed.

If 5TKBLKf=PTRU now, comparator C0M
The N0TFOUNDP signal is output from PP, the N0TFOUND signal is output from the OR circuit OR, and interrupt processing is performed.The processing at this time is performed by a routine as shown in FIG.

a. At this time, the logical stack block number held in register 5TKBLK is transferred to the register (B
LK)9 to instruct the control circuit 12 to start the swap out operation. As a result, the blocks on the physical stack 1 that have been used until now are swapped out to the logical stack.

That is, the start address 5TKBASE of the logical stack written in the register 13 and the logical stack block number written in the register 9 are added by the adder 14, and the swap address I/dest address is set in the address register 7. Ru. As a result, a swap out is performed, and at this time, the control circuit 12 operates so as to transfer only the entry whose change flag CFLAGO value is "1" in the change flag memory 2. In this way, the CPU waits until the swap-out process for the data on the physical stack 1 that has been used until now is completed.

b. When the swap out process is completed, the logical stack block written in the register PTRU in FIG. 3 is written in the register (BLK) 9 in FIG. 2, and the control circuit 12 is instructed to start the swap in operation. do. As a result, the logical blocks required for data processing, indicated by the register PTRU, are swapped into the physical stack 1. CPTJ waits for the processing to proceed until this swap-in is completed, and when the swap-in is completed, it returns to the next microprogram to be executed.

Also, when 5TKBLK≠5TPU, that is, when the stack top pointer position does not match the data in register 5TKBLK due to expansion or contraction of the stack, the comparator COMPS outputs the N0TFOUNDS signal and interrupt processing is performed. , the processing at this time is the sixth
This is performed by the routine shown in the figure. Before explaining the flow in Figure 6, Figure 7 shows the state when the stack is extended.
The state when the stack is shrunk is illustrated in FIG.

When extending from the stack top position shown in FIG. 7(a) to the position shown in FIG. The flag memory entry becomes "1".

Also, from the stack top position shown in Figure 8 (al),
When the stack has shrunk to the position shown in Figure 8(b),
The change flag memory entry corresponding to area 0, which is no longer needed, remains the same as before shrinking, but even if the change flag is "1" for area O, it is not necessary to transfer it when swapping out. do not have.

Next, with reference to FIG. 6, a description will be given of the processing when the N0TFOUND signal is output from the OR circuit OR and interrupt processing is performed in the case of 5TKBLKf-3TPU.

, l At this time, it is first determined whether 5TPU>5TKBLK. If YES, that is, if the stack has grown, it is necessary to swap out the blocks on the physical stack 1 that have been used so far to the logical stack. Therefore, the logical stack block number held in register 5TKBLK is changed to the register (B
LK)9 to instruct the control circuit 12 to start the swap out operation. As a result, the blocks on the physical stack 1 that have been used until now are swapped out to the logical stack. At this time, only entries whose change flag CFLAG is "1" are transferred.

In this way, the data on physical stack 1 can be swapped and
The CPU waits until the out processing is completed, and when the swap out processing is completed, it moves on to the next b' swap in operation. If 5TPU>5TKBLK is No, this means that the stack has shrunk, so there is no need to swap out, and the process moves to the next step b'.

b,'Next, the logical blocks required for data processing indicated by register 5TPU are swapped into physical stack 1. Therefore, the logical stack block written in the register 5TPU is written in the register (BLK) 9 in FIG. 2, and the control circuit 12 is instructed to start the swap-in operation. As a result, a swap-in operation is performed, and the CPU waits for the processing to proceed until the swap-in operation is completed. When the swap-in is completed, the CPU returns to the next microprogram to be executed.

In the above description, only the case where the number of blocks in the physical stack on the CPU is one is explained, but of course the present invention is not limited to this only, and even when the number of blocks is plural,
It can be implemented in a similar manner.

〔Effect of the invention〕

According to the present invention, when swapping out, only what has been rewritten on the physical stack can be selected and returned to the logical stack, so the amount of data transferred can be significantly reduced, and the data processing Efficiency can be improved.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 is a configuration diagram of an embodiment of the present invention, Fig. 3 is an explanatory diagram when virtual stack control is performed using one block of physical stack, and Fig. 4 is a control unit. An explanatory diagram of the operation of CTL. Figure 5 is an explanatory diagram of the operation when NoTFOUNDP occurs. Figure 6 is an explanatory diagram of the operation when NoTFOUNDS occurs. Figure 7 is an explanatory diagram of the physical stack when the stack is extended. An explanatory diagram of the physical stack when the stack shrinks, FIG. 9 shows a conventional example. 1-Physical stack 2...-Change flag memory 3.4-Register 5--Transfer section 6-4 memory 7-Address register 8--Data register 9-Register 10--Count register

Claims (1)

[Scope of Claims] A data processing system consisting of a central processing unit, a main memory control unit, a main memory unit, etc., comprising a physical stack provided in the central processing unit and a logical stack provided in the main memory device. In a device configured to perform virtual stack control, change flag memory 2 has the same number of entries as physical stack (1) and indicates that the corresponding physical stack entry has been rewritten, and physical stack 1 block. It is equipped with a transfer means (5) that transfers data between one block of the logical stack, and when transferring one block from the logical stack to the physical stack, only the top block of the logical stack transfers data of one block or less, and also transfers data from the physical block to the top block of the logical stack. When transferring one block to the logical stack, only the top block of the logical stack transfers one block or less of data, and at the time of transfer, only the data that has been rewritten by referring to the change flag memory is transferred. data transfer method.