JPH04158464A - Memory controller - Google Patents

Abstract

PURPOSE:To simplify circuit configuration by sharing main memory controlled by a CPU and the display memory of a video RAM, etc., and making a main memory controller and a display controller into one chip. CONSTITUTION:A shared RAM 1 is the one shared as the display memory (video RAM) other than the main memory controlled by the CPU 4, and the shared RAM 1 and a ROM 2 comprise a main memory device, and the access control of them are performed by a display/main controller 3. In such a case, the display/main controller 3 is the one made into one chip, and is provided with an access control circuit 3-1, an address switching circuit 3-2, a read/write signal switching circuit 3-3, and a wait signal generation circuit 3-4, etc. There by, the circuit configuration is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory control device that controls main memory and display memory in a word processor or the like.

[Summary of the Invention] The present invention uses a main memory controlled by a CPU and a display memory such as a video RAM in common, and also provides a main memory controller and a display controller.

By converting the and into one-chip and two-pu, the circuit configuration can be reduced to 11! l
'JI:

[Prior Art 1] Conventionally, personal computers, word processors, etc. are configured as shown in FIG. RAM (V
RAM) 24 is provided with a dedicated display controller 25.

Here, main memory controller 23 H CPU 26
The main RAM 21 and ROM 22 are accessed under ff1HH, and data writing/reading operations are controlled between the CPU 26 and the display controller 25.
6 is written to the video RAM 24, and the data read from the video RAM 24 is written to the display driver 2.
7 and output the display from the display device 28. Note that 29 in the figure is an I10 controller that controls the keyboard 30.

[Invention tries to solve! ml] In this way, the main RAM 21 and the video RAM 24 are provided separately, and moreover, the main RAM 21.
Since the configuration includes a dedicated main memory controller 23 and a display controller 25 corresponding to the video RAM 24, there is a disadvantage that the number of components increases and the number of signal lines increases, resulting in high costs.

H@ of this invention shares main memory and display memory,
Moreover, even if the main memory controller and display controller are integrated into one chip, the CPH processing speed can be controlled so as not to be significantly reduced.

[Means to solve the problem] The means of this invention are as follows.

(1) The shared memory is random access memory, etc.
It is shared as a display memory in addition to the main memory controlled by the PU.

(2) The access cycle control circuit specifies CPU access and display access to this shared memory.

(3) The address switching circuit switches and outputs the CPU address and the display address according to the specified state of the access cycle control circuit, and provides the output to the shared memory.

(0, read/write signal off) The M circuit switches and outputs a CPU read/write signal and a display read/write signal according to the designated state of the access cycle control circuit, and supplies the signal to the shared memory.

(5) When the access cycle control circuit specifies display access, the wait signal generation circuit
When a read/write signal is input, a wait signal is generated and given to the CPU to temporarily suspend CPU access until one display access is completed.

Note that the access cycle control circuit, address switching circuit, read/write signal switching circuit, and wait signal generation circuit are integrated into one chip.

[Made by J The operation of the means of this invention is as follows.

Now, when displaying image data on a liquid crystal display device or a CRT display device, an access cycle control circuit specifies display access to the shared memory.

Then, the address switching circuit switches and outputs the display address and provides it to the shared memory, and the read/write signal switching circuit switches and outputs the display read/write signal and provides it to the shared memory. As a result, the image data in the shared memory is displayed and output from the display device.

Furthermore, when accessing the CPU, the access cycle control circuit specifies CPU access to the shared memory.

Then, the address switching circuit switches and outputs the CPU address and provides it to the shared memory, and the read/write signal switching circuit switches and outputs the CPU read/write signal and provides it to the shared memory. This allows the CPU to read/write data to/from the shared memory.

By the way, if the shared memory is being accessed in a visible way,
When the wait generation circuit receives a CPU read/write signal, it generates a wait signal to temporarily wait the CPU access until the display access is completed, and supplies it to the CPU.

In this case, for example, a liquid crystal display (CLCD) with a 640 x 80 dot configuration and driven by a 70 Hz signal is
When the display is driven by the LCD driver on the bit data bus, 8-bit data can be read from the display memory and transferred to the LCD driver once every 2.231 Ls.During this display access period, the CPU read/write signal When a CPU access occurs, the CPU access is temporarily put on standby, but in a CPU that executes one instruction at a rate of once every four clocks at 8MHz, the wait is only entered approximately once every five cycles, which reduces the processing speed by approximately The reduction can be kept to 20%.

Therefore, the main memory and display memory are shared, and the main memory controller and display controller are
Even if the CPU is made into a single file system, the processing speed of the CPU can be controlled so as not to be significantly reduced.

[First Example] Hereinafter, a tsl example will be described with reference to FIGS. 1 to 3.

FIG. 1 is a block diagram showing a word processor (memory control unit W).

Shared RAMI is a random access memory that includes main memory controlled by CPU 2 as well as display memory (Video R
This shared RAMI and ROM 2 constitute the main storage device A, and access is controlled by the display/main controller 3.

Here, the 1 display/main controller 3 accesses the shared RAMI and ROM 2 under the control of the CPU 4, controls data writing/reading operations with the CPU 4, and writes display data from the CPU 4 to the shared RAMI. The display data read out from the CPUJ is given to the display driver 5 to be displayed and output from the first display device 6. Note that 7 in the figure is an I10 controller that controls the keychain 8.

FIG. 2 is a circuit diagram showing the display/main controller 3t7jl.

The display/main controller 3 is a one-chip LIS, and includes an access fi control circuit 3-1, an address switching circuit 3-2, a read/write signal switching circuit 3-3, a wait signal generation circuit 3-4, etc. In the configuration, the access control circuit 3-1 is an access cycle control circuit that specifies CPU access and display access to the shared RAM 1, and an access designation signal A is output according to the specified state.
s is an address switching circuit 3-2. Read/write signal switching circuit 3-3. The signal is applied to the wait signal generation circuit 3-4.

In addition to inputting the CPU address from the CPU 4 to the address cutoff i1 circuit 3-2, the display address generation circuit 3-5
The address switching circuit 3-2 switches between the CPU address and the display address according to the access designation signal As output from the access control circuit 3-1, and provides the output to the main memory #MA. .

The read/write signal switching circuit 3-3 has signals from the CPU 4 to the C
In addition to the PU read/write signal CPUR/W, a display read/write signal DISR/W is also input from the 1-display read/write signal generation circuit 3-6, and the read/write signal switching circuit 3-3 is access control circuit 3
CP according to the access designation signal As output from -1.
Switches between the U read/write signal CPUR/W and the display read/write signal DISR/W, and outputs the main storage device A.
give to

The wait signal generation circuit 3-4 includes an access control circuit 3-4.
In addition to the access designation signal As input from 1, CP
The CPU read/write signal CPUR/W is input from U4, and the wait signal generation circuit 3-4 outputs the CPU read/write signal CPUR/W when the access control circuit 3-1 specifies display access. If is input, wait position to temporarily wait CPU access until display access is completed! Generate fWAIT and
Give to PU4.

Note that data is exchanged between the CPU 4 and the main storage device 1A via buffers 3-7, 3-8 that constitute the display/main controller 3, and display data read from the shared RAMI is Display/Main controller 3
Data is changed via buffers 3-7 that constitute #! circuit 3
-9 and then given to the display driver 5.

Next, the operation of this embodiment will be explained.

Now, the display device 6 is a liquid crystal display device with a 640×80 dot configuration, and when the display device 6 is driven by a 70Hz signal, 8-bit data is read from the shared RAMI and displayed at a rate of 1@ every 2.23 μS. It is assumed that the data is transferred to the driver 5.

In such a display access cycle, the access control circuit 3-1 specifies display access once every 2.23 μs. At this time, the address switching circuit 3-2 provides the display address generated by the display address generation circuit 3-5 to the shared RAMI, and the read/write signal switching circuit 3-3 provides the display address generated by the display address generation circuit 3-5 to the display address generation circuit 3-5. In order to apply the display read/write signal DISR/W generated by -6 to the shared RAMI, display data is read from the shared RAMI and sent to the display driver 5 via the data conversion circuit 3-9 to the display device 6. Displayed and output from.

Furthermore, when the access control circuit 3-1 specifies CPU access, the CPU address is output from the access control circuit 3-1 and given to the shared RAMI, and the read/write signal switching circuit 3-3 outputs the CPU address. A CPU read/write signal CPUR/W is output and applied to the shared RAMI.

Therefore, if the access control circuit 3-1 does not specify display access, in other words, the access control circuit 3-1f
When one CPU access is specified, the CPU 4 can perform data read/write operations to the shared RAMI.

On the other hand, when the access control circuit 3-1 specifies display access and the CPU read/write signal CPU/W comes from the CPU 4, the wait signal generation circuit 3-4 generates the wait signal WAIT. and gives it to CPU4. This causes the CPU 4 to temporarily suspend CPU access until the display access is completed.

#J3 diagram shows the generation timing of the wait signal WAIT, and even if the CPU read/write signal CPUR/W is received within the CPU access period, the wait signal generation circuit 3-4 outputs the wait signal WAIT. No but 1
CPU read/write signal CP within display access period
When receiving UR/W.

The wait signal generation circuit 3-4 generates and outputs a low active wait signal WAIT during display access.

In this way, in this embodiment, the normal main memory and display memory are shared, and the main memory controller and display controller are integrated into one chip, so the circuit structure is simplified by eliminating the number of chips, etc. At the same time, significant cost reductions are possible.

In addition, as mentioned above, CPU access is temporarily put on standby only when a CPU read/write signal comes during the display access period, which is performed once every < 2.23 ps, but once every four clocks of 8MHz. In the CPU that executes instructions, the processing speed can be suppressed to about 20% by entering a wait only once every five cycles.

In other words, even if the main memory controller and the display controller are integrated into one chip, the processing speed of the CPU will not be significantly reduced.

Also, normally the display memory refresh time is 512/8m.
5i? If the display memory is accessed once every 2 and 23 gs as described above, there is no need to refresh the display memory once every 15.625#Ls.

[Second Embodiment j FIG. 4 is an overall configuration diagram of a memory control device showing a second embodiment.

In addition, in Figure 4, the shared RAM II, ROM 12, display and
Main controller 13, CPU 14, display driver 1
5. Display device 1B, I10 controller 17. The keyboard 18 corresponds to the components shown in FIG. 1 described above.
In this embodiment, the shared RAM II is controlled by the main controller 13 as in the first embodiment, whereas the ROM 12 is directly controlled by the CPU 14.

That is, in this embodiment, the ROM 12 is separated from the control by the display/main controller 13 and accessed directly by the CPU 14.
Since the M12 can be freely accessed at any time, it is possible to further suppress a decrease in processing speed.

[Effect of the invention] According to the invention, the main memory and the display memory are shared,
In addition, even if the main memory controller and display controller are integrated into one chip, it is possible to control the CPU processing speed without significantly reducing it, making it possible to simplify the circuit configuration and significantly reduce costs. etc., it is extremely practical.

[Brief explanation of the drawing]

s1 figure~JF53F! ! J shows the first embodiment, FIG. 1 is an overall configuration diagram of the memory ig control MW, FIG. 2 is a detailed circuit configuration diagram of the display/main controller 3 shown in FIG. 1, and FIG. 3 is a wait signal diagram. A diagram showing the timing of occurrence of
FIG. 4 is an overall configuration diagram of a memory control device showing a second embodiment, and the pS diagram is an overall configuration diagram of a memory control device showing a conventional example. l, 11... Shared RAM, 3.13...
・Display・Main controller, 4.14...C
PU, 6.16・old・display device, 3-1・・・・
access control circuit, 3-2... address switching circuit, 3-3... read/write signal switching circuit,
3-4...Wait signal generation circuit, 3-5...
. . . Display address generation circuit, 3-6 . . . Display read/write signal generation circuit, A . . . Main memory # location. Patent Applicant Casio Computer Co., Ltd. Agent Patent Attorney Mitsuru Chonan - Male Patent Figure 1 Figure 3

Claims (1)

[Scope of Claims] A shared memory that is shared as a display memory in addition to the main memory controlled by the CPU, an access cycle control circuit that specifies CPU access and display access to this shared memory, and this access cycle control circuit. CP depending on the specified state of
an address switching circuit that switches and outputs a U address and a display address and provides it to the shared memory; and a CP according to the designated state of the access cycle control circuit.
a read/write signal switching circuit that switches and outputs a U read/write signal and a display read/write signal to provide the shared memory; a wait signal generation circuit that generates a wait signal that temporarily waits for CPU access until the display access is completed when the signal is input, and supplies the wait signal to the CPU, the access cycle control circuit, the address switching circuit, A memory control device characterized in that a read/write signal switching circuit and a wait signal generation circuit are integrated into one chip.