WO2008007419A1

WO2008007419A1 - Memory controller

Info

Publication number: WO2008007419A1
Application number: PCT/JP2006/313688
Authority: WO
Inventors: Atsushi Yamada; Yasutsugu Nagusa
Original assignee: Fujitsu Microelectronics Limited
Priority date: 2006-07-10
Filing date: 2006-07-10
Publication date: 2008-01-17

Abstract

An access control unit receives an access request supplied through a system bus and provides a memory with an internal access request to access the memory in response to the received access request. An image processing unit carries out image processing for an image data supplied through the system bus. A writing image selecting unit selects either the image data processed by the image processing unit or the image data supplied through the system bus in accordance with a writing selection instruction, and outputs the selected image data to the memory. Thus, the image data that does not pass through the system bus but are processed by the image processing unit can be written into the memory. As a result, when the memory is accessed in relation to the image processing, the utilization of the system bus can be prevented from falling down.

Description

Specification

Memory controller technology

The present invention relates to a memory controller for controlling memory access.

Background art

Generally, a memory controller is arranged between a system bus and a memory, and accesses the memory in response to an access request output from a master controller such as a CPU.

On the other hand, in an electronic device (such as a digital camera) having an image processing function for rotating or resizing an image, an image processing controller that performs image processing is connected to the system bus and operates as a master controller. For example, the image is rotated by converting the coordinates of the image data to which the address is assigned (see, for example, Patent Document 1). In this type of system, the image data transferred from the imaging unit is written in the memory. Thereafter, the image data is read from the memory by the image processing controller, and image processing is performed. Then, the image processing controller writes the image processed image data in the memory.

Patent Document 1: Japanese Patent Laid-Open No. 6-40093

Disclosure of the invention

Problems to be solved by the invention

[0003] In the electronic apparatus having the image processing function described above, the image processing controller reads and writes image data using the system bus. For this reason, when image processing is performed, the usage rate of the system bus increases. Also, the CPU cannot use the system bus while image data is being transferred to the system bus. As a result, system performance is degraded.

An object of the present invention is to prevent the usage rate of a system bus from being lowered when a memory is accessed during image processing.

Means for solving the problem

In one form of the memory controller of the present invention, the access control unit is connected via a system bus. The internal access request for accessing the memory is output to the memory according to the received access request. The image processing unit performs image processing on image data supplied via the system bus. The writing image selection unit selects either the processed image data processed by the image processing unit or the image data supplied via the system bus according to the writing selection instruction, and outputs the selected data to the memory. To do. As a result, the processed image data processed by the image processing unit can be written to the memory without going through the system bus. As a result, it is possible to prevent the usage rate of the system bus from being lowered when the memory is accessed during image processing.

In a preferred example of one aspect of the present invention, the read image selection unit outputs image data read from the memory to either the image processing unit or the system bus according to the read selection instruction. The image processing unit performs image processing on the image data supplied via the read image selection unit, and outputs the processed image data subjected to the image processing to the system bus. Since the image processed image data is read out simply by accessing the memory, the controller accessing the memory can access the memory as if it were held in the image processed image data S memory. . It is not necessary to perform image processing by an image processing controller after image data has been read out to the system bus. For this reason, it is possible to prevent the system bus usage rate from decreasing.

[0006] Preferably, in one example of the present invention, the image processing control unit operates in response to an internal processing request supplied via the system bus, reads image data from the memory, and reads the read image data. Write to memory. As a result, it is possible to copy the image data held in the memory without using the system node to another area of the memory. The image processing control unit supplies the image data read from the memory to the image processing unit, and writes the processed image data processed by the image processing unit to the memory. As a result, it is possible to perform image processing on the image data held in the memory without using the system bus. As a result, the system bus usage rate can be prevented from decreasing. The invention's effect

[0007] When the memory is accessed during image processing, it is possible to prevent the system bus usage rate from decreasing. Brief Description of Drawings

FIG. 1 is a block diagram showing a first embodiment of the present invention.

2 is a block diagram showing a bus matrix of the system shown in FIG.

FIG. 3 is a block diagram showing a comparative example of the present invention.

4 is a block diagram showing a bus matrix of the system shown in FIG.

FIG. 5 is a block diagram showing a second embodiment of the present invention.

FIG. 6 is a block diagram showing a third embodiment of the present invention.

FIG. 7 is a block diagram showing a fourth embodiment of the present invention.

FIG. 8 is a block diagram showing a fifth embodiment of the present invention.

FIG. 9 is a block diagram showing a sixth embodiment of the present invention.

FIG. 10 is a block diagram showing a seventh embodiment of the present invention.

FIG. 11 is a block diagram showing an eighth embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the figure, the signal lines indicated by bold lines are composed of a plurality of lines. Some of the blocks to which the bold lines are connected are composed of multiple circuits. The same reference numerals as the signal names are used for signal lines through which signals are transmitted. FIG. 1 shows a first embodiment of the memory controller of the present invention. The memory controller MCNT is installed in a system SYS (electronic equipment) such as a digital camera. The system S YS includes the memory MEM accessed by the memory controller MCNT, the CPU, DMAC, camera interface unit CAMIF, display interface unit DISPIF and arbiter ARB connected to the system bus SYSB together with the memory controller MCNT, and the display interface unit DISPIF. A display DISP connected to the camera, and a camera unit CAM connected to the camera interface unit CAMIF.

For example, the memory controller MCNT, CPU, DMAC, camera interface unit C AMIF, and arbiter ARB are configured as one chip as a system LSI. The memory MEM is, for example, an SDRAM chip, and stores image data taken by the camera unit CAM and CPU work data. The memory MEM may store programs executed by the CPU in the memory MEM! /. Display interface unit DISPI F is, for example, a liquid crystal display controller. Display DISP is, for example, a liquid crystal display. The system LSI and memory MEM are mounted on the system board. The camera unit CAM and display DISP are connected to the system bus SYSB via connectors attached to the system board.

[0011] The memory controller MCNT accesses the memory MEM in response to an access request from the bus master (CPU, DMAC, DISPIF and CAMIF). The CPU controls the operation of the system SYS and always operates as a master controller. DMAC, DISPIF, and CAMIF operate as a master controller when accessing the memory MEM, and operate as a slave controller when accessing the CPU. The camera interface unit CAMIF receives camera unit CAM force image data having an image sensor such as a CCD.

[0012] The arbiter ARB determines the use order (priority order) of the system node SYSB when requests output from the CPU, DMAC, DISPIF, and CAMIF compete to use the system bus SYSB. The CPU, DMAC, DISPIF, and CAMIF that operate as the master controller use the master port MP to input and output signals. DMAC, DISPIF, and CAMIF that operate as slave controllers use the slave port SP to input and output signals.

[0013] The memory controller MCNT has an image selection unit IMGSEL, an access control unit ACSCNT, an image processing unit IMGPU, an image register IMGREG, and a first port P1 and a second port P2 connected to the system bus SYSB. .

The first and second ports P1-2 function as slave ports. The first port P1 is an input-only port having an input buffer, and the second port is an input / output port having an input buffer and an output buffer. A symbol (W) indicated on the signal line in the figure indicates that write data to the memory MEM is transferred. The symbol) indicates that the read data from the memory MEM is transferred. The sign (RZW) indicates that the write data to the memory MEM and the read data of the memory MEM force are transferred.

[0014] The first port P1 is, for example, an image output from the camera interface unit CAMIF. The data is received via the system bus SYSB, and the received image data is output to the image processing unit IMGPU via the data line DT1, the address line AD 1, and the command line CMD 1. The second port P2 receives the address AD2 and command CMD2 for accessing the memory MEM and the data DT2 to be written to the memory MEM via the system bus SYSB, and outputs the data DT2 read from the memory MEM to the system bus SYSB. . Here, the data DT2 is one of image data output from the camera interface unit CAMIF, image data accessed by the CPU or DMAC for display on the display DISP, and work data used by the CPU. is there. When a program is stored in the memory MEM, the data DT2 may be program data.

[0015] The input terminals of the ports P1-2 that receive image data are connected to system data lines that are wired independently of each other as the system bus SYSB. CPU, DMAC, DISPIF, and CAMIF output image data to the system data line connected to port P1 when image processing is performed by the image processing unit IMGPU. On the other hand, the CPU, DMAC, DISPIF, and CAMIF, when writing image data to the memory MEM without image processing, output the image data to the system data line connected to the port P2.

[0016] The access control unit ACSCNT is an access request supplied via the system bus SYSB.

(Address AD2 and command CMD2) and the access request (address AD1 and command CMD1) supplied via the image processor IMGPU are output to the memory MEM as the internal address IAD and internal command ICMD. The access control unit ACSCNT has a function to hold a plurality of access requests. Even when a large number of access requests are received in a short period of time, the internal address IAD and the internal command are optimized for the memory MEM. Generate ICMD. The access control unit ACSCNT includes a circuit that generates a refresh request for causing the memory MEM to perform a refresh operation, and an arbiter that determines the priority order of the access request and the refresh request. Furthermore, the access control unit ACSCNT writes the synchronization signal SYNC and selects the image to output the image data IDT output from the write image selection unit WINGSEL, which will be described later, to the memory MEM together with the internal access request (IAD, ICMD). Output to WINGSEL.

[0017] The image processing unit IMGPU performs different types of image processing using the image data DT1. A plurality of image processing circuits are provided. Specifically, the image processing unit IMGPU includes a rotation processing circuit ROT that rotates the image data DT1, a mirror processing circuit MIR that mirrors the image data DTI, a resizing processing circuit RES that changes the size of the image data DTI, and In addition, a data conversion circuit CNV that converts the data format of image data DT1 is built in as an image processing circuit. For example, the data conversion circuit CNV converts RGB data into YUV data, or converts some YUV data into YUV data in another format. The processed image data PDT processed by the image processing unit IMGPU is supplied to the image selection unit IMGSEL.

Image processing circuit for performing image processing Processing selection instructions for selecting ROT, MIR, RES, and CNV, and parameters necessary for each image processing are set in the image processing area of the image register IMGREG. The value of the image processing area is set by writing and accessing the image processing area by the CPU using the second port P2. In this way, the image register IMGREG functions as a processing selection unit that selects one of the image processing circuits ROT, MIR, RES, and CNV in accordance with an image processing instruction supplied by the CPU power via the system bus SYSB. To do.

The image selection unit IMGSEL has a writing image selection unit WIMGSEL. The write image selection unit WIMGSEL sets either the processed image data PDT processed by the image processing unit IMGPU or the image data DT2 supplied via the system bus SYSB in the selected area of the image register IMGREG. Select according to the selected value (write selection instruction). The write image selection unit WIMGSEL has a holding circuit that temporarily holds the selected image data, and outputs the held image data to the memory MEM via the internal data line IDT in synchronization with the synchronization signal SYNC. To do. The selection value set in the selection area of the image register IMGREG is set by writing and accessing the selection area by the CPU using the second port P2.

[0020] The access control unit ACSCNT selects one of the access requests AD2 and CMD2 from the second port P2 or the access request AD1-1 and CMD1-1 from the image processing unit IMGPU, and the internal access request IAD and ICMD. And the synchronization signal SYNC is output in synchronization with the internal access request IAD and ICMD output. Memory MEM force The read image data and work data are output from the second port P2 to the system bus SYSB via the data line with the internal data line ID T and the sign (R). By directly transferring the read data to the second port P2 bypassing the image selection unit IMGSEL, the CPU, DMAC, DISPIF and CAMIF can read the data with the same memory access as the conventional read access.

FIG. 2 shows a bus matrix of the system SYS shown in FIG. In this embodiment, the CPU, DMAC, DISPIF, and CAMIF can operate as the master controller MST, and the DISPIF, DMAC, CAMIF, and memory controller MCNT can operate as the slave controller SLV. Since the memory controller MCNT has two ports P1 -2, it is recognized as two slave controllers SLV. For this reason, the arbiter ARB has only to manage the connection between the four master controllers MST and the five slave controllers SLV.

[0022] The memory controller MCNT described above operates as follows. For example, when storing the image data captured by the camera cut CAM in the memory MEM without image processing, the camera interface unit CAMIF sends the image data, the write command CMD2 and the write address AD2 to the second port P2. Output. The write image selection unit WIMGS EL selects the data line DT2 in advance by setting the image register IMGREG. The access control unit ACSCNT outputs the internal write command ICMD, the internal write address IAD, and the synchronization signal SYNC in synchronization with the reception of the write command CMD2 and the write address AD2. The write image selection unit WIMGSEL outputs the image data received from the data line DT2 to the data line IDT in synchronization with the synchronization signal SYN C. As a result, the image data is written to the memory MEM in synchronization with the write command CMD.

[0023] When displaying the image data held in the memory MEM on the display DISP, for example, the DMAC outputs the read command CMD2 and the read address AD2 to the second port P2. The access control unit ACSCNT outputs the internal read command ICMD and the internal read address IAD in synchronization with the reception of the read command CMD2 and the read address AD2. In the read operation cycle, the synchronization signal SYNC is not output. Yes. The image data is also read from the memory MEM and output to the system bus SYSB via the data lines IDT and DT2. The DMAC receives image data via the system bus SYSB and outputs the received data to the display DISP. The image is then displayed on the display DISP. In another example, DISPIF outputs the read command CMD2 and read address AD2 to the second port P2. The access control unit ACSCNT outputs the internal read command ICMD and the internal read address IAD in synchronization with the reception of the read command CMD2 and the read address AD2. In the read operation cycle, the synchronization signal SYNC is not output. Image data is read out from the memory MEM and output to the system bus SYSB via the data lines IDT and DT2. DISPIF receives image data via system node SYSB and outputs the received data to display DISP. The image is then displayed on the display DISP.

[0024] On the other hand, when image data captured by the camera unit CAM is processed and stored in the memory MEM, the camera interface unit CAMIF receives the image data DT1, the write command CMD1, and the write address AD1 in the first port P1. Output to. The write image selection unit WIMGSEL selects the data line PDT in advance by setting the image register IMGREG. For example, the rotation processing circuit ROT selected by the image register IMGREG processes the image data so that the image is rotated by a predetermined angle, the processed image data is the data line PDT, and the converted address is the address line AD1. — 1, Output command to command line CMD1—1. Here, the time required for image rotation is T1.

[0025] The access control unit ACSCNT selects one of the address AD1-1, command CMD1-1 output from the image processing unit IMGPU, the address AD2, command CMD2 from the second port P2, and the internal write command. Outputs ICMD, internal write address IAD, and sync signal S YNC. When performing image processing, the original image data is not written to the memory MEM. By writing only the image data after image processing into the memory MEM, the area for storing the image data in the memory MEM can be reduced.

In the present embodiment, a dedicated port P11S memory controller MCNT that receives image data for performing image processing is formed. Data line DT2 is directly connected to MEM via data line ID T. For this reason, for example, the CPU is an image processing circuit. During image processing by ROT, MIR, RES, and CNV, data or other image data can also be read from memory MEM using port P2.

FIG. 3 shows a comparative example of the present invention. In the system SYS shown in FIG. 3, the four image processing circuits ROT, MIR, RES, and CNV (macro) force shown in FIG. 1 are connected to the system bus SYSB. The memory controller MCNT has only the function of accessing the memory MEM and does not include the image processing circuits ROT, MIR, RES, and CNV. For this reason, the memory controller MCNT has only one slave port SP. Each image processing circuit ROT, MIR, RES, CNV has a master port MP and a slave port SP.

In the system SYS shown in FIG. 3, for example, when image data captured by the camera unit CAM is rotated and stored in the memory MEM, the camera interface unit CAMIF first stores the image data in the memory. Write to MEM. Next, the rotation processing circuit ROT reads the image data written in the memory MEM, performs rotation processing, and writes the image data subjected to the rotation processing to the memory MEM. For this reason, image data appears three times on the system bus SYSB for each image process. In other words, in the system SYS shown in FIG. 1, the frequency of image data appearing on the system bus SYSB is one third that of the system SYS shown in FIG.

FIG. 4 shows a bus matrix of the system SYS shown in FIG. In this example, the image processing circuits ROT, MIR, RES, and CNV can operate as a master controller MST and a slave controller SLV. The memory controller MCNT operates as a slave controller SLV. For this reason, the arbiter ARB must manage the connection between the eight master controllers MST and the eight slave controllers SLV. Therefore, the circuit scale of the arbiter A RB increases as compared to FIG. In other words, in the present invention, the circuit scale of the arbiter ARB can be reduced, and the system cost can be reduced.

As described above, in the first embodiment, when image processing is performed on image data and the processed image data is stored in the memory MEM, the image data appears only once on the system bus SYSB. Therefore, when the memory MEM is accessed along with image processing, it is possible to prevent the usage rate of the system bus SYSB from being lowered, and the performance of the system SYS can be improved.

FIG. 5 shows a second embodiment of the memory controller of the present invention. First embodiment The same elements as those described in the above are denoted by the same reference numerals, and detailed description thereof will be omitted. The memory controller MCNT of this embodiment has a common port PC instead of the port P1-2 in the first embodiment. The common port PC is an input / output port with input and output buffers. The input of the image processing unit IMGPU is connected to the common data line DT. Other configurations are the same as those of the first embodiment. That is, the system SYS is an electronic device such as a digital camera, for example.

In this embodiment, image data regardless of whether or not the image processing is performed is supplied to the common data line DT via the common port PC. The write image selection unit WIMGS EL selects the data line PDT when image processing is performed, and selects the data line DT when image processing is not performed. For this reason, even when image data to be subjected to image processing is supplied to the common port PC, it is possible to prevent erroneous writing to the image data memory MEM. Only system data lines connected to the common port PC are formed on the system bus SYSB. For this reason, it is not necessary to form a dedicated data line for transferring image data for performing image processing in the system node SYSB.

[0032] The common data line DT is directly connected to the memory MEM via the data line IDT. For this reason, as in the first embodiment, for example, the CPU reads data or another image data using the port P2 during the image processing by the image processing circuits ROT, MIR, RES, and CNV. be able to.

As described above, also in the second embodiment, it is possible to obtain the same effect as that of the first embodiment described above. Furthermore, in this embodiment, the size of the memory controller MCNT can be reduced by forming the common port PC in the memory controller MCNT. It is also possible to prevent an increase in the number of system data lines wired to the system bus SYSB. Therefore, an increase in system cost can be prevented.

FIG. 6 shows a third embodiment of the memory controller of the present invention. The same elements as those described in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. In this embodiment, the memory controller MCNT is configured by adding an image processing control unit IMGCNT to the memory controller MCNT of the first embodiment. Other configurations, except for the signal line wired to the image processing control unit IMGCNT, The same as in the first embodiment. That is, the system SYS is an electronic device such as a digital camera, for example.

[0034] The memory controller MCNT of this embodiment has a function of writing back image data read from the memory MEM to the memory MEM and a function of processing the read image data of the memory MEM and writing it back to the memory MEM. Have. For this purpose, the image processing control unit IM GCNT operates in response to an internal processing request (CMD 2, AD2) supplied to the port P2 via the system bus SYSB, and the memory MEM power is also imaged via the internal data line IDT. Data

BJC sticks out.

[0035] The address line AD2, command line CMD2, and data line DT2 connected to the image processing control unit IMGCNT are used to access the setting unit of the image processing control unit IMGCNT and start the image processing control unit IMGCNT. Wired. Image processing control unit The IMGCNT setting unit includes a register for setting the read area of the memory MEM, a register for selecting the image processing circuits ROT, MIR, RES, and CNV for image processing, and image processing for image processing. A register for setting a write area of the memory MEM for storing data and a register having a start bit for starting the image processing control unit IMGCNT.

[0036] When the value set in the image register IMGREG indicates image processing, the image processing control unit IMGCNT writes the image data read from the memory MEM to the memory MEM. As described above, the image processing control unit IMGCNT has a function of performing read access and write access to the memory MEM. When accessing the memory MEM, the image processing control unit IMGCNT directly outputs an access command and an access address to the internal command line ICMD and the internal address line IAD. By making the area for writing image data (write address) different from the area for reading image data (read address), a copy function from memory MEM to memory MEM can be realized. That is, the image processing control unit IM GCNT operates as a DMAC built in the memory controller MCNT.

On the other hand, when the value set in the image register IMGREG indicates image processing, the image processing control unit IMGCNT supplies the read image data to the image processing unit IMGPU via the processing data line IMGDT, and Processing unit Writes processed image data processed by IMGPU to memory MEM. As described above, also in the third embodiment, the same effect as in the first embodiment described above can be obtained. Furthermore, in this embodiment, it is possible to perform image processing on the image data held in the memory MEM without reading out the image data to the system node SYSB, and write the processed image data back into the memory MEM.

FIG. 7 shows a fourth embodiment of the memory controller of the present invention. The same elements as those described in the first, second, and third embodiments are denoted by the same reference numerals, and detailed description thereof will be omitted. The memory controller MCNT of this embodiment has a common port PC instead of the port P1-2 in the third embodiment (FIG. 6). That is, the memory controller MCNT is configured by combining the second and third embodiments. Other configurations are the same as those of the third embodiment. The system SYS is an electronic device such as a digital camera. In the fourth embodiment, the same effects as those of the first, second, and third embodiments described above can be obtained.

FIG. 8 shows a fifth embodiment of the memory controller of the present invention. The same elements as those described in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. In this embodiment, an image selection unit IMGSEL2 is formed instead of the image selection unit I MGSEL of the first embodiment (FIG. 1). The first port P1 is formed as an input / output port. The image processing unit IMGPU performs image processing on the image data supplied via the first port P1, outputs the processed image data to the data line PDT, and a memory via the internal data line IDT and the image selection unit IMGSEL. It has a function to perform image processing on the image data supplied from the MEM and output the processed image data to the system bus SYSB via the data line DT1. Other configurations are the same as those in the first embodiment. That is, the system SYS is an electronic device such as a digital camera.

[0040] The image selection unit IMGSEL2 includes a read image selection unit RIMGSEL and a write image selection unit WIMGSEL of the first embodiment. The read image selection unit RIMGSEL reads the image data to be read from the memory MEM via the internal data line IDT according to the selection value (read selection instruction) set in the selection area of the image register IMGREG. Or, output the data line DT2! Read from memory MEM The processed image data is output to the image processing unit IMGPU when image processing is performed, and is output to the data line DT2 when image processing is not performed. The sync signal SYNC is used only for the write image selection unit WIMGSEL. The image register IMGREG is accessed using the second port P2 as in the first embodiment.

As described above, also in the fifth embodiment, the same effect as in the first embodiment described above can be obtained. Furthermore, in this embodiment, a master controller such as a CPU can read out image data that has undergone image processing only by accessing the memory MEM. For this reason, the master controller can access the memory MEM as a result of the image data subjected to image processing being held in the memory MEM. It is not necessary to perform image processing after the image data is read to the system bus SYSB. For this reason, it is possible to prevent the usage rate of the system bus SYSB from being lowered and to prevent the system performance from being lowered.

FIG. 9 shows a sixth embodiment of the memory controller of the present invention. The same elements as those described in the first, second, and fifth embodiments are denoted by the same reference numerals, and detailed description thereof will be omitted. The memory controller MCNT of this embodiment has a common port PC instead of the port P1-2 in the fifth embodiment (FIG. 8). That is, the memory controller MCNT is configured by combining the second and fifth embodiments. Other configurations are the same as those of the fifth embodiment. The system SYS is an electronic device such as a digital camera. In the sixth embodiment, the same effects as those of the first, second, and fifth embodiments described above can be obtained.

FIG. 10 shows a seventh embodiment of the memory controller of the present invention. The same elements as those described in the first, third and fifth embodiments are denoted by the same reference numerals, and detailed description thereof will be omitted. In this embodiment, the memory controller MCNT is configured by adding the image processing control unit IMGCNT of the third embodiment (FIG. 6) to the memory controller MCNT of the fifth embodiment (FIG. 8). Other configurations are the same as those of the fifth embodiment. The system SYS is an electronic device such as a digital camera. In the seventh embodiment, the same effects as those of the first, third, and fifth embodiments described above can be obtained.

FIG. 11 shows an eighth embodiment of the memory controller of the present invention. 1st, 2nd, 2nd The same elements as those described in the third and fifth embodiments are denoted by the same reference numerals, and detailed description thereof will be omitted. The memory controller MCNT of this embodiment has a common port PC instead of the port P1-2 in the seventh embodiment (FIG. 10). That is, the memory controller MCNT is configured by combining the second and seventh embodiments. Other configurations are the same as those of the seventh embodiment. The system SYS is an electronic device such as a digital camera, for example. In the eighth embodiment, the same effects as those of the first, second, third, and fifth embodiments described above can be obtained.

In the first embodiment described above, the example in which the system data lines respectively corresponding to the ports P1-2 are formed on the system bus SYSB has been described. The present invention is not limited to such an embodiment. For example, a system data line common to ports P1-2 may be formed on the system bus SYSB. In this case, for example, a register indicating which image data is supplied to the port P1-2 is formed in the memory controller MCNT. The input buffer that is formed at port P1-2 and receives the image data permits data reception according to the register setting value. Similarly, in the third, fifth and seventh embodiments, a system data line common to the port P1-2 may be formed on the system bus SYSB.

In the first embodiment described above, the access control unit ACSCNT outputs the synchronization signal SYNC after the image processing time recognized in advance, and the image selection unit IMGSEL performs image synchronization in synchronization with the synchronization signal SYNC. An example of outputting data to the memory MEM was described. The present invention is not limited to such embodiments. For example, the image selection unit IMGSEL outputs a completion signal to the access control unit ACSCNT in synchronization with the completion of the image processing, and the access control unit ACSCNT outputs the internal access requests IAD and ICMD in response to the completion signal. Good. In addition, the access control unit ACSCNT outputs the synchronization signal SYNC in response to the completion signal.

In the embodiment described above, an example in which the present invention is applied to a memory controller mounted on a digital camera has been described. The invention is not limited to the powerful embodiments. For example, the present invention may be applied to a memory controller mounted on a mobile phone having a camera function or a memory controller mounted on a video camera. In the above-described embodiment, the example in which the present invention is applied to a memory controller that accesses SDRAM is described. The invention is not limited to the powerful embodiments. For example, the present invention may be applied to a volatile memory such as DRAM or SRAM or a non-volatile memory such as flash memory.

In the embodiment described above, the example in which the four image processing circuits ROT, MIR, RES, and CNV are formed in the image processing unit IMGPU has been described. The invention is not limited to the powerful embodiments. For example, at least two image processing circuits ROT, MIR, RES, and CNV may be formed in the image processing unit IMGPU. Alternatively, an image processing circuit other than the image processing circuits ROT, MIR, RES, and CNV may be formed.

As described above, the force that has been described in detail for the present invention. The above-described embodiments and modifications thereof are merely examples of the present invention, and the present invention is not limited thereto. Obviously, modifications can be made without departing from the scope of the present invention.

Industrial applicability

The present invention can be used for a memory controller for controlling memory access.

Claims

The scope of the claims

[1] In response to an access request supplied via the system bus,

An access control unit for outputting an internal access request for accessing the memory to the memory;

An image processing unit that performs image processing on the image data supplied through the system bus, and writes whether the processed image data processed by the image processing unit and the! / 供給 deviation of the image data supplied through the system bus A memory controller, comprising: a writing image selection unit that selects according to a selection instruction and outputs the selected image data to the memory.

[2] The memory controller according to claim 1,

A memory comprising: a first port connected to the system bus and receiving image data supplied to the image processing unit; and a second port receiving image data supplied to the write selection unit. controller.

[3] The memory controller according to claim 1,

A memory controller, comprising: a common port connected to the system bus for commonly receiving image data supplied to the image processing unit and image data supplied to the writing selection unit.

[4] The memory controller according to claim 1,

The image processing unit includes a plurality of image processing circuits for performing different types of image processing,

The memory controller includes a processing selection unit that selects whether the image processing circuit performs image processing according to an image processing instruction supplied via the system bus. And memory controller.

[5] The memory controller according to claim 4,

The image processing unit includes at least a rotation processing circuit that rotates image data, a mirror processing circuit that mirrors image data, a resizing processing circuit that changes the size of image data, and a data conversion circuit that converts a data format of image data. A memory controller, comprising two as the image processing circuit.

[6] The memory controller according to claim 1,

When the image processing is performed by the image processing unit, the access control unit outputs the internal access request and the synchronization signal in synchronization with completion of image processing, and the write image selection unit is configured to output the synchronization signal. A memory controller for outputting the processed image data in synchronism with the image data.

[7] The memory controller according to claim 1,

A read image selection unit that outputs image data read from the memory to either the image processing unit or the system bus in response to a read selection instruction; and the image processing unit passes through the read image selection unit. A memory controller having a function of performing image processing on the supplied image data and outputting the processed image data to the system bus.

[8] The memory controller according to claim 1,

A memory comprising an image processing control unit that operates in accordance with an internal processing request supplied via the system bus, reads image data from the memory, and writes the read image data to the memory. controller.

[9] The memory controller according to claim 8,

The memory controller, wherein the image processing control unit supplies the image data read from the memory to the image processing unit, and writes the processed image data processed by the image processing unit to the memory.

[10] The memory controller according to claim 9,

[11] The memory controller according to claim 10,

The image processing unit includes: a rotation processing circuit that rotates image data; a mirror processing circuit that mirrors image data; a resizing processing circuit that changes the size of image data; A memory controller comprising at least two data conversion circuits for converting data format of data as the image processing circuit.