JPH01131969A - Image processing device - Google Patents

Abstract

PURPOSE:To easily permit the extension of an image memory or a processor, to improve the universality of a processing, and to permit an address operation in a few common bus by providing a selector corresponding to each image memory and also, providing the selector corresponding to each processor. CONSTITUTION:Plural selectors S1-Sm which perform input selection from a common bus 20 independently for the horizontal address and the vertical address of the image memories VRAMi-VRAMm and data input are provided corresponding to each image memory, and also, plural processors P1-Pn are provided, and the plural selectors SP1-SPn possible to select the input of the processors from the common bus 20 independently are provided corresponding to each processor. In such a way, it is possible to perform data transfer between the addresses with different from each other, and also, to facilitate the extension of the image memory or the processor, and to accelerate the processing by improving the universality of the device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing apparatus, and more particularly to a bus configuration for realizing high-speed processing.

[Conventional technology]

As an image processing apparatus, there is a conventional one shown in FIG. 4, for example. In the figure, 1, 2.3 are image memories, 4 is a common bus consisting of 5 trees of address buses X, Y, and data buses A, B, C, and 5 is a predetermined image data input from the image memory of 6. a processor that performs the calculation and writes the result to another image memory; ．． 7, 8.9 are output buffers, 10 is an address control unit that outputs address data to each image memory 1, 2.3, 11 is a controller that controls the processor 5, address control unit 10, etc., and 12 is an image memory VRAM1 to This is a VRAM controller that controls VRAMm.

In such a device, when performing processing such as adding image data in image memories 1 and 2 and writing them into image memory 3, for example, image data input from data buses A and B are added to image memory 1.
．． After the processor 5 adds the data of 2, the result is output to the data bus C, and the processor 5
It is sufficient to write the output data to the image memory 3. Incidentally, at this time, the address control section 10 controls the image memory 1゜2,
Scan the address of 3 one screen (for example, Japanese Patent Application Laid-Open No. 61-1
53774).

[Problem that the invention seeks to solve]

By the way, in such conventional image processing devices,
The image memory address is input from a fixed bus,
Furthermore, since input to the processor is also performed from a fixed bus, there is a problem in that processing that requires calculation of image memory addresses, such as affine transformation (rotation of figures), cannot be executed. Furthermore, even if the number of image memories and processors is increased, or the number of buses is increased, there is a problem that processing flexibility and versatility are lacking due to connection constraints, and processing speed cannot be increased.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to enable address calculations under a small number of common buses, and to make it easier to add image memories and processors to provide processing versatility.

(Means for solving the problems) In order to achieve the above objectives and solve the problems of the prior art,
An image processing device according to the present invention includes a plurality of image memories connected to a common bus, and a calculation result based on image data from one image memory inputted via the common bus to another image via the common bus. In an image processing device including a processor that writes to the memory, a horizontal address of each image memory,
A plurality of selectors are provided for each image memory to independently select inputs from the common bus for vertical addresses and data inputs, and a plurality of processors are provided so that the inputs of each processor can be independently selected from the common bus. Multiple selectors were provided for each processor.

〔Example〕

Hereinafter, the present invention will be described in detail based on the accompanying drawings. FIG. 1 shows an example of an image processing apparatus according to the present invention.

In the figure, reference numeral 20 denotes a common bus consisting of data buses A, B, C and address buses X, Y;
V RA M m is a plurality of (m) image memories, S□~
Sm is a selector provided corresponding to each image memory VRAM1 to VRAMm. The selectors 81 to 5ITl select at least the address bus X and the data bus A for the X address.

One of B and C is selected, and the Y address is also at least address bus Y and data bus A.

One of data buses A, B, and C is selected, and one tree is selected from data buses A, B, and C for data input. Also, image output (ou
t), data bus A.

Output buffer B□~ to output to either B or C
B, set up n. Further, P-Pn are a plurality of (n) processors that execute predetermined operations on image data, each processor P□-Pn has at least two inputs, and a data bus A,
Input can be selected from any of address buses B, C, and address buses X and Y. In addition, processors P1 to Pn
The output can be output to any of data buses A, B, and C via output buffers BP□ to BPn. As shown in FIG. 2, the processors P□ to Pn each have an ALU (operation unit) that performs addition/subtraction, logic, and calculations via an LUT (lookup table) that performs function conversion such as constant multiplication, sin, and cos. processing device).

Writing to the LUT (initial setting) is performed by a host computer or the like. Returning to FIG. 1, reference numeral 21 denotes a VRAM controller which controls read and write of each of the image memories VRAM1 to VRAMm and also controls selectors S to Sm. This control by the VRAM controller 21 is performed independently for each of the image memories VRAMI to VRAMm. Further, 22 and 23 are an address control section and a controller, respectively, which are similar to those in the conventional device. Note that although these are all controlled by a host computer, illustration is omitted for the sake of simplicity.

Next, the operation of this apparatus will be explained based on FIG. 3, taking affine transformation (image rotation) as an example.

Now, it is assumed that an affine transformation is performed based on the data in the image memory VRAM1 in which the original image is stored, and the transformed data is stored in the image memory VRAMm. In this case, the image memory VRAM1 is set to the read state, data bus A is selected for the X address and data bus B is selected for the Y address via the selector S□, and the processor P□,
The p and q addresses output by Pn to the data buses A and B, respectively, are input to the image memory VRAM1, and the image data stored in the image data VRAM1 is output to the data bus C. On the other hand, the image memory VRAMm is set to the write state, and selects the address bus X for the X address and the address bus Y for the Y address via the selectors S, . While inputting the X address, the common bus C is selected for inputting image data, and data from the image memory VRAM1 is inputted.

Further, the inputs of the processors p, pn select the address bus X and the address bus Y via the selectors SP□, sp, respectively, and x,
Input each X address. In addition, each processor P
>, Pn performs constant multiplication in the LUT, and performs addition and calculation in the ALU, and calculates p=ax+by q=cx+dy, respectively. Here, constants a, b, c, and d are constants corresponding to rotation angles. In addition, x and y are the address control unit 22
is the address after image rotation output by image memory V
This is the address of RAMm.

Further, p and q are addresses of the original image, that is, addresses of the image memory VRAM1. Output of processor P□,
That is, the P address is input to the image memory VRAM1 through the data bus A, and the output of the processor Pn, that is, the q address, is input to the image memory VRAM1 through the data bus B.
Input to RAMI. Then, the image memory VRAM1 outputs image data to the data bus C using these p and q addresses, and this is stored in the image memory VRAMm, so this device allows data transfer between different addresses. be. Note that the address control unit 22
When the screen is controlled to be scanned, one rotated image is stored in the image memory VRAMm, and the process ends.

We have explained affine transformation above, but with this kind of bus configuration, it is easy to add processors and image memory, and by increasing the number of common buses, complex parallel processing becomes possible and speeds up processing. be able to.

(Effects of the Invention) As explained above, the image processing device according to the present invention has a selector that independently selects inputs from a common bus for the horizontal address, vertical address, and data input of each image memory, which corresponds to the image memory. In addition to providing a selector for each processor that allows the input of each processor to be selected independently from the common bus, it is possible to transfer data between different addresses, and it is also easy to add image memory and processors. This has the effect of improving the versatility of the device and speeding up processing.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of an image processing device according to the present invention, FIG. 2 is a block diagram showing an example of a processor according to the present invention, and FIG. 3 is a diagram showing an example of the operation of the image processing device according to the present invention. , FIG. 4 is a diagram showing an example of a conventional image processing apparatus. 20...Common bus 21...VRAM controller 22...Address control unit 23...Controller VRAM1~VRAMm-Image memory S□~5ffl, sp□~SPn...Selector Patent applicant Nissan Motor Co., Ltd.

Claims (1)

[Claims] An image comprising a plurality of image memories connected to a common bus, and a processor that writes a calculation result based on image data from one image memory input via the common bus to another image memory via the common bus. In the processing device, a plurality of selectors are provided corresponding to each image memory to independently select inputs from the common bus for the horizontal address, vertical address, and data input of each image memory, and a plurality of processors are provided so that each processor An image processing device characterized in that a plurality of selectors are provided corresponding to each processor, each of which can independently select an input from a common bus.