JPS60218170A - Local window operation control system - Google Patents

Abstract

PURPOSE:To execute operation at a high speed with the small quantity of hardwares by counting up a counting means on the basis of a reference address and the lateral width size of two-dimensional data and controlling the address on a line buffer memory through a pointer. CONSTITUTION:A reference address is generated from a reference address counter 20, the lateral size is outputted from a lateral size storing register 21 and these outputs are selectively outputted from a data selector 22 and inputted to a counter 24. The counter 24 executes counting operation on the basis of the output of the data selector 22 and outputs the address of the line buffer memory.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an image processing device that performs local parallel processing used, for example, in noise removal and differential calculation processing, and particularly relates to an image processing device that performs local parallel processing used for noise removal, differential calculation processing, etc. The present invention relates to a local window operation control method that can handle images of 2000, and can reduce a local parallel operation section that conventionally had a size of nXn to a size of n.

[Prior art and problems]

For example, in image processing, local window processing is performed for noise removal, differential calculation, etc. In this case, an nxn size window is used to sequentially process data in a two-dimensional array. When performing processing using this window, the data within this window is output from memory and calculations are performed according to the purpose. 3
When performing noise removal processing using a ×3 window, as shown in Figure 1, read the data a - i of ■, determine the new value of e based on the average value, and then Data b-z is read out and a new value of f is determined based on the average value. In other words, the new i-cho of e is ding (a+b
+c+'d+e+f+g+h+yu1), and the new value of f is s(b+c+j
-)-e -1-f + k + h + i + I
t). Of course, each pixel may be weighted for calculation.

When such local processing is performed primarily by software, it is necessary to extract data in the vicinity of the central pixel in order to determine a new value, which requires complicated address calculations. Moreover, ■ in Figure 1,
As shown in (2), even if there is a large amount of data that overlaps with the previous data, it is necessary to read all of them by address, and therefore there is a drawback that it takes a long time to process the data. When locally parallel processing is performed using hardware, as shown in FIG. 2, data in a two-dimensional array stored in the memory M is sequentially read out in the same manner as rask scanning and processed by the arithmetic unit. The arithmetic unit includes shift registers 5GRI to 5RG5 (
5×5 size in this example) and line buffers LBUI to LB U 5 that hold at least one line of data.
, a local window arithmetic circuit unit WP that performs parallel processing in a pipeline manner, and a load table TB used when applying a load, and a two-dimensional array on the memory M that is input via an input register RG. The data are sequentially input and parallel processing is performed in a pipeline manner in the local window calculation circuit unit wp. However, this method has the disadvantage that the circuit scale increases in proportion to the window size n×n for locally parallel processing.

[Purpose of the invention]

An object of the present invention is to improve the above-mentioned drawbacks and to be able to perform local window operations at high speed and with a small amount of hardware. By providing only a line buffer memory and omitting the shift I register, and manipulating the address, the amount of circuitry and wiring in the input section can be reduced to 1/H, and images of arbitrary size can be created. It is an object of the present invention to provide a local window arithmetic circuit control method that can handle the following and further reduce the amount of circuitry and wiring of an nXn local window arithmetic circuit section to 1/n.

[Structure of the invention]

In order to achieve the above object, the local window arithmetic control method of the present invention provides a basic address counting means for generating basic addresses for manipulating addresses in the line buffer memory in a local window arithmetic processing device equipped with a line buffer. , a width size storage means for storing the width size of the two-dimensional data, an output selection means for selectively outputting the output of the basic address counting means or the width size storage means, and a counting operation is performed based on the output of the output selection means. The present invention is characterized in that a counting means is provided and the address of the line buffer memory is controlled by a pointer.

[Embodiments of the invention]

The present invention will be described in detail. The present invention takes advantage of the fact that when memory is used as a line buffer, addresses can be manipulated freely and internal data can be handled, and a line buffer control circuit is provided so that boundary processing can be performed for any image size. The local window calculation unit 178 can be reduced in size to 1/n.

An embodiment of the present invention will be described with reference to FIGS. 3 to 7.

FIG. 3 is a schematic diagram of a local window data generating section which is an embodiment of the present invention, FIG. 4 is a detailed diagram of its line buffer/address control circuit, and FIGS. 5 to 7 are diagrams explaining its operation. be.

In the figure, 10 is a line buffer address control circuit, 11
are registers, 12-1 to 12-5 are line buffer memories, 13-1 to 13-5 are registers, 14 is a local window calculation unit, 20 is a basic address counter, 21 is a width size storage register, 22 is data・Selector, 2
3 is a data inverter/local window inversion circuit which is an embodiment of the present invention, 24 is a counter, and 25 is a data inversion circuit 2.
6.27 is an OR circuit.

An outline of the data generation section will be explained with reference to FIG. 3, with reference to an example in which local parallel calculations are performed using a window size of 5×5. In other words, a register 11 that launches input data using a synchronous lock Φ0, and five line buffer memories (addresses O to 16383) 12-1.
12-5, a line buffer address control circuit 10 that controls the address of the line buffer, and registers 13-1 to 13 that latch data from the line buffer memories 12-1 to 12-5 using a synchronized clock Φ1.
-5 and a part that performs local window operations using that data. Note that the line buffer address control circuit 10 includes line buffer memories 12-1 to 12-1.
It controls the addresses necessary for accessing data from 2-5, and has a configuration as shown in FIG. 4, as will be described in detail later.

This causes the input data to become 1 in synchronization with the synchronous clock Φ0.
Line buffer address control circuit 1
0 to each line buffer memory I712-1 to 12-
The data from the previous stage is transmitted to line buffer It is possible to read the contents of the memories 12-1 to 12-5 and implement local window processing similar to the conventional case using the 5×5 local window calculation unit 14.

Next, the line buffer address control circuit 14 will be explained in detail.

As shown in FIG. 4, the line buffer address control circuit 14 includes a basic address counter 20, a width size storage register 21, a data selector 22, and a data inversion circuit 2.
3. Counter 24, data inversion circuit 25, OR circuit 26
．． 27 etc. The base address counter 20 generates the base address for writing sent data into the line buffer memory.

The width size storage register 21 is the target image to be processed (7)
41 width size. Data selector 2
2 is a 2t01 data selector that outputs data from either the basic address counter 20 or the width size storage register 21 according to the select signal "0" or "1"; for example, when the select signal is rOJ, the basic address - Outputs the count value of the counter 20, and when it is "1", outputs the width size set in the width size storage register 21. The data inversion circuit 23 is the data selector 2
This is to invert the ``1'' and ``0'' of the output data of 2. If the width size is r7FJ (hexadecimal code) is input, the ``1'' and ``0'' are inverted and r80J (16
decimal code). The counter 24 is set by the output of the data inverting circuit 23, and operates by +1 in response to the synchronous clock Φ1. The data inversion circuit 25 inverts the output data "1" and "0" of the counter 24.

Next, the operation of this line buffer address control circuit 14 will be explained with reference to FIGS. 3 and 5. Here, an example will be explained in which the image to be processed is 128x128, and the line buffer memories 2-1 to 12-5 each have a maximum of 65536 addresses. Therefore, "7F" indicating the width 128 of the image to be processed is set in the width size storage register 21.

The synchronous clock Φ0 is a clock that is synchronized with the input data, and the synchronous clock Φ0 stores the input data in the register 11 for input data launch.
The basic address counter 20 is incremented by 1. therefore,
As shown in FIG.
When the input data is input sequentially at "3", r 04 j is synchronized with the synchronization clock Φ0 from "03".
, "05", r06j-. This is then transmitted to the data selector 22.

By the way, the data selector 22 has a selection signal SEL of "0".
Since the data transmitted from the basic address counter 20 is output when the counter 24
The basic address output from the basic address counter 20 is output to the data inverting circuit 23 unless a carry "1" is output from the basic address counter 20 and this is applied as a selection signal.

As will be described later, when the counter 24 generates a carry "1", the data selector 22 outputs "7F" transmitted from the width size storage register 21, so the data inversion circuit 23 outputs "80".

On the other hand, the load signal ")" to the counter 24 is the OR circuit 2
LOAD by ORing the load signal LOAD applied to 6 and the carry CARRY output from the counter 24.
′ signal. Only when this LOAD'' signal is active rLOWJ, the counter 24 preloads the output of the data inversion circuit 23 in synchronization with the synchronization clock Φ1.

At other times, this counter 24 uses the synchronous clock Φ
It operates by +1 in synchronization with 1. And all F
Activates CARRY rHIGH when counting
Make it j.

In addition, the cycles of the simultaneous clock Φ1 are (a), (b), (tsu), (1), (o), (force) as shown in FIG.
, (g) constitute one cycle, and a reset signal RESET2 is output to the OR circuit 26 in response to the clock of (g).

Next, the operation of the present invention will be explained.

+1) As shown in FIG. 5, it is assumed that the width size storage register 21 is set to the width size "7F" and the basic address counter 20 is counting r03J (hexadecimal). At this time, the counter 24 is not outputting a carry, so the data selector 22 outputs "03" from the basic address counter 20 to the data inversion circuit 2.
3, and the data inverting circuit 23 outputs rF Cl as shown by ■ in FIG. 0Ar), the OR circuit 26 also simultaneously l,
Since the OAD° signal [5 is output and applied to the counter 24, the output rFCJ of the data inversion circuit 23 is loaded into the counter 24. Then, based on the synchronous clock Φ1 shown in (A) to (A) above being applied to the counter 24, the counter 24 increments by +1 and first outputs "FD", rFEJ, and "FFJ" as shown in FIG. death,
As a result, a carry "1" is output. This carry
1"1, the data selector 22 selects the width size storage register 2.
Since the data inversion circuit 23 outputs "7F" transmitted from 1, the data inversion circuit 23 outputs "80". By the way, the carry
1” is also transmitted to the OR circuit 26 and outputs the LOAD” signal “
Since 5 is output, the counter 24 is set to "80" next to the rFFJ, and henceforth "80" and "81".
will be output.

(2) When the synchronous clock Φ1 shown in (g) above is applied, the reset signal RESET2 is simultaneously applied to the OR circuit 27, so the counter 24 is reset to "00" and the carry is also "00". 0".

(3) As a result, from the data inversion circuit 25, the fifth
As shown in Figure ■ (line buffer memory addresses are "02", "01", "OO", "7F", "7E"
" is output, which causes registers 13-1 to 13-5 to
Since five pieces of data are output for each, the local window calculation unit 14 shown in FIG. 3 performs a predetermined calculation.

3 2 (4) The above (1) to (3) are confirmed based on the data input (“04”, “05” of the basic address counter 20).
” - is the line buffer memory address that is decremented five times while this base address changes by one.
03'' to r7F-1 and ``04'' to ``00'' are sequentially output, and based on these (local window calculations are performed).

By the way, by generating the write timing to the line buffer memory as shown in FIG.
-2, the data of the t register 13-2 to the line buffer memory 12-3, the data of the register 13-3 to the line buffer memory 12-4, the data of the register 13-4 to the line buffer memory 12-3. 5, respectively. After this, as the line buffer address changes, register 13-1 is
By launching 4 to ~13-5, the contents of the line buffer memory addresses sequentially incremented by -1 from the basic address can be propagated to the local window calculation unit 14.

Next, the reason why a width size storage register is provided in the present invention and selection must be made by a data selector will be explained with reference to FIG. If the current maximum address of the line buffer memory is "rFFFF" and the image size is smaller than that (for example, "7FJ"), in order to return from the left edge of the image to the right edge of the image at "007FJ," It is necessary to output the width size and set a counter.If this is not provided, as the base address is decremented, it will move to the maximum address of the line buffer memory, and the right edge of the image size Position IQ 07 You will not be able to return to the FJ position.With this configuration, the line buffer
Image processing with a size smaller than memory can be performed.

Note that although the above description has been made regarding an example in which the size of the local window is 5×5, the present invention is of course not limited to this.

〔Effect of the invention〕

According to the present invention, it is not only possible to perform local window processing on an image of any size, but also it is possible to reduce a local window calculation section having a size of nXn to a size of n.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of local window processing, Fig. 2 is a conventional local window calculation circuit, Fig. 3 is a schematic diagram of a local window data generation unit which is an embodiment of the present invention, and Fig. 4 is its line buffer.・Detailed diagrams of the address control circuit, and FIGS. 5 to 7 are diagrams explaining its operation. In the figure, 10 is a line buffer address control circuit, 11
are registers, 12-1 to 12-5 are line buffer memories, 13 to 1 to 13-5 are registers, 14 is a local window calculation unit, 20 is a basic address counter, 21 is a width size storage register, 22 is data・Selector, 2
3 is a data inversion circuit, 24 is a counter, 25 is a data inversion circuit, 26
．． 27 is an OR circuit. Patent applicant Fujitsu Ltd. agent Patent attorney Akira Yamatani 7 6

Claims (1)

[Claims] In a local window arithmetic processing device equipped with a line buffer, basic address counting means for generating a basic address for manipulating the address of the line buffer memory; width size storage means for storing the width size of two-dimensional data; Output selection means for selectively outputting the output of the basic address/counting means or width size storage means, and counting means for counting based on the output of the output selection means are provided, and the address of the line buffer memory is controlled by a pointer. A local window calculation control method characterized by the following.