JPH0531771B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an improvement of a pipelined information processing device, and more specifically to an information processing device that can perform update control of general-purpose registers with a small amount of hardware. It is related to.

[Conventional technology]

FIG. 3 is a block diagram of a conventional example, in which 1 is an instruction decoding section, 2-1 to 2-N are arithmetic unit sections,
3-1 to 3-N are pipeline operation units, 4 is an execution unit of each stage, and 5-1 to 5-N are pipeline operation units 3-1 to 3-N that finish executing instructions. , when outputting the calculation result, which is the execution result, to the signal lines 16-1 to 16-N, the signal line 15-1
~15-N outputs the storage destination address in the general-purpose register bank 10 for the above calculation result, and also outputs a signal for selecting the storage destination address and the calculation result to signal lines 14-1 to 14-N. Among the storage destination addresses added via the signal lines 15-1 to 15-N based on the signals applied via the signal lines 14-1 to 14-N from the output address holding circuits 5-1 to 5-N, A selector 7 selects one of these and adds it to the address register 8;
14-N from the pipeline calculation units 3-1 to 3-N based on the signal applied via the signal line 16-N.
A selector selects one of the operation results added through 1 to 16-N and adds it to the data register 9, and 10 is a general-purpose register bank. The types of operations each of the operation units 2-1 to 2-N are responsible for are determined, and the operation time is determined by the operation code of the instruction.

When the instruction decoding section 1 receives an instruction from an instruction processing unit (not shown), it first decodes which one of the arithmetic units 2-1 to 2-N should execute this instruction. With,
It decodes the execution time (number of machine cycles) of this instruction and the storage address of the instruction execution result, and then issues the instruction via the signal line 11 to the arithmetic unit section that executes this instruction, and also executes this instruction. The execution time of this instruction and the storage destination address of the execution result are added via signal lines 12 and 13 to the address holding circuit in the arithmetic unit section in which the instruction is executed.

FIG. 4 is a block diagram showing the configuration of the address holding circuit 5-1 provided inside the arithmetic unit section 2-1, in which 21 is a decoder, 22-1 to 22-
N is the register in which the validity bit is set, 23
-1~23-(N-1) is or gate, 24-1
~24-N are registers in which the storage address of the instruction execution result is set; 25-1~25-(N-
1) is a switching circuit, and 26-1 to 26-N are signal lines. In addition, registers 22-1 to 22-N, 24-
The number of stages 1 to 24-N must be the same as the number of machine cycles when executing the operation that takes the longest time among the operations that can be performed by the operation unit section 2-1. In addition, the switching circuits 25-1 to 25-2
5-(N-1) is the signal line 26-1 to 26-(N-
1), when the signal applied via the signal line 13 is “1”, the storage address of the execution result of the instruction applied via the signal line 13 is stored in the registers 24-1 to 24-(N-
In addition to 1), if it is “0”, registers 24-2~
The storage address set in 24-N is added to registers 24-1 to 24-(N-1). Further, the register 22-N is connected to the signal line 26-N.
When the signal applied via N becomes "1", the validity bit is set and the register 24-
When the signal N is applied via the signal line 26-N becomes "1", the storage address applied via the signal line 13 is set. In addition, the address holding circuits in other arithmetic units are also address holding circuits 5 except for the number of register stages.
-1 has the same configuration.

Now, for example, from the instruction processing unit section (not shown) to the instruction decoding section 1, the arithmetic unit section 2-
This is an instruction that should be executed in 1, and 3 is required to execute the instruction.
Assume that an instruction is added that requires a machine cycle and stores the execution result at address A of general-purpose register bank 10. When the instruction decoder 1 decodes the instruction, it applies the instruction to the arithmetic unit section 2-1 via the signal line 11, and sends the instruction to the decoder 21 in the address holding circuit 5-1 via the signal line 12 to execute the instruction. Data indicating time (3 machine cycles) is added, and the execution result storage address (address A) is added to the address holding circuit 5-1 via the signal line 13.

When data indicating i machine cycles (i is an integer from 1 to N) is added via the signal line 12, the decoder 21 changes only the signal line 26-i of the signal lines 26-1 to 26-N to "1". ”.
In this case, since data indicating three machine cycles is applied to the decoder 21 from the instruction decoding section 1 via the signal line 12, the decoder 21
will set the signal line 26-3 to "1". By setting the signal line 26-3 to "1", the register 22-3 is set to "1" via the OR gate 23-3, that is, the validity bit is set, and the register 24-3 is set to the switching circuit 25. -3, the storage address of the instruction execution result (in this case, address A) is set. Then, after one machine cycle has elapsed, the storage address set in register 24-3 is shifted to register 24-2 via switching circuit 25-2, and
The validity bit set in ORGATE 2
3-2 to the register 22-2. Thereafter, similarly, each time the machine cycle progresses, in other words, the storage address and validity bit are shifted downward in synchronization with the pipeline processing in the pipeline calculation section 3-1.
Therefore, at the timing when the instruction execution result is output from the arithmetic unit section 2-1, the validity bit is output from the register 22-1, and the storage destination address (address A) is output from the register 24-1. Become.

Selector 6 is address holding circuit 5-1 to 5-N
By adding a validity bit from the address holding circuit 5-i (i is an integer from 1 to N) through the signal line 14-i, the signal line 15-i is transferred from the address holding circuit 5-i to the signal line 15-i. The selector 7 adds the storage destination address added via the address register 8 to the address register 8, and the selector 7 transfers the storage address from the address holding circuit 5-i to the signal line 14.
By adding a validity bit via -i, the execution result of the instruction applied from the arithmetic unit section 2-i via the signal line 16-i is added to the data register 9. Therefore, in the above case, address A is set in the address register 8, and the arithmetic unit section 2-1 is set in the data register 9.
Therefore, the execution result of the instruction output from the arithmetic unit section 2-1 is set at address A of the general-purpose register bank 10.

Here, an instruction that requires an execution time of 3 machine cycles is issued from the instruction decoding section 1 to the arithmetic unit section 2-1, and after one machine cycle, the instruction is issued from the instruction decoding section 1 to the arithmetic unit section 2-1 for execution in 2 machine cycles. If an instruction that requires time is issued, register 2 in address holding circuit 5-1
2-2, 24-2 and the selectors 6, 7, the information such as the storage address of the two instructions collides with each other. In order to prevent such a collision, a path busy check circuit as shown in FIG. 5 is provided in the instruction decoding section 1. In the same figure, 31-1 to 31-N are registers, and 33-1 to 31-N are registers.
32-(N-1) is a switching circuit, 33-1 to 33-
N is a check circuit, and 34 is a signal line.

When issuing an instruction that requires i machine cycles (i is an integer from 1 to N) to execute the instruction, the instruction decoding section 1 checks whether or not a validity bit is set in the register 31-i using a check circuit 33-i.
Check by i. And register 31-
If the validity bit is set in i, the issuance of the instruction is delayed by one machine cycle; if it is not set, the validity bit is set in register 31-i and the instruction is issued. Note that the data set in each register 31-1 to 31-N is shifted downward each time the machine cycle progresses. Therefore, by doing as described above, it is possible to prevent a collision of instructions in the registers of the selectors 6 and 7 and the address holding circuit.

[Problem that the invention seeks to solve]

By the way, as mentioned above, the number of stages of registers in the address holding circuit that holds the storage address and validity bit until the end of instruction execution depends on the operations that can be performed by the arithmetic unit in which the address holding circuit is housed. It is necessary to set the number of machine cycles to be the same as the number of machine cycles when executing the operation that takes the longest calculation time. For example, if the longest calculation time of the calculations that can be performed by the calculation unit section is 10 machine cycles, the number of register stages required will be 10, and if the calculation time is 40 machine cycles, the number of register stages required will be 10.
Operations that require 40 stages and approximately 40 machine cycles include floating-point division and the like. As described above, in the conventional example described above, since the number of register stages in the address holding circuit increases in proportion to the calculation time, there is a problem that the amount of hardware increases.

The present invention solves the above-mentioned problems, and its purpose is to prevent the amount of metal from increasing even when executing instructions that require many machine cycles.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention provides a pipe in which the time from the start of execution of an instruction to the end of execution is determined by the operation code of the instruction to be executed, and which outputs the operation result as the execution result at the end of execution. The storage destination address for storing the operation result that is the execution result of each instruction executed by the line operation units 3-1 to 3-N and the pipeline operation units 3-1 to 3-N is It is retained until the end of execution, and is the storage destination address of the operation result that is the execution result output by the pipeline operation units 3-1 to 3-N at the end of execution of each instruction, and the storage destination address and the end of the execution. A plurality of arithmetic unit sections 2-1' to 2-1' each having address holding circuits 40-1 to 40-N that output a selection signal instructing selection of an arithmetic result that is an execution result of an instruction.
2-N', and the plurality of arithmetic unit sections 2-1' to 2-
The pipeline calculation units 3-1 to 3-N in N'
a first selector 7 that selects one of the calculation results output one by one from each of the calculation results from the selection signal; and the plurality of calculation unit sections 2-1' to 2-.
The address holding circuits 40-1 to 40- in N'
a second one for selecting one of the storage destination addresses outputted from N respectively by the selection signal;
a selector 6, and a general-purpose register for storing the operation results of the pipeline operation units 3-1 to 3-N selected by the first selector 7 in the storage address selected by the second selector 6. In the information processing device equipped with the bank 10, the address holding circuits 40-1 to 40-N are
Counters 41-1 to 41-M, 42-1 to 42-M, 42-1 to 42-M start counting down when the execution time of an instruction is set and the execution of the instruction is started.
M, 43-1 to 43-M, and registers 45-1 to 45-M in which the storage address of the instruction is set.
and each of the counters 41-1 to 41-M, 42-1.
- 42-M, 43-1 to 43-M, and corresponding counters 41-1 to 41-M, 42
Detection circuits 44-1 to 44- that generate the selection signal by detecting that the count values of -1 to 42-M and 43-1 to 43-M have reached a predetermined value.
M, and counters 41-1 to 41-M, 42-1 to 4 whose count values have reached the predetermined values based on the selection signals generated by the detection circuits 44-1 to 44-M.
2-M, 43-1 to 43-M, and a third selector 49 that outputs the storage address set in the registers 45-1 to 45-M paired with the second selector 6. have.

[Effect]

A counter provided in the address holding circuit is set to a value indicating the instruction execution time, and a countdown is started when the instruction execution starts. Therefore, the count value of the counter becomes a predetermined value at the end of execution of the instruction. The selection signal generation means is provided corresponding to each counter where a value indicating the instruction execution time is set, and when the count value of the counter reaches a predetermined value, that is, when the execution of the instruction is completed, the first selection signal generation means is provided. , generates a selection signal for the second selection means. Further, the third selection means selects the storage destination address set in the register paired with the counter whose count value has reached a predetermined value based on the selection signal generated by the selection signal generation means. Output to selection means. Therefore, the execution result of the instruction output from the pipeline operation section is stored at a predetermined address in the general-purpose register bank.

〔Example〕

FIG. 1 is a block diagram of an embodiment of the present invention.
1' is an instruction decoding section, 2-1' to 2-N' are arithmetic unit sections, 40-1 to 40-N are address holding circuits, and 60 is a signal line. represents the part.

When the instruction decoding section 1' receives an instruction from an instruction processing unit section (not shown), it decodes which one of the arithmetic unit sections 2-1' to 2-N' should execute this instruction. At the same time, the execution time (number of machine cycles) of the instruction is decoded based on the operation code of this instruction, and furthermore, the storage destination address of the execution result of the instruction is decoded. Next, the instruction decoding section 1' issues an instruction via the signal line 11 to the arithmetic unit section that executes this instruction, and issues the instruction via signal lines 12 and 13 to the address holding circuit in the arithmetic unit section that executes this instruction. Add the execution time of this instruction and the storage address of the execution result. Here, the execution time of the instruction transmitted via the signal line 12 is the execution time of the instruction transmitted via the signal line 12.
Pipeline calculation unit 3-1 in -1' to 2-N'
This is information about how many machine cycles it takes to execute an instruction in 3-N. Further, the storage destination address of the execution result transmitted via the signal line 13 is the storage destination address on the general-purpose register bank 10 of the execution result of each instruction decoded by the instruction decoding section 1'. At the same time, the instruction decoding section 1' notifies the arithmetic unit section which executes the instruction via the signal line 60 that the instruction has been issued.

FIG. 2 is a block diagram showing an example of the configuration of the address holding path 40-1 in the arithmetic unit section 2-1', in which 41-1 to 41-M are registers in which the instruction execution time is set, and 42- 1 to 42-M are switching circuits, 43-1 to 43-M are subtracters that perform a subtraction operation every machine cycle, and 44-1 to 44-M are set to 1 when the contents of registers 41-1 to 41-M are "1". Detection circuit for detecting that the state has become ``, 45-1 to 45-
46-1 to 46-M are registers in which validity bits are set; 47 is a control circuit;
8 is an OR gate, and 49 is a selector. In addition,
Registers 41-1 to 41-M and register 45-1
~45-M and registers 46-1 to 46-M are equal in number, and register 41-j and register 4
5-j and register 46-j (j is an integer from 1 to M) are combined into one set. Moreover, the switching circuits 42-1 to 42-M are control circuits 47
When the signal applied from the signal line 50-1 to 50-M is "1", the data indicating the execution time of the instruction applied via the signal line 12 is stored in the register 4.
In addition to 1-1 to 41-M, if it is "0", the outputs of subtracters 43-1 to 43-M are sent to registers 41-1 to 41-M.
This is in addition to 41-M. Therefore, register 41-j, switching circuit 42-j and subtractor 43-j
The execution time of the instruction is set by , and a counter that starts counting down is configured when the execution of the instruction is started. Further, address holding circuits 40-2 to 40 in other arithmetic unit sections
-M also has the same configuration as the address holding circuit 40-1.

Now, for example, from the instruction processing unit section (not shown) to the instruction decoding section 1', the arithmetic unit section 2
Assume that an instruction is added that is to be executed at -1', takes three machine cycles to execute, and stores the execution result of the instruction at address A of the general-purpose register bank 10. When the instruction decoding section 1' receives the above-mentioned instruction, it issues the instruction to the arithmetic unit section 2-1' via the signal line 11. At the same time, the instruction decoding section 1' is connected to the arithmetic unit section 2.
-1' address holding circuit 40-1 to signal line 2
The execution time of the instruction via (3 machine cycles)
, and add the storage address (address A) of the execution result of the instruction via the signal line 13.
It is notified via the signal line 60 that the command has been issued.

When the control circuit 47 in the address holding circuit 40-1 is notified via the signal line 60 that an instruction has been issued, it selects registers 46-1 to 46-M whose validity bits are not set. and registers 41-j and 4 that are paired with register 46-j whose validity bit is not set.
5-j sets the data indicating the calculation time for this instruction and the storage address. For example, if the validity bit is not set in the register 46-M, the control circuit 47 will set the signal line 50-M.
-1 to 50-M, only the signal line 50-M is set to "1", so that the register 41-M contains data indicating the execution time of the instruction applied via the signal line 12. A storage address applied via signal line 13 is set in register 45-M, and a validity bit is set in register 46-M.

When the instruction decoder 1' is ready to execute the issued instruction, it notifies the control circuit 47 via the signal line 60, and the control circuit 47 receives the data indicating the calculation time, the storage address, and the valid instruction. The bits are stored in registers 41-j, 45-j,
The signal line 50-j, which was set to "1" to set the signal to the signal line 46-j, is set to "0". When the signal line 50-j becomes "0", the output of the subtracter 43-j is applied to the register 41-j via the switching circuit 42-j, so that the value set in the register 41-j is changed in the machine cycle. It will be decremented by 1 each time it advances. Therefore, the value of the register 41-j becomes "1" at the timing when the execution of the instruction is completed.

Upon completion of instruction execution, register 4
When the value of 1-j becomes "1", the detection circuit 44-j
sets its output signal to "1". Detection circuit 44-
The output signal of j is applied to the selector 49 as a selection signal, and is also applied to the OR gate 48 and the signal line 14-1.
It is also added to selectors 6 and 7 via. Also,
Furthermore, the output signal of detection circuit 44-j is also applied to register 46-j as a reset signal. The selector 49 selects the storage destination address set in the register 45-j when the signal from the detection circuit 44-j becomes "1". Therefore, the output signal of the detection circuit 44-j becomes "1", the storage address set in the register 45-j is transferred to the selector 49 and the signal line 15.
It will be added to selector 6 via -1. In addition, as described above, when the signal applied via the signal line 14-i becomes "1," the selectors 6 and 7 receive the storage destination address and the signal line 16, which are applied via the signal line 15-i, respectively. -i
Since the execution result of the instruction added via The execution result of the instruction applied from section 2-1' via signal line 16-1 is set in data register 9. Therefore, the execution result of the instruction output from the arithmetic unit section 2-1' is set at address A of the general-purpose register bank 10.

Note that register 4 is used to set the instruction execution time.
1-j, a register 45-j in which the storage address is set, and a register 46-j in which the validity bit is set. determined by the number of subsequent instructions. Here, the number M of the above sets becomes maximum when N or more consecutive instructions that take the longest calculation time (instructions that require N machine cycles) are executed among the instructions that can be executed in the calculation unit. In this case, M=N, but generally speaking, among the instructions that can be executed in the same arithmetic unit section, a large number of instructions that require the longest computation time are consecutively executed. Since the address is never issued, the number of sets M is less than N, and the amount of hardware can be reduced compared to a conventional address holding circuit that requires N stages of registers. Furthermore, since a plurality of instructions are subjected to pipeline processing, it is necessary that the number of sets M is two or more. Although not explained in the above embodiment, the instruction decoding section 1' is provided with a path busy check circuit as shown in FIG. 5, as in the conventional example. The selectors 6 and 7 prevent information indicating the storage address of the above-mentioned instructions from colliding with each other.

〔Effect of the invention〕

As explained above, the present invention provides a counter (in the embodiment, a register 41-j, a switching circuit 42-j, and a subtracter 43-j) to which the execution time of an instruction is set.
) and registers such as register 45-j in which the storage address of the instruction is set, and when the count value of the counter reaches a predetermined value, Since the storage destination address set in the register paired with the counter whose value has reached a predetermined value is added to the general-purpose register bank as a write address, the address holding circuit requires less space than the conventional example. There is an advantage that the amount of metal can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram showing a configuration example of an address holding circuit according to the present invention, FIG. 3 is a block diagram of a conventional example, and FIG.
This figure is a block diagram showing an example of the configuration of a conventional address holding circuit, and FIG. 5 is a block diagram showing an example of the configuration of a path busy check circuit. In the figure, 1, 1'...instruction decoding section, 2
-1 to 2-N, 2-1' to 2 to N'... operation unit section, 3-1 to 3-N... pipeline operation section,
4...Execution part of each stage, 5-1 to 5-N',
40-1 to 40-N...address holding circuit, 6,
7, 49...Selector, 8...Address register, 9...Data register, 10...General-purpose register bank, 41-1 to 41-M, 45-1 to 4
5-M, 46-1 to 46-M...Register, 42
-1 to 42-M...Switching circuit, 43-1 to 43-
M...subtractor, 47...control circuit, 48...OR gate.

Claims (1)

[Scope of Claims] 1. A pipeline operation unit 3 whose time from the start of execution of an instruction to the end of execution is determined by the operation code of the instruction to be executed, and which outputs an operation result as an execution result at the end of execution of the instruction. -1~3-
N and a storage address for storing the operation result which is the execution result of each instruction executed by the pipeline operation units 3-1 to 3-N until the end of execution of each of the instructions. the storage destination address of the calculation result which is the execution result outputted by the pipeline calculation units 3-1 to 3-N at the end of execution, and the storage destination address and the calculation result which is the execution result of the instruction whose execution has been completed. Address holding circuits 40-1 to 40-1 that output selection signals instructing selection;
a plurality of arithmetic unit sections 2-1' to 2-N' each having a 40-N; and a plurality of arithmetic unit sections 2-1' to 2-N';
The pipeline calculation units 3-1 to 3-N in N'
a first selector 7 that selects one of the calculation results output one by one from each of the calculation results from the selection signal; and the plurality of calculation unit sections 2-1' to 2-.
The address holding circuits 40-1 to 40- in N'
a second one for selecting one of the storage destination addresses outputted from N respectively by the selection signal;
a selector 6, and a general-purpose register for storing the operation results of the pipeline operation units 3-1 to 3-N selected by the first selector 7 in the storage address selected by the second selector 6. In the information processing device equipped with the bank 10, the address holding circuits 40-1 to 40-N are
Counters 41-1 to 41-M, 42-1 to 42-M, 42-1 to 42-M start counting down when the execution time of an instruction is set and the execution of the instruction is started.
M, 43-1 to 43-M, and registers 45-1 to 45-M in which the storage address of the instruction is set.
and each of the counters 41-1 to 41-M, 42-1.
- 42-M, 43-1 to 43-M, and corresponding counters 41-1 to 41-M, 42
Detection circuits 44-1 to 44- that generate the selection signal by detecting that the count values of -1 to 42-M and 43-1 to 43-M have reached a predetermined value.
M, and counters 41-1 to 41-M, 42-1 to 4 whose count values have reached the predetermined values based on the selection signals generated by the detection circuits 44-1 to 44-M.
2-M, 43-1 to 43-M, and a third selector 49 that outputs the storage address set in the registers 45-1 to 45-M paired with the second selector 6. An information processing device comprising: