JP3196661B2 - Data transmission device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmitting apparatus, and more particularly to a data transmitting apparatus having a function of attaching a header to each frame of information data and transmitting the frame.

[0002]

2. Description of the Related Art In a data transmitting apparatus for attaching a header to information data and transmitting the information data to a communication line, a header is attached to each frame of the information data in a main memory for storing information data composed of a plurality of frames. Then, the corresponding header and information data frame are transferred as a unit to a continuous address area and transmitted again, or the information data is stored in each frame main memory, and the header is stored in another memory. (See, for example, Japanese Patent Application Laid-Open No. 62-98444). FIG. 3 shows the former of these conventional data transmission apparatuses as a first example, and FIG. 4 shows the latter as a second example.
Shown in

[0003] The data transmitting apparatus of the first example shown in FIG. 3 is configured such that each frame of information data (IDT) is stored at a predetermined address.
a, IDTb, etc.) and a header (HDa, IDb, etc.) corresponding to each frame of these information data are written, stored and read out, and a main memory 1x
A control unit 22x for controlling access to the data and a transmission FIFO memory 21 for storing a header and a frame of information data sequentially supplied and transmitting the frame to a communication line in accordance with a predetermined data format, The control unit 22x is started, and under the control of the DMA control unit 22x, the header and information data frames are sequentially read from consecutive addresses in the main memory 1x and transmitted to the sequential communication line supplied to the transmission FIFO memory 21. The communication controller 2x, a header corresponding to each frame of the information data is added and written and stored at a predetermined address of the main memory 1x, and each frame of the information data is transferred to a continuous address of the corresponding header, and the communication is performed. CPU 4x that outputs a data transmission request to controller 2x Has a configuration having a bus controller 3x for controlling the exchange of data performed via the system bus SB between the main memory 1x, communication controller 2x and CPU4x.

Next, the first operation will be described.

[0005] The information data to be transmitted is stored in the main memory 1x, and is divided and transmitted in frame units (IDTa, IDTb). These frames (IDTa, IDT
b) Since each of them needs to be transmitted with a header attached, the CPU 4x
After adding headers HDa and HDb to Ta and IDTb, respectively, and writing and transferring the corresponding header and information data frames in a predetermined address area of the main memory 1x so as to be stored at continuous addresses, the communication controller Send a data transmission request to 2x. At the time of this data transmission request, the header address of the header and the transmission data size which is the total size of the header and the corresponding frame are specified.

The communication controller 2x activates the internal DMA control unit 22x in response to the data transmission request, and transmits a header (eg, HDa) and a corresponding frame (IDT).
a) to output a read signal and an address signal for successively reading out a). In response, the header (HDa) is transmitted from the main memory 1x under the control of the bus controller 3x.
And the corresponding information data frame (IDTa) is read continuously, and the transmission FIF of the communication controller 2x is read.
The data is sequentially transferred to the O memory 21x. The transmission FIFO memory 21x sequentially sends the transferred data to the communication line according to the transmission data format.

The same operation is repeated for the next header (HDb) and the corresponding information data frame (IDTb), and the frames are sequentially transmitted to the communication line.

In the second example shown in FIG. 4, a main memory 71 for storing information data and a local memory 61 for storing a header are separately provided.
And the main processor 72 to form the station 7,
Local memory 61, DMA control unit 62, transmission FIF
The communication control board 6 includes an O memory 63, a local processor 64, a bus controller 65, and a local bus LB.
Is formed. The exchange of data between the station 7 and the communication control board 6 is performed via the system bus SB.

Next, the operation of the second example will be described.

In this second example, transmission of information data is performed under the control of local processor 64. When transmitting information data, first, a header corresponding to each frame of the information data is written in the local memory 61. After that, the DMA control unit 62 is started, and one header stored in the local memory 61 is read and transferred to the transmission FIFO memory 63. Subsequently, the DMA control unit 6
2, the corresponding frame of the information data stored in the main memory 71 is read and the FIFO memory for transmission 6
Transfer to 3. Then, the transmission FIFO memory 63 sequentially transmits the transferred data to the communication line according to the transmission data format.

[0011]

In the first example, the conventional data transmission apparatus described above uses the information data frames (IDTa, IDT) stored in the main memory 1x in the first example.
b) needs to be transferred again so that the header (HDa, HDb) added and written to another address area and the corresponding frame have a continuous address.
There is a problem that the load on the PU 4x becomes heavy and the use efficiency of the main memory 1x is low. In the second example, the information data is stored in the main memory 71, and the header thereof is stored in the local memory 61. One header is read from a predetermined address of the local memory 61 and transferred to the transmission FIFO memory 63, and then a corresponding frame of information data is read from a predetermined address of the main memory 71 and transferred to the transmission FIFO memory 63. This requires separate addressing and reading operations for each of the two memories (61, 71), so that there is a problem in that data transfer takes time and transmission efficiency deteriorates.

An object of the present invention is to provide a data transmission apparatus capable of reducing the load on a CPU, improving the use efficiency of a main memory, and shortening the data transfer time to improve the transmission efficiency. To provide.

[0013]

According to the present invention, there is provided a data transmitting apparatus comprising: a main memory for writing and storing information data consisting of a plurality of frames at predetermined addresses in frame units, and reading out these frames in accordance with a data read signal and an address signal; A header FIFO memory for sequentially writing and storing a header corresponding to each of the plurality of frames of the information data and sequentially reading the header in accordance with a header read signal; a header size register for storing the size of the header; A DMA controller for responding to output the header read signal for a period corresponding to the header size, the data read signal for a period corresponding to the frame size following the header read signal, and information on a start address; Header read from the FIFO memory for A communication controller including a transmission FIFO memory for sequentially writing and storing frames of information data read from the memory and sending the frames to a communication line; and outputting an address signal to the main memory in accordance with the data read signal and information on a head address. possess an address signal generating means for the data transmission request and the address
Is specified by one instruction and the readout signal is
And read the corresponding frame of the information data
In this configuration, the data is transferred to the transmission FIFO memory.

Further, the data transmitting apparatus of the present invention sets and stores a header size in a header size register, and sequentially writes and stores a header corresponding to each of a plurality of frames of information data in a header FIFO memory.
A CPU for outputting information of a start address of a frame of information data to be transmitted when a data transmission request is issued and information of a transmission data size including a total size of the header and the frame, and It can be configured in the controller,
Alternatively , the header readout signal and the data readout signal may be configured as a single signal having a first level during a period corresponding to the header size and a second level during a period corresponding to the frame size of the information data .

[0015]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

This embodiment uses a plurality of frame IDTs.
a, IDTb is written and stored at predetermined addresses in frame units, and the main memory 1 reads out these frames in accordance with the second level of the header data read signal and the address signal; and a plurality of frames of information data IDTa. , IDTb and corresponding header HD
a and HDb are sequentially written and stored, and a header FIFO memory 5 for sequentially reading these headers according to the first level of the header data read signal; a header size register 23 for storing the sizes of the headers HDa and HDb; , The first level of the period corresponding to the size of the headers HDa and HDb, and the frame IDT of the information data.
a, a header control unit 22 for sequentially outputting a header data read signal HDR at the second level for a period corresponding to the size of a and IDTb, and an address signal of a frame size from the head address of the frame of the information data to be read; A communication controller including a transmission FIFO memory for sequentially writing and storing a header read from the FIFO memory and a frame of information data read from the main memory and sequentially transmitting the frame to a communication line in accordance with a transmission data format; .Data read signal HDR
Read control of the header (eg, HDa) corresponding to a predetermined frame of information data from the header FIFO memory 5 in response to the first level, and the main memory 1 in response to the second level and the aforementioned address signal. Read control of a predetermined frame (IDTa) of information data from the FIFO memory 5 for header and the FIFO read from the main memory 1 and a transmission FIFO of a frame of information data
A bus controller 3 for controlling transfer to the memory 21 via a system bus SB;
3 setting of header size, storage control, FI for header
A CPU 4 for controlling the writing and storing of a header in the FO memory 5 and outputting a data transmission request including information on a start address of a frame of information data to be transmitted and information on a transmission data size of a total size of the header and the information data. Configuration.

Next, the operation of this embodiment will be described with reference to FIG.
The description will be made with reference to the timing waveform diagrams of the signals of the respective parts shown in FIG.

When sequentially transmitting the information data stored in the main memory 1 on a frame-by-frame basis, the CPU 4 first attaches a header to each of the frames IDTa and IDTb of the information data, and transfers this to the header FIFO memory 5.
And the header size register 23
The size of the header is set and stored.

Next, the CPU 4 issues a data transmission request to the communication controller 2. At this time, the CPU 4 determines the information of the head address of the frame IDTa of the information data to be transmitted,
And information of a transmission data size obtained by combining the size of the header with the size of the frame of the information data.

The communication controller 2 activates the DMA control unit 22 in response to the data transmission request, and the DMA control unit 22 sets the high level (first level) for the size of the header, the frame of the information data, Header data read signal HD that is at a low level (second level) for a period corresponding to the size
R is output, and address signals for the frame size are sequentially output from the start address of this frame. FIG. 2 shows an example in which the size of the header is 2 bytes and the size of the frame of the information data is 3 bytes or more.

The bus controller 3 responds to the high level of the header / data read signal HDR and responds to the high level of the header FIFO.
The header HDa of 2 bytes is sequentially read from the memory 5 and transferred to the transmission FIFO memory 21 for writing. Subsequently, the low level of the header / data read signal HDR and the address corresponding to the frame size from the head address of the frame IDTa of the information data. In response to the signal, frame IDTa of the information data is read from main memory 1 and transferred to transmission FIFO memory 21 for writing.

The transmission FIFO memory 21 sequentially transmits the transferred and written header and information data frames to the communication line in accordance with the transmission data format. The frame IDTb of the information data is similarly output.

In this embodiment, the header memory is F
Since it is an IFO memory and it is not necessary to specify the address for this memory, the corresponding frame of the header and information data is read out by one command (data transmission request, address specification) and one read signal, and the transmission FIFO is used.
The data can be transferred to the O memory 21, so that the time required for data transfer can be shortened and the transmission efficiency can be improved. Also,
Since it is not necessary to transfer information data in the main memory 1, the load on the CPU 4 can be reduced and the use efficiency of the main memory 1 can be increased.

In this embodiment, a signal for reading the header from the header FIFO memory 5 and the main memory 1
A header data read signal HDR is used as a signal for reading a frame of information data from the header data, and the header read and the data read are distinguished by the level difference. It can also be. The point is that a predetermined frame of the header and the information data can be continuously read by one data transmission request and one head address designation.

[0026]

As described above, according to the present invention, a header FIFO memory for sequentially storing headers corresponding to a plurality of frames of information data is provided, and a header is read from the header FIFO memory in response to a data transmission request. After reading, the corresponding frame of the information data is immediately read from the main memory. Therefore, the header and the corresponding frame of the information data are continuously read and transmitted by one data transmission request and one head address designation. FIFO
Since the data can be transferred to the memory, the data transfer time can be shortened and the transmission efficiency can be improved. In addition, since the operation of transferring information data in the main memory is eliminated, the load on the CPU can be reduced. There is an effect that the use efficiency of the main memory can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing waveform chart of signals of respective parts for explaining the operation of the embodiment shown in FIG. 1;

FIG. 3 is a block diagram showing a first example of a conventional data transmission device.

FIG. 4 is a block diagram showing a second example of a conventional data transmission device.

[Explanation of symbols]

 1, 1x main memory 2, 2x communication controller 3, 3x bus controller 4, 4x CPU 5 FIFO memory for header 6 communication control board 7 station 21 FIFO memory for transmission 22, 22x DMA controller 23 header size register 61 local memory 62 DMA control unit 63 FIFO memory for transmission 64 Local processor 65 Bus controller 71 Main memory 72 Main processor

Claims (3)

(57) [Claims] 1. A main memory for writing and storing information data consisting of a plurality of frames at predetermined addresses on a frame basis and reading these frames in accordance with a data read signal and an address signal, and a plurality of frames of the information data, respectively. Header FIF for sequentially writing and storing a header and sequentially reading the header according to a header read signal
O memory, a header size register for storing the size of the header, a header read signal for a period of the header size in response to a data transmission request, and a header for a period of the frame size following the header read signal. D for outputting the data read signal and the information of the head address
A communication controller including a MA control unit, a transmission FIFO memory for sequentially writing and storing a header read from the header FIFO memory and a frame of information data read from the main memory, and transmitting the frame to a communication line; possess an address signal generating means for outputting an address signal to said main memory in accordance with the information of the data read signal and the start address, the data transmission request and
The address is specified by one instruction and one read signal
And the corresponding frame of the information data in the header
A data transmission device for reading the data and transferring the data to the transmission FIFO memory . 2. A header size register sets and stores a header size, a header corresponding to each of a plurality of frames of information data is sequentially written and stored in a header FIFO memory, and is transmitted when a data transmission request is issued. A CPU for outputting information of a start address of a frame of information data to be transmitted and information of a transmission data size comprising a total size of the header and the frame, and an address signal generating means provided in the communication controller. A data transmission device as described in the above. 3. The header read signal and the data read signal are one signal having a first level during a period corresponding to a header size and a second level during a period corresponding to a frame size of information data. Data transmission device.