JP2002091823A - Memory controller to be used for image display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory controller with which a high speed memory such as SDRAM or DDR-SDRAM is controlled by a 16-bit central processing unit(CPU) or the like at high speed. SOLUTION: In the memory controller to be used for an image display device for displaying an image signal, this device is provided with a high speed memory 11 having a burst transfer function for continuously transferring the data of the image signal, a CPU 12 which does not have the burst transfer function, a buffer memory 13A which is connected between the high speed memory 11, and the CPU 12 for storing the transferred data of the image signal and performing the burst transfer of the stored data of the image signal to the high speed memory 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an SDRAM, a DD,
High-speed memory such as R-SDRAM is converted to 16-bit CPU
The present invention relates to a memory control that performs high-speed control by using a method such as the one described above.

[0002]

2. Description of the Related Art Recently, SDRAMs and DDR-SDRAMs have been developed.
Such high-speed memories are generally used, but these memories enable high-speed data transfer by executing burst transfer. Further, a high-end central processing unit (CPU) having a storage unit such as an HDD or an optical disk of 32 bits or more can be designed in consideration of burst transfer. It is possible to realize a simple system. However, it is not a conventional high-end CPU.
In the case of a CPU of about a bit, it is not possible to design a burst transfer in consideration of the normal transfer. Therefore, even if a high-speed memory is adopted, it is not possible to construct a high-performance system corresponding to the high-speed memory. I could not do it.

An example of a memory control device used in a conventional image display device will be described below with reference to FIG. FIG.
Examples of a memory control device used in the conventional image display device shown in FIG.
CPU (3) having a storage unit 32M such as an (optical disk)
2), a memory control circuit 33, and a video circuit (image display device) 35. The memory control circuit 33 has an input buffer memory 33B and an output buffer memory 33C.

A video input such as a moving image is input to a memory control circuit 3.
3 is supplied to the input buffer memory 33B and the SDRAM
(High-speed memory) 31 is supplied to an output buffer memory 33C via a (high-speed memory) 31, and is output to a video circuit (image display device) 35 for normal continuous reproduction of moving images. Next, a case in which the video is switched to the video circuit (image display device) 35 to output a still image of another image unrelated to the video will be described. In this case, a still image from the CPU (32) having the storage unit 32M such as an HDD (optical disk) is normally and individually transferred to the SDRAM (high-speed memory) 31 over time, and is accumulated. The still image signal is output to the video circuit (image display device) 35 via the output buffer memory 33C.

[0005] This still image is stored in an SDRAM (high-speed memory) 31.
Since it takes a considerable amount of time to normally transfer and accumulate the images, it is not possible to perform the performance utilizing the high-speed memory 31 such as switching and outputting the still images in sequence at a moderate timing. Switching between continuous playback of moving images and successively outputting different still images to the video circuit (image display device) 35 has a problem in that it is not possible to smoothly switch between still images. .

FIG. 6 shows a conventional non-high-end CPU 1
A timing chart at the time of normal transfer in the case of a CPU of about 6 bits is shown. In the case of normal transfer,
One write cycle requires four clock cycles (active (ACT), blank, write (WRT), and precharge (PRE)). As will be described later, in the case of burst transfer of an image signal (data), six clock cycles (in the case of four bursts) are required. If an attempt is made to transfer the same amount of data as that transferred by burst transfer using normal transfer, 16 clock cycles are required, resulting in time-consuming and very inefficient data transfer.

For an SDRAM of a high-speed memory, Vi
Requests for three types of access, i.e., video-in, CPU, and Video-out, occur. For each access request,
When the normal transfer is executed, the system becomes very inefficient.

Therefore, even in the case of a display device such as a projector using a CPU of about 16 bits instead of a high-end CPU, it is desired that all accesses to a high-speed memory (SDRAM) be performed by burst transfer.

[0009]

In a system (display device such as a projector) in which a high-end CPU cannot be used as described above, desired performance cannot be realized despite the use of a high-speed memory. That was the challenge.

In view of the above problems, the present invention is not a high-end CPU (central processing unit) of 32 bits or more.
By using a memory controller using a CPU of about a bit, a high-speed memory having a burst transfer function, and a buffer memory, an object is to realize a memory controller capable of constructing an image display device capable of high performance. And

[0011]

According to a first aspect of the present invention, there is provided a memory control device used for an image display device for displaying an image signal, wherein the data of the image signal is continuously transferred. And a central processing unit (CP) having no burst transfer function and having a storage unit 12M for the image signal.
U) 12, the high-speed memory 11 and the CPU (12)
And a buffer memory for storing data of the image signals individually transferred from the CPU (12), and burst-transferring the stored image signal data to the high-speed memory 11 collectively. 13A and a memory control device used in an image display device characterized by comprising:

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of a memory control device according to the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an image display device to which a memory control device used in the image display device of the present invention is applied.

One embodiment of a memory control device used in the image display device of the present invention shown in FIG. 1 is a CPU (storage function) 12M such as an SDRAM (high-speed memory) 11, an HDD or an optical disk. 12), a memory control circuit 13 and a video circuit (image display device) 15. An embodiment of the memory control circuit of the memory control device used in the image display device of the present invention shown in FIG.
B and an output buffer memory 13C.

The present invention, as shown in FIG.
D, CPU having storage unit 12M such as optical disk (12)
By providing a memory control circuit 13 having a buffer memory 13A between the high-speed memory 11 and the high-speed memory 11, high-speed data transfer can be realized.

First, a video input such as a moving image is supplied to an input buffer memo 13B of the memory control circuit 13, and the SDR
Output buffer memory 13 via AM (high-speed memory) 11
C and supplied to a video circuit (image display device) 15 for normal continuous reproduction of moving images.

Next, a case where it is desired to switch the normal continuous reproduction of a moving image so far and supply still images of other images to the video circuit (image display device) 15 one after another will be described with reference to FIG. In this case, still image data from a CPU (12) having a storage unit 12M such as an HDD (optical disk) is repeatedly stored in a buffer memory 13A, and data D0, D2, D3, D4 for one burst is 32 bits × (About 4 bursts), the stored image data is transferred to an SDRAM (high-speed memory) having a burst transfer function.
11 and are burst-transferred as shown in FIG. The transferred image signal data is stored in a video circuit (image display device) via an output buffer memory 13C.
15 is output.

The still image is transferred to an SDRAM (high-speed memory) 11
It does not take as long as conventional normal transfer to accumulate signal data by burst transfer in a batch, and still images are sequentially switched at a timing of a moderate speed and output to the video circuit (image display device) 15 one after another. It is possible to perform switching reproduction of each still image as smoothly as desired.

Hereinafter, each operation of the memory control device used in the image display device according to the embodiment of the present invention in the case of the write cycle and the read cycle will be described. A write cycle of one embodiment of the memory control device used in the image display device of the present invention will be described.
Since a 16-bit CPU (12) having a storage unit 12M such as an HDD or an optical disk does not support burst transfer of data, one bus cycle only transfers a maximum of 16 bits (2 bytes) of data. .

For this reason, the memory control circuit 13 of the present invention
Stores the address and data in the buffer memory 13A when the buffer memory 13A detects the write cycle from the CPU (12). The buffer memory 13A is a high-speed memory (S
A write cycle to the DRAM 11 is executed.
CPU (1) having a storage unit 12M such as a DD and an optical disc.
Buffer memory 13A repeatedly stored from 2)
Image data is burst-transferred to a high-speed memory 11 having a burst transfer function.

Here, since the burst transfer of data is not supported, the 16-bit CPU (12) has H
An embodiment of a method of supplying a video signal to the storage unit 12M such as a DD or an optical disk will be described. First, a high-speed memory is input to the video input as a still image via the input buffer 13B.
(SDRAM) 11.

The video signal of a still image stored in the high-speed memory (SDRAM) 11 is transferred to the buffer memory 13A by burst transfer. The video signal of the still image stored in the buffer memory 13A is transmitted to the buffer memory 13A.
CPU that does not support data and data burst transfer
Since the burst transfer cannot be performed between (12) and (12), the data is individually transferred to the storage unit 12M by the normal transfer and accumulated after a long time.

Next, a case of a read cycle of an embodiment of the memory control device used in the image display device of the present invention will be described. When the high-speed memory (SDRAM) 11 detects a read cycle from the CPU (12),
Starting from the address indicated by (12), the high-speed memory (SDRAM) 11 having the burst transfer function has 32 bits ×
Approximately (4 bursts) of image data is stored in the buffer memory 13A by burst transfer.

When the CPU (12) makes continuous access by this transfer, the second and subsequent data are read not from the high speed memory (SDRAM) 11 but from the buffer memory 13A.

When displaying a moving image on the screen, as shown in FIG. 3, a video input (Video in buf) (write cycle) to the input video buffer 13B (FIG. 1) and a video output buffer 13C (FIG. 1) ) Video output from
ut buf) cycle (read cycle) is alternately executed to reproduce a moving image on the screen. When characters are displayed on the screen, as shown in FIG. 4, a CPU access cycle from the CPU buffer memory (CPU buf) 13A (FIG. 1) is also inserted and executed, and the characters are reproduced on the screen. You.

Further, when a still image from a storage unit 12M such as an HDD or an optical disk of the CPU (12) is displayed on the screen, as shown in FIG. 4, a video output buffer 13C (FIG. 1) Video out from
A buf) cycle (read cycle) is executed by adding a CPUaccess cycle from the CPU buffer memory (CPU buf) 13A (FIG. 1), and a still image from the storage unit 12M is reproduced on the screen.

In the present invention, since data is temporarily stored in the buffer 13A inside the memory control circuit 13 and then transferred, as shown in FIG. 2, four times the data can be transferred in six clock cycles as compared with the conventional example. It is what becomes.

In the present invention, for example, a still image is converted to an SDRAM
(High-speed memory) It does not take as long as the conventional normal transfer to accumulate signal data by burst transfer in a batch at 11 and still images are sequentially switched at a timing of a moderate speed, and a video circuit (image display) Device), and can switch and reproduce each still image as smoothly as desired.

[0028]

As described above, the present invention relates to a high-speed memory having a burst transfer function for continuously transferring the image signal data in a memory control device used for an image display device for displaying an image signal. CPU without the burst transfer function and having a storage unit for the image signal
And connected between the high-speed memory and the CPU;
A buffer memory for accumulating the image signal data individually transferred from the CPU and collectively transferring the accumulated image signal data to the high-speed memory. Using a high-speed memory having a function and a CPU not having a burst transfer function of about 16 bits instead of a high-end CPU of 32 bits or more, a projector or the like capable of transferring data without deteriorating the performance of the high-speed memory A memory control device used for an image display device can be constructed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an image display device to which a memory control device of the present invention is applied.

FIG. 2 is a diagram showing a time chart of data transfer timing of a memory control device used in the image display device of the present invention.

FIG. 3 is a diagram showing one embodiment of a cycle (write cycle and read cycle) in the case of displaying a moving image of the memory control device used in the image display device of the present invention.

FIG. 4 is a diagram showing one embodiment of a cycle (read cycle) when a still image is displayed by the memory control device of the present invention.

FIG. 5 is a block diagram showing an example of an image display device to which a conventional memory control device is applied.

FIG. 6 is a diagram showing a time chart of data transfer timing of an example of a conventional memory control device.

[Explanation of symbols]

Reference Signs List 11 SDRAM (high-speed memory) 12 CPU having image signal storage unit (storage function)
(Central Processing Unit) 12M Image Signal Storage Unit (Image Signal Storage Function) 13 Memory Control Circuit 13A Buffer Memory 13B Input Buffer Memory 13C Output Buffer Memory 15 Video Circuit (Image Display Device)

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 5/00 G09G 5/00 555H 555T

Claims (1)

[Claims] 1. A memory control device used in an image display device for displaying an image signal, comprising: a high-speed memory having a burst transfer function for continuously transferring data of the image signal; A central processing unit (CPU) having an image signal storage unit, connected between the high-speed memory and the CPU, and storing the image signal data individually transferred from the CPU; A memory control device for use in an image display device, comprising: a buffer memory that collectively transfers burst data of the image signal to the high-speed memory.