JPH08166901A - Memory control circuit and facsimile equipment provided with the circuit - Google Patents

Abstract

PURPOSE: To easily and securely supply control signals corresponding to operated DMA controllers to a memory even if the plural DMA controllers different in operation speed and operation timing are used. CONSTITUTION: At the time of transferring picture data, CPU 1 gives an operation instruction to the respective DMA controllers 2 and 14 at prescribed timing. Then, the respective DMA controllers 2 and 14 DMA-transfer picture data between the picture memory 6 or a MODEM buffer 6 and a prescribed input/ output means designated from CPU 1 based on the instruction. When the operation instruction is executed, CPU 1 outputs data to which DMA controller 2 or 14 the operation instruction is executed to a memory control circuit 15 as a state display signal. Then, the memory control circuit 15 supplies the control signals for inputting/outputting data, which correspond to the operated DMA controllers 2 and 14, to the picture memory 6 and the like based on the state display signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention controls DM of data between a memory and a plurality of input / output means by controlling a plurality of DMA controllers having different operation speeds and operation timings.
The present invention relates to a memory control circuit that supplies a control signal for data input / output to a memory when A transfer is performed, and a facsimile apparatus including the memory control circuit.

[0002]

2. Description of the Related Art For example, in a facsimile machine,
In order to transfer image data efficiently between the image memory and various input / output devices in a short time, the transfer should be performed by DMA (Direct Memory Access) control instead of program control of the main control unit such as CPU. There is something I did. In this DMA control, the DMA controller forms a data transfer path (channel) independent of the main controller between the image memory and a predetermined input / output device.
The image data is directly transferred between the image memory and a predetermined input / output device. Usually, the DMA controller is configured to be able to perform transfer for a plurality of channels, and one channel can access one input / output device to the image memory.

By the way, in a facsimile machine,
An external device such as a personal computer, including a reading device for reading an image, a recording device for printing image data, and a CODEC for encoding / decoding image data as an input / output device for accessing the image memory. There are also many other input / output devices, such as an interface for transferring data between and. In such a facsimile device, D
It is necessary to provide many channels for MA transfer. However, since the number of channels that can be controlled by one DMA controller is limited, the required number of channels can be controlled by one DM.
If the A controller cannot cover the area, it is necessary to provide a plurality of DMA controllers.

[0004]

[Problems to be Solved by the Invention]
As the MA controller, it is not necessary to use those having the same operation speed and operation timing. That is, some input / output devices require transfer of image data at high speed, and some may transfer image data at relatively low speed. Therefore, it is not necessary to allocate a channel of a DMA controller having a high operation speed to all of these input / output devices, and in consideration of the manufacturing cost of the device, it is possible to transfer the image data at a high speed. It is desirable to allocate a high-speed DMA controller channel to a low-speed DMA controller channel when image data may be transferred at a relatively low speed.

However, when a plurality of DMA controllers having different operating speeds are used as described above, the control signals for image data input / output supplied to the image memory are also activated. It must be changed according to the DMA controller used. Therefore, there arises a problem that it is difficult to accurately control the input / output of the image data of the image memory.

The present invention has been made to solve the above problems, and an object thereof is to respond to a DMA controller to be operated even when a plurality of DMA controllers having different operation speeds and operation timings are used. It is an object of the present invention to provide a memory control circuit that can easily and surely supply a control signal to a memory and a facsimile apparatus including the memory control circuit.

[0007]

In order to achieve the above object, in the invention of claim 1, a plurality of DMs having different operation speeds and operation timings based on a command from a main control unit.
When data is DMA-transferred between the memory and each of the plurality of input / output means by the A controller, a data input / output corresponding to the operated DMA controller is performed based on the status display signal from the main control unit. The control signal is supplied to the memory.

According to the second aspect of the present invention, the memory is an image memory for storing image data, and the plurality of DMA controllers perform the DMA transfer of the image data between the image memory and the plurality of input / output means. It is something that can be made.

According to the third aspect of the present invention, at least the reading means for reading the image on the original and the recording means for printing on the recording paper based on the image data in the image memory are provided as the input / output means. The read image data is transferred to the memory and the image data is transferred from the image memory to the recording means by the DMA controller having the highest operation speed.

[0010]

Therefore, according to the first aspect of the present invention, the predetermined DMA controller is operated based on the command from the main control unit, and the data D is transferred between the memory and the predetermined input / output means.
MA transfer is performed. At this time, a control signal corresponding to the DMA controller to be operated is supplied to the memory based on the status display signal from the main control unit. Therefore, even when a plurality of DMA controllers having different operation speeds or operation timings are used, the control signal supplied to the memory is changed according to the operated DMA controller, and the data of the memory is changed. I / O control is performed accurately.

According to the second aspect of the present invention, even in the facsimile apparatus having a large number of input / output means, a plurality of D
The MA controller can efficiently transfer image data to and from the image memory in a short time.

According to the third aspect of the present invention, it is possible to perform the reading operation of the image on the original and the recording operation of the image data on the recording paper which require particularly high-speed processing at high speed.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is embodied in a facsimile machine will be described below with reference to the drawings. FIG. 1 shows the circuit configuration of this facsimile apparatus. A CPU (Central Processing Unit) 1 as a main control unit includes a ROM (Read Only Memory) storing a program for controlling the operation of the entire apparatus, and an RA for temporarily storing various information.
It is provided with M (random access memory). Further, the CPU 1 has a built-in DMA controller 2, and this DMA controller 2 enables data transfer for a plurality of channels (up to 4 channels in this embodiment). NCU (Network Control Unit) 3 controls connection with a telephone line. The modem 4 as an input / output means modulates and demodulates transmitted / received data.

A modem buffer 5 as a memory composed of SRAM (Static RAM) is for temporarily storing transmission / reception image data, and transfers image data to the modem 4 during transmission or from the modem 4 during reception. Temporarily stores the transferred image data. D
Image memory 6 composed of RAM (dynamic RAM)
Stores the image data in the encoded state. The scanner 7
Scan the image on the original. The reading side CODEC 8 encodes the image data read by the scanner 7 and outputs the encoded data to the image memory 6 via the bus bs.
In this embodiment, the scanner 7 and the reading side CODEC 8 constitute a reading unit as an input / output unit. The recording CODEC 9 decodes the image data transferred from the image memory 6 via the bus bs, and outputs the decoded data to the printer 10. The printer 10 as a recording unit prints on recording paper based on the decoded image data sent from the recording CODEC 9. In this embodiment, the printer 10 and the recording side CODEC 9 constitute a recording unit as an input / output unit.

Communication CODEC 11 as input / output means
Decodes the image data transferred from the image memory 6 at the time of transmission, re-encodes it and transfers it to the modem buffer 5, and decodes the received image data transferred from the modem buffer 5 at the time of reception and then re-encodes it. It is encoded and transferred to the image memory 6. That is, the encoding format of the image data stored in the image memory 6 of the own machine and the encoding format of the image data receivable by the partner device or the encoding format of the image data transmitted from the partner device Not necessarily the same. Therefore, with the CODEC 11 for communication,
At the time of transmission, the image data in the image memory 6 is changed again to a coding format that can be received by the partner device, and at the time of reception, the image data from the partner device is changed again to a coding format that can be stored in the image memory 6. I am trying.

A serial interface 12 such as RS232C as an input / output means is provided for exchanging image data as serial data with an external device (not shown) such as a personal computer. The connector 13 is for connecting an external device via a cable (not shown). Then, with the external device connected to the connector 13, the data in the image memory 6 is transferred to the external device via the serial interface 12, and the data transferred from the external device is transferred via the serial interface 12. Are stored in the image memory 6.

The external DMA controller 14 is provided independently of the DMA controller 2 built in the CPU 1 and can transfer data for a plurality of channels (up to 4 channels in this embodiment). . The memory control circuit 15 includes a CPU 1 and each DMA controller 1,
Based on the command from 14, the writing and reading of the image data to and from the image memory 6 and the modem buffer 5 are controlled.

In this embodiment, the CPU 1 is supplied with a 32 MHz clock signal as an operation clock. A 16 MHz clock signal is applied from the CPU 1 to the DMA controller 2 built in the CPU 1 as an operation clock, and the DMA controller 2 is operated at an operating speed based on the 16 MHz clock signal. Further, the external DMA controller 14 is supplied with a clock signal of 8 MHz from the CPU 1 as an operating clock, and the DMA controller 14 is operated at an operating speed based on the clock signal of 8 MHz. That is, in this embodiment, the DMA controller 2 built in the CPU 1 has a higher operation speed than the external DMA controller 14.

Further, in the present embodiment, the DMA controller 2 incorporated in the CPU 1 transfers image data from the reading side CODEC 8 to the image memory 6, transfers image data from the image memory 6 to the recording side CODEC 9, and sends and receives. DMA control of data transfer for three channels, that is, transfer of image data between the image memory 6 and the communication CODEC 11 is performed. The remaining one channel of the DMA controller 2 is an external DMA controller for transferring data for addressing the image memory 6 and the modem buffer 5 to the external DMA controller 14. Allocated for control of 14.

On the other hand, the external DMA controller 14
Is a modem buffer 5 and a COD for communication during transmission and reception.
DMA data transfer for three channels, that is, transfer of image data to and from the EC 11, transfer of image data between the modem buffer 5 and the modem 4, and transfer of image data between the image memory 6 and the serial interface 12. Control.
The external DMA controller 14 transfers the image data between the image memory 6 and the communication CODEC 11, and the DMA controller 2 built in the CPU 1 transfers the image data between the modem buffer 5 and the communication CODEC 11 using the DMA controller 2. It may be changed to control.

Then, the CPU 1 issues an operation command to each of the DMA controllers 2 and 14 at a predetermined timing when image data is transmitted and received with the start of a facsimile communication operation, for example. Then, based on that directive,
Each of the DMA controllers 2 and 14 causes a DMA transfer of image data between the image memory 6 or the modem buffer 5 and a predetermined input / output unit designated by the CPU 1.

Further, when the CPU 1 issues an operation command to each of the DMA controllers 2 and 14, it does not know which DMA
It outputs to the memory control circuit 15 as a status display signal whether or not an operation command has been issued to the controllers 2 and 14. Then, the memory control circuit 15 supplies the image memory 6 or the modem buffer 5 with a control signal for data input / output according to the operated DMA controllers 2 and 14 based on the state display signal.

That is, for example, data transfer between the image memory 6 and the external DMA controller 14 is performed by the DMA.
When controlled, image data is read / written to / from the image memory 6 at the speed and timing shown in the time chart of FIG. As shown in the figure, this read / write operation is performed with four cycles S1 to S4 of the 8 MHz clock signal as one cycle.

The external DMA controller 14 is a CP
The 8 MHz clock signal supplied from U1 is output to the memory control circuit 15, and a predetermined read / write signal R / D is output to the memory control path 15 and the image memory 6. The DMA controller 14 reads the read / write signal R at a timing slightly delayed from the fall of the second cycle S2 in one cycle of the 8 MHz clock signal.
/ D, and read / write signal R / at a timing slightly delayed from the fall of the fourth cycle S4.
Start up D. The CPU 1 also outputs the status display signal and the 16 MHz clock signal to the memory control circuit 15.

At this time, the memory control circuit 15 receives the state display signal and inputs the row address selection signal RAS and the column address selection signal CA as shown in FIG.
The S and address signal ADD are output to the image memory 6 as control signals. As shown in the figure, the memory control circuit 15 changes the L / H state of the input read / write signal R / D to the row address selection signal RAS at a timing slightly delayed from the fall of the 16 MHz clock signal. Output as. Further, the memory control circuit 15 outputs a signal obtained by delaying the rise and fall of the row address selection signal RAS for a predetermined time as a column address selection signal CAS. Further, the memory control circuit 15 switches the address signal ADD input from the DMA controller 14 to the row address based on the fall of the first cycle S1 in one cycle of the 8 MHz clock signal, and the fall of the third cycle S3. Based on the above, the address signal ADD is switched to the column address and output.

As a result, the image memory 6 fetches the row address and the column address of the address signal ADD based on the fall of the row and column address selection signals RAS and CAS, respectively. Then, the image memory 6 reads / writes the image data at the fetched address based on the read / write signal R / D.

Although not shown in the drawing, when data transfer to and from the modem buffer 5 is DMA controlled by the external DMA controller 14, reading / writing of image data to / from the modem buffer 5 is different from the above. Although it is a timing, in this case also, the timing is set to a predetermined timing by a method substantially similar to the above.

A DMA controller 2 with a built-in CPU 1
When the data transfer to and from the image memory 6 is DMA controlled by, the read / write of the image data to the image memory 6 is performed at the speed and timing shown in the time chart of FIG. As shown in the figure, this read / write operation is performed in four cycles T of the 16 MHz clock signal.
1 to T4 are performed as one cycle.

The DMA controller 2 receives the clock signal of 16 MHz given from the CPU 1 from the memory control circuit 1.
5 is output. Further, the CPU 1 controls the status display signal and the bus cycle start signal BCYST as shown in FIG.
Is output to the memory control circuit 15.

At this time, the memory control circuit 15 uses the row address selection signal RAS, the column address selection signal CAS, and the address signal ADD as shown in FIG. Output to. As shown in the figure, the memory control circuit 15 has a 16M
Second cycle T2 in one cycle of the Hz clock signal
At a timing slightly delayed from the falling edge of, the L level state of the input bus cycle start signal BCYST is output as the row address selection signal RAS, and the signal RAS is raised after two cycles of the clock signal. Further, the memory control circuit 15 outputs a signal obtained by delaying the rise and fall of the row address selection signal RAS for a predetermined time as a column address selection signal CAS. Further, the memory control circuit 15 switches the address signal ADD input from the DMA controller 2 to the row address based on the trailing edge of the first period T1 in one cycle of the 16 MHz clock signal, and the third
Based on the falling edge of the cycle T3, the address signal ADD is switched to the column address and output.

As a result, the image memory 6 fetches the row address and the column address of the address signal ADD based on the fall of the row and column address selection signals RAS and CAS, and the image is fetched at the fetched address, as described above. Read / write data.

Next, the operation of the facsimile apparatus configured as described above will be described. Now, for example, when the facsimile transmission operation is started, the image on the document is first read by the scanner 7, and the read image data is encoded by the reading side CODEC 8. Then, the encoded data is the DMA controller 2 with the built-in CPU 1.
Thus, the data is DMA-transferred to the image memory 6 via the bus bs and temporarily stored in the memory 6. After that, the image data in the image memory 6 is DMA-transferred to the communication CODEC 11 by the DMA controller 2 also incorporated in the CPU 1 to be decoded and re-encoded. continue,
The image data is transmitted by the external DMA controller 14
DMA transfer from the communication CODEC 11 to the modem buffer 5 and DMA transfer from the buffer 5 to the modem 4
After being transferred and modulated by the modem 4, it is transmitted to the partner device via the NCU 3 and the telephone line.

On the other hand, when the facsimile receiving operation is started, the image data transmitted from the partner device is N
It is received via the CU 3 and the modem 4, and demodulated by the modem 4. Then, the image data is transferred from the modem 4 to the modem buffer 5 by the external DMA controller 14.
MA is transferred and the communication CO is also sent from the buffer 5.
It is DMA-transferred to the DEC 11 and subjected to decoding and re-encoding processing. Then, the encoded image data is CP
It is DMA-transferred to the image memory 6 by the DMA controller 2 incorporated in the U1 and temporarily stored in the memory 6. After that, the image data in the image memory 6 is transferred to the recording side CODEC 9 by the DMA controller 2 also incorporated in the CPU 1.
The data is transferred to the MA and decrypted by the CODEC 9. Then, based on the decrypted data, the printer 10 prints on the recording paper.

When data communication is performed with an external device connected to the connector 13, an external DM is used.
By the A controller 14, the data in the image memory 6 is DMA-transferred to the serial interface 12 and then sent to the external device, and the data sent from the external device is DMA-transferred from the serial interface 12 to the image memory 6, It is stored in the memory 6.

As described above, DM of image data is exchanged between the image memory 6 or the modem buffer 5 and a predetermined input / output means.
When the A transfer is started, the CPU 1 issues an operation command to each of the DMA controllers 2 and 14 at a predetermined timing. Further, at this time, which of the DMA controllers 2 and 14 the operation command is issued to is output from the CPU 1 to the memory control circuit 15 as a status display signal. Then, based on the status display signal, the memory control circuit 15 recognizes which of the DMA controllers 2 and 14 is to be operated. A control signal as shown in (1) is supplied to the image memory 6 or the modem buffer 5.

As described above, in this embodiment, the operated DMA controllers 2 and 14 are accurately recognized based on the status display signal from the CPU 1, and the control signals corresponding to the operated DMA controllers 2 and 14 are generated. It can be easily and surely supplied to the image memory 6 and the modem buffer 5. Therefore, even when a plurality of DMA controllers 2 and 14 having different operation speeds and operation timings are used, the input / output control of the image data of the image memory 6 and the modem buffer 5 can be accurately performed.

Further, even if the facsimile apparatus is provided with a large number of input / output means as in this embodiment, a plurality of DMs are used.
By causing the A controllers 2 and 14 to perform the DMA transfer between the input / output means and the image memory 6 and the modem buffer 5, the image data can be transferred efficiently in a short time. Therefore, it is possible to realize a facsimile machine capable of high-speed processing.

Moreover, in the present embodiment, the reading side CODEC
8 from the image memory 6 to the image memory 6 and from the image memory 6 to the recording side CODEC 9 by the DMA controller 2 with a faster operating speed than the external DMA controller 14 I'm trying to get it done. Therefore, it is possible to perform the reading operation of the image on the original and the recording operation of the image data on the recording paper, which require particularly high-speed processing, at high speed.

The present invention is not limited to the above embodiment, but may be embodied with the following modifications. (1) Provide three or more DMA controllers.

(2) Which DMA controller 2, 14
What kind of DMA control is to be carried out in any other way than the mode of the above embodiment.

[0041]

As described in detail above, according to the first aspect of the invention, a plurality of Ds having different operation speeds and operation timings are used.
DM operated even when using MA controller
The control signal according to the A controller can be easily and surely supplied to the memory, and the excellent effect that the input / output control of the data of the memory can be accurately performed is exhibited.

According to the second aspect of the invention, even if the facsimile apparatus is provided with a large number of input / output means, a plurality of D
The MA controller can efficiently transfer image data to and from the image memory in a short time.

According to the third aspect of the present invention, it is possible to perform the reading operation of the image on the original and the recording operation of the image data on the recording paper which require particularly high-speed processing at high speed.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention.

FIG. 2 is a time chart showing a read / write operation of image data during DMA control of an external DMA controller.

FIG. 3 is a time chart showing a read / write operation of image data during DMA control of a DMA controller with a built-in CPU.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... CPU as main controller, 2 ... DMA controller, 4 ... Modem as input / output means, 5 ... Modem buffer as memory, 6 ... Image memory, 7 ... Scanner that constitutes reading means as input / output means, 8 ... a reading side CODEC constituting a reading means as an input / output means, 9 ... a recording side CODEC constituting a recording means as an input / output means,
DESCRIPTION OF SYMBOLS 10 ... Printer constituting recording means as input / output means, 11 ... Communication CODEC as input / output means, 12
... Serial interface as input / output means, 14
... DMA controller, 15 ... Memory control circuit.

Claims (3)

[Claims] 1. When a DMA transfer of data is performed between a memory and a plurality of input / output means by a plurality of DMA controllers having different operation speeds and operation timings based on a command from a main controller, A memory control circuit configured to supply a control signal for data input / output according to a DMA controller to be operated to a memory based on a status display signal from a control unit. 2. The memory is an image memory for storing image data, and the plurality of DMA controllers cause the image data to be DMA-transferred between the image memory and each of the plurality of input / output means. A facsimile apparatus including the memory control circuit according to item 1. 3. An input / output unit comprising at least a reading unit for reading an image on a document and a recording unit for printing on a recording paper based on image data in the image memory, and the reading image from the reading unit to the image memory. The facsimile apparatus according to claim 2, wherein the data transfer and the image data transfer from the image memory to the recording means are performed by a DMA controller having the highest operation speed.