JPH08305665A - Memory controller - Google Patents

Abstract

PURPOSE: To prevent the use efficiency of a bus or a memory from being degraded by refresh. CONSTITUTION: Bus masters 31 and 81 which control first and second bus systems 3 and 8 are provided with refresh means 34 and 84 which refresh a DRAM (shared memory 10). Signals indicating the operation states of refresh means 34 and 84 are supplied to a switch control circuit 12, and the control signal from the switch control circuit 12 is supplied to refresh means 34 and 84. When bus systems 3 and 8 are connected to the shared memory 10 through a bus switch 5 controlled by the switch control circuit 12, the shared memory 10 is refreshed by refresh means 34 and 84 of connected bus systems 3 and 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device suitable for use in, for example, a video printer device for making a hard copy of a video signal, a scanner device for capturing a still picture into a video device, and the like. .

[0002]

2. Description of the Related Art For example, in a video printer for making a hard copy of a video signal, the input video signal is written into a memory at the speed of the video signal (high speed), and the memory is read out at a speed (low speed) suitable for printing. It is possible to print by printing. In this case, this memory merely functions as a buffer and does not require any special configuration.

On the other hand, it is required that the video signal written in the above-mentioned memory be subjected to special effect processing such as color change, deformation, enlargement, reduction, rotation, mosaic, etc. before printing. There is. In that case, the video signal written in the above-mentioned memory may be read once, the above-mentioned special effect processing or the like may be performed, and the video signal subjected to the special effect processing may be written in the above-mentioned memory again. Be seen.

Further, it is required to read the video signal written in the above memory and display it on an arbitrary video monitor or the like. In this case, the video signal written in the memory is read at the speed (high speed) of the video signal and supplied to an arbitrary video monitor or the like.

On the other hand, when processing a special effect or the like on a video signal written in the above-mentioned memory, it takes time to process the special effect or the like. It is done relatively slowly. That is, the writing of the video signal to the memory described above and the reading of the video signal to an arbitrary video monitor or the like are performed at high speed, and the reading of the video signal written to the memory for processing such as special effects and printing is performed. Is slow.

Therefore, a circuit (first bus system) operated at high speed for writing a video signal to the above-mentioned memory and reading a video signal to an arbitrary video monitor and the like, and written to the above-mentioned memory. A circuit that operates at a low speed (second bus system) for performing processing such as special effects of a video signal and reading for performing printing is formed separately, and these are driven independently to achieve the optimum speed for each. It is conceivable to perform the operation with.

Further, for example, in a scanner device for capturing a still picture into a video device, a signal captured at a scanner speed (low speed) is written in a memory, and the memory is read out at a video signal speed (high speed) to obtain a video. It is output to a device or the like.

Therefore, also in this case, a circuit operated at a high speed (first bus system) for reading a video signal from the memory to the video device and a low speed for writing a signal captured by the scanner to the memory. It is conceivable that the circuit to be operated (second bus system) is formed separately, and these are independently driven to operate at their optimum speeds.

However, when such different bus systems use the same data, in the conventional configuration, each bus system must have a memory containing the same data. Therefore, the structure for providing these memories has become complicated and large-scale.

When data is transferred between different bus systems, the C that controls each bus system is used.
It is necessary for the PU and the like to synchronize with each other and for the CPUs to be directly involved in the data transfer. For this reason, depending on the bus system, there is a case where the other party is uselessly waited until the other party is ready.

On the other hand, the applicant of the present application has previously proposed a plurality of bus systems, a memory having an interface connectable to all of the plurality of bus systems, and a switching means for switching and connecting the memories to the plurality of bus systems. And a control means for controlling the switching timing of the switching means, and proposes a memory control device capable of arbitrarily changing the connection form between a plurality of bus systems and memories (Japanese Patent Application No. 31538/1994). did.

According to this, a plurality of bus systems can operate by sharing a single memory, and with a simple configuration, different bus systems can perform processing using the same data. It is possible to perform suitable memory control by using the above-mentioned video printer device or scanner device.

By the way, in the above-mentioned configuration, D is stored in the memory.
When the RAM is adopted, it is necessary to refresh the DRAM at a predetermined timing. In that case, in a device having a conventional bus system, a refresh means is provided in the bus system, and the refresh means performs the refresh operation.

However, in the device to which a plurality of bus systems are arbitrarily connected as described above, for example, if the refresh means is provided for only one bus system, the refresh is performed even when the bus system without the refresh means is connected. It is necessary to switch the connection to the bus system having the refresh means at the timing.

That is, in FIG. 4, in this example,
This is the case where the third bus system is provided, and the refresh means is provided in the second bus system. 4A shows a bus system that is performing processing. For example, after the first bus system first performs processing, the connection is switched and the third bus system performs processing. .

On the other hand, as shown in B of FIG. 4, the actual connection of the switching means is the second when the refresh timing (C in the same figure) is reached during the processing of the first and third bus systems. The bus system is switched to another bus system, and after refreshing, the bus system is switched back to the original first or third bus system.

Therefore, in the above-mentioned configuration, since the connection is frequently switched, the utilization efficiency of the bus and the memory is lowered, and the processing speed and the processing performance may be lowered.

[0018]

This application has been made in view of such a point, and the problem to be solved is that the connection is frequently switched in the conventional configuration. The use efficiency of the bus and the memory is reduced, and the processing speed and the processing performance may be reduced.

[0019]

Therefore, in the present invention, the plurality of bus systems are respectively provided with refreshing means, and the refreshing means of any bus system is used to refresh the memory. .

[0020]

According to this, even if the refresh timing comes during the processing of the bus system, it is not necessary to switch the connection, and the switching does not reduce the utilization efficiency of the bus and the memory. It is possible to eliminate the risk of deterioration of the processing performance.

[0021]

More specifically, in the present invention, a plurality of bus systems, a memory having an interface capable of connecting to all of the plurality of bus systems, a switching means for switching and connecting this memory to each of the plurality of bus systems, and this switching are provided. A plurality of bus systems, each of which is provided with a refreshing means corresponding to a memory, and the control means has an arbitrary connection form between the plurality of bus systems and the memory. In addition, the memory can be refreshed by using any bus system refreshing means.

The present invention will be described below with reference to the drawings. In FIG. 1, the memory control device according to the present invention is used, for example, in a video printer device to process a special effect or the like on an input video signal. The structure of the embodiment in the case of performing and printing is shown.

In FIG. 1, a terminal 1 is an input terminal to which a digital video signal is supplied, for example. The input terminal 1 is connected to the data / address bus 2. The data / address bus 2 is a first for writing and reading a video signal to and from a shared memory 10 described later at high speed.
Is a data / address bus constituting the bus system 3 of FIG. The data / address bus 2 has a bus master (CPU) 31 for controlling the first bus system 3 and an RA.
The M32 and the ROM 33 are connected. Also this data /
The address bus 2 is connected to an arbitrary video monitor 4 such as a digital input.

The data / address bus 2 is connected to the first fixed contact 5A of the bus switch 5. Furthermore, from the bus master 31 that controls the first bus system 3,
Chip select (CS), read enable (RD),
Write enable (WR: not required if the memory is a ROM), and its control signal (RA
S, CAS), a control bus (shown by a broken line) such as a signal (enable) indicating an available state of the shared memory 10 which will be described later, is connected to the RAM 32 and the ROM 33, and the first second fixed contact of the bus switch 5 is connected. 5a.

Further, the device 6 is a user's key input device. The key input device 6 is connected to the data / address bus 7. This data / address bus 7 is a second bus system 8 for processing special effects of video signals.
Is a data / address bus that configures. The data / address bus 7 has a bus master (CPU) 81 that controls the second bus system 8, a RAM 82, and a ROM.
83 is connected. The data / address bus 7 is also connected to a print head block 9 for printing.

The data / address bus 7 is also connected to the second fixed contact 5B of the bus switch 5. Furthermore, from the bus master 81 that controls the second bus system 8,
Chip select (CS), read enable (RD),
Write enable (WR: not required if the memory is a ROM), and its control signal (RA
S, CAS), a control bus (shown by a broken line) such as a signal (enable) indicating an available state of the shared memory 10 described later, is connected to the RAM 82 and the ROM 83, and the second fixed contact of the bus switch 5 is connected. 5b is connected.

The 1 movable contact 5X and the 2 movable contact 5x of the bus switch 5 are connected to the data / data of the shared memory 10.
Connected to address bus and control bus. The shared memory 10 has an interface that can be connected to both the first and second bus systems 3 and 8 described above.

Further, the circuit 11 is a synchronization generating circuit.
The sync generation circuit 11 is driven in synchronization with a sync signal of a video signal supplied to the free-running or input terminal 1.
Then, the signal from the synchronization generation circuit 11 is used as a bus master 31, 81 for controlling the first and second bus systems 3, 8.
Is supplied to.

Further, the signal from the synchronization generating circuit 11 is supplied to the switch control circuit 12 and, for example, during the horizontal blanking period of the video signal which is written in and read out from the shared memory 10 at high speed, the bus switch 5 operates. Movable contacts 5X, 5x from the first fixed contacts 5A, 5a,
It is switched to the second fixed contacts 5B and 5b.

Therefore, in this apparatus, when the video signal is written from the input terminal 1 to the shared memory 10, the synchronization generating circuit 11 is driven in synchronization with the synchronization signal of the video signal supplied to the input terminal 1 to generate this synchronization. According to the signal from the circuit 11, the video signal is written to the shared memory 10 through the first bus system 3.

Further, when the video signal is read from the shared memory 10 to the arbitrary video monitor 4, the synchronization generating circuit 11 is driven by free running, and according to the signal from the synchronization generating circuit 11, the arbitrary operation is performed through the first bus system 3. The video signal is read out to the video monitor 4.

Then, the bus switch 5 is switched to the second fixed contacts 5B and 5b during, for example, a horizontal blanking period while high-speed writing and reading are performed on the shared memory 10. As a result, during this period, the shared memory 10 is under the control of the second bus system 8 and data can be transferred between the shared memory 10 and the second bus system 8.

That is, during this period, the program control method directly performed by the bus master 81 which controls the second bus system 8 and so-called direct memory access (DM
Data can be transferred by the block transfer according to A). Then, using the transferred data, processing such as special effects of the video signal written in the shared memory 10 and printing are performed.

Therefore, according to this device, the shared memory 1 having a plurality of bus systems 3 and 8 and an interface capable of connecting to all of these plurality of bus systems 3 and 8 is provided.
0 and this shared memory 10 are connected to a plurality of bus systems 3,
8 is composed of a bus switch 5 for switching connection and a switch control circuit 12 for controlling the switching timing of the bus switch 5, and the connection form between the plurality of bus systems 3, 8 and the shared memory 10 can be arbitrarily changed. By doing so, a plurality of bus systems can operate by sharing a single memory, and with a simple configuration, different bus systems can perform processing using the same data. .

That is, in this device, when the same data is used in a plurality of independent bus systems, it is not necessary for all the bus systems to have a memory for storing data, and the data storage unit is provided in one place. , It is possible to reduce the number of memories for storing data. Also, by performing maintenance on one place, it is possible to reliably reflect it on all bus systems.

Further, the data transfer can be performed asynchronously. For this reason, it is not necessary to wait for permission of the transfer partner at the time of transfer, so that there is no waste of time. Further, even when the transfer is performed by interruption, the processing in the own bus system is not interrupted by the transfer of the data from the other. Therefore, the processing in each bus system can be smoothly performed, and the processing efficiency can be improved.

In such a memory control device, according to the present invention, the shared memory 1 is provided to the bus masters 31 and 81 which control the first and second bus systems 3 and 8, for example.
When 0 is a DRAM, refresh means 34 and 84 for refreshing the DRAM are provided. Further, a signal indicating the operating state of the refresh means 34, 84 is supplied to the switch control circuit 12, and a control signal from the switch control circuit 12 is supplied to each refresh means 34, 84.

The refreshing means 34 and 84 are
When the bus masters 31 and 81 are, for example, the above-mentioned CPU devices, they are provided, for example, as part of the software of the CPU. Alternatively, when the bus masters 31 and 81 are DRAM control devices, the refresh means 34 and 84 are, for example, existing refresh circuits in the control devices. When the bus masters 31 and 81 are gate array devices, the refreshing means 34 and 84 are formed, for example, in a part of the gate array.

In this device, basically, the bus systems 3 and 8 connected via the bus switch 5 are connected.
Shared memory 1 by the refresh means 34, 84 of
A 0 refresh is performed.

That is, in FIG. 2, as in the case of FIG. 4 described above, this example is a case where the first to third bus systems are included. 2A shows a bus system that is performing processing. For example, after the first bus system first performs processing, the connection is switched and the third bus system performs processing. .

In this case, as shown in FIG. 2B, even if the refresh timing comes during the processing of the first and third bus systems, this refresh is performed for the first and third bus systems. It does not need to switch the bus system for refresh. The difference in the refresh period length between the first and third bus systems is due to the difference in the specifications of the refresh means.

Therefore, in this device, in the conventional configuration, since the connection is frequently switched, the utilization efficiency of the bus and the memory is lowered, and the processing speed and the processing performance may be lowered. By providing refreshing means for each of a plurality of bus systems and refreshing the memory by using the refreshing means of an arbitrary bus system, the connection is switched even at the refresh timing during the processing of the bus system. There is no need to do so, the efficiency of use of the bus and memory is not reduced by switching, and there is no fear of a reduction in processing speed or processing performance.

In the above-mentioned device, if the bus system is switched during the execution of refresh, the refresh being executed may not be completed, which may cause inconvenience. Therefore, in the above device, the refreshing means 34, 8
The signal indicating the operation state of No. 4 is supplied to the switch control circuit 12 so that the refresh priority control is performed so that the bus system is not switched during the refresh execution.

The above-mentioned device is particularly effective when the bus system is switched in a relatively long cycle. However, if the bus system is switched in a short cycle, it may not be possible to satisfy the refresh specification of the DRAM configuring the shared memory 10 during the cycle in which the bus system is connected, depending on the specifications of the refresh means provided. Sexuality occurs.

That is, for example, when the bus master of each bus system is formed of various devices as described above, the specifications of the refresh means provided therein may be different. In that case, if the specification of the refresh means takes a relatively long time, the refresh may not be completed during the period when the bus system is connected. In that case, the period during which the bus system is connected only for refreshing is extended. Therefore, the utilization efficiency of the bus and the memory is reduced, and the processing speed and the processing performance may be reduced.

Therefore, in such a case, for example, as shown in FIG. 3, the bus system for refreshing can be fixed so that the DRAM refreshing specifications are always satisfied. That is, in FIG. 3, when the first to third bus systems are switched in a short cycle and processing is performed, as shown in A of FIG. 3, for example, refresh execution is performed to refresh the second bus system. Fixed to the means.

As a result, at the refresh timing shown in C of the same figure, as shown in B of the same figure, when the second bus system is connected, the refresh is performed as it is, and the first and third buses are connected. During the processing of the system, the second bus system is switched to refresh.

Therefore, by fixing the execution of the refresh to the second bus system by making the specifications of the refresh means provided in the second bus system such that the processing is completed in a short time, for example, It is possible to improve the use efficiency of the bus and the memory, and eliminate the fear of a reduction in processing speed and a reduction in processing performance.

That is, in the above-mentioned device, when the bus system switching is performed in a relatively long cycle, the shared memory is refreshed by the refresh means of each bus system as shown in FIG. If the switching is performed in a short cycle,
By fixing the execution of refreshing to the refreshing means of an arbitrary bus system as shown in, it is possible to always perform efficient memory control.

For such switching control, a CPU or the like is provided in the switch control circuit 12, and the contents of the control are arbitrarily set in accordance with the respective circumstances etc., so that the most efficient memory control is always achieved. Can be done.

Further, in the above-mentioned device, when the DRAM provided as the shared memory corresponds to the sleep mode, at least one of the refresh means provided in each bus system is constituted by the means corresponding to the sleep mode. . When the entire device is in the stopped state, the shared memory is connected to the bus system provided with the refresh means corresponding to the sleep mode.

As a result, for example, in a device driven by a built-in battery, the power consumption can be greatly reduced and the life of the built-in battery can be extended.

Thus, according to the above memory control device,
A plurality of bus systems, a memory having an interface capable of connecting to all of the plurality of bus systems, a switching means for switching and connecting this memory to each of the plurality of bus systems, and a control means for controlling the switching timing of the switching means. A plurality of bus systems are respectively provided with refresh means corresponding to the memories, and the control means can arbitrarily change the connection form between the plurality of bus systems and the memory, and By refreshing the memory using the refreshing means, it is not necessary to switch the connection even when the refresh timing comes during the processing of the bus system, and the switching may reduce the utilization efficiency of the bus and the memory. Eliminates the risk of reduced processing speed and processing performance. It is what it is.

The present invention is not limited to the memory control device used in the above video printer device or scanner device, but can be generally applied to the case where different bus systems use the same data. It is possible.

[0055]

According to the present invention, refreshing means is provided for each of a plurality of bus systems, and the refreshing means of an arbitrary bus system is used to refresh the memory. Even if it becomes, it is no longer necessary to switch the connection, the usage efficiency of the bus and memory will not be reduced due to the switching, and it is possible to eliminate the possibility of lowering processing speed and processing performance. .

[Brief description of drawings]

FIG. 1 is a configuration diagram of an example in which a memory control device according to the present invention is applied to a video printer device.

FIG. 2 is a diagram for explaining the operation.

FIG. 3 is a diagram for explaining the operation.

FIG. 4 is a diagram for explaining the operation of a conventional device.

[Explanation of symbols]

 1 Digital Video Signal Input Terminal 2 Data / Address Bus 3 First Bus System 31 Bus Master 32 RAM 33 ROM 34 Refreshing Means 4 Digital Input Video Monitor 5 Bus Switch 6 Key Input Device 7 Data / Address Bus 8 Second Bus system 81 Bus master 82 RAM 83 ROM 84 Refreshing means 9 Print head block 10 Shared memory 11 Synchronization generation circuit 12 Switch control circuit

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Tadashi Morishige 6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation (72) Kazumasa Miyazaki 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo No. Sony Corporation (72) Inventor Toshiyuki Iijima 6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation

Claims (4)

[Claims] 1. A plurality of bus systems, a memory having an interface capable of connecting to all of the plurality of bus systems, a switching means for switching and connecting the memories to the plurality of bus systems, and a switching of the switching means. Control means for controlling the timing of each of the plurality of bus systems, and each of the plurality of bus systems is provided with a refresh means corresponding to the memory, and the control means includes a connection form between the plurality of bus systems and the memory. And a memory control device for refreshing the memory by using any refreshing means of the bus system. 2. The memory control device according to claim 1, wherein the control means does not switch the switching means while refresh is being executed by any refresh means of the bus system. Memory controller. 3. The memory control device according to claim 1, wherein when the switching of the plurality of bus systems is performed in a short cycle, the control means performs refresh by a refresh means of a specific bus system. Memory control device. 4. The memory control device according to claim 1, wherein when the memory has a sleep mode, the control means has a refresh means corresponding to the sleep mode during an operation suspension period. A memory control device adapted to switch to the bus system.