JPH07239823A - Memory controller - Google Patents

Abstract

PURPOSE:To execute the processing at different bus systems while using the same data. CONSTITUTION:A data/address bus 2, to which a master CPU 31 for controlling a first bus system 3 is connected, is connected to a fixed contact 5A of a bus switch 5 and a control bus from the master CPU 31 is connected to a fixed contact 5a. A data address bus 7, to which a master CPU 81 for controlling a second bus system 8 is connected, is connected to a fixed contact 5B of the bus switch 5 and a control bus from the master CPU 81 is connected to a fixed contact 5b. Then, a movable contact 5X and a movable contact 5x are connected to the data/address bus and control bus of a shared memory 10. Further, a signal from a synchronism generating circuit 11 is supplied to a switch control circuit 12, and the movable contacts 5X and 5x of the bus switch 5 are changed over at a prescribed timing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device suitable for use in, for example, a video printer device when a special effect process or the like is applied to an input video signal for printing.

[0002]

2. Description of the Related Art For example, in a video printer, it is considered that an input video signal is written in a memory at a speed (high speed) of the video signal, the memory is read out at a speed (low speed) suitable for printing, and printing is performed. . In this case, this memory merely functions as a buffer and does not require any special configuration.

On the other hand, it is required that the video signal written in the above-mentioned memory be subjected to special effect processing such as color change, deformation, enlargement, reduction, rotation, mosaic, etc. before printing. There is. In that case, the video signal written in the above-mentioned memory may be read once, the above-mentioned special effect processing or the like may be performed, and the video signal subjected to the special effect processing may be written in the above-mentioned memory again. Be seen.

Further, it is required to read the video signal written in the above memory and display it on an arbitrary video monitor or the like. In this case, the video signal written in the memory is read at the speed (high speed) of the video signal and supplied to an arbitrary video monitor or the like.

On the other hand, when processing a special effect or the like on a video signal written in the above-mentioned memory, it takes time to process the special effect or the like. It is done relatively slowly. That is, the writing of the video signal to the memory described above and the reading of the video signal to an arbitrary video monitor or the like are performed at high speed, and the reading of the video signal written to the memory for processing such as special effects and printing is performed. Is slow.

Therefore, a circuit (first bus system) operated at high speed for writing a video signal to the above-mentioned memory and reading a video signal to an arbitrary video monitor and the like, and written to the above-mentioned memory. A circuit that operates at a low speed (second bus system) for performing processing such as special effects of a video signal and reading for performing printing is formed separately, and these are driven independently to achieve the optimum speed for each. It is conceivable to perform the operation with.

However, when such different bus systems use the same data, in the conventional configuration, each bus system must have a memory containing the same data. Therefore, the structure for providing these memories becomes complicated and large-scale.

Further, when data is transferred between different bus systems, C which controls each bus system is used.
It is necessary for the PUs to be synchronized and for the CPUs to be directly involved in the data transfer. Therefore, depending on the bus system,
In some cases, they had to wait unnecessarily until the other party was ready.

[0009]

The problem to be solved by the present invention is that, in the conventional configuration, when a plurality of bus systems use the same data, a memory containing the same data is provided in each bus system. , Each must have, which complicates the configuration. Further, when data is transferred between different bus systems, special operations and circuit configurations are required, such as synchronization of CPUs that control the respective bus systems.

[0010]

A first means according to the present invention is to provide a plurality of bus systems 3 and 8, a memory 10 having an interface connectable to all of the plurality of bus systems, and a plurality of the memories each including the plurality of bus systems. Switching means (bus switch 5) for switching connection to the above bus system,
A memory control device comprising control means (switch control circuit 12) for controlling the switching timing of the switching means, and capable of arbitrarily changing the connection form between the plurality of bus systems and the memory.

According to a second aspect of the present invention, in the memory control device according to the first aspect, the control means is controlled based on a synchronizing signal of a signal written in the memory. Is.

A third means according to the present invention is the memory control device according to the first means, wherein the control means is controlled based on selection signals from the plurality of bus systems. Is.

A fourth means according to the present invention is the memory control device according to the first means, wherein the control means is controlled based on a control signal from the outside.

According to a fifth aspect of the present invention, in the memory control device according to the first aspect, a video signal is written in the memory through the first bus system of the plurality of bus systems, and at least the video signal is written. The memory control device is configured such that the memory is read through a second bus system of the plurality of bus systems during a horizontal blanking period of a signal.

[0015]

According to this, a plurality of bus systems, a memory having an interface capable of connecting to all of the plurality of bus systems, a switching means for switching and connecting the memory to each of the plurality of bus systems, and a switching means of the switching means. Consisting of control means for controlling the switching timing,
By making it possible to arbitrarily change the connection form between multiple bus systems and memory, multiple bus systems can operate by sharing a single memory, and with a simple configuration, different bus systems can be used. Processing using the same data can be performed.

[0016]

FIG. 1 shows the configuration of an embodiment in which the memory control device according to the present invention is used, for example, in a video printer device to perform processing such as special effects on an input video signal for printing. .

In FIG. 1, reference numeral 1 is an input terminal to which, for example, a digital video signal is supplied, and the input terminal 1 is connected to a data / address bus 2. The data / address bus 2 is a data / address bus which constitutes a first bus system 3 for writing and reading a video signal to and from a shared memory 10, which will be described later, at high speed. A master CPU 31, a RAM 32, and a ROM 33, which control the first bus system 3, are connected to the data / address bus 2. Further, the data / address bus 2 is connected to a video monitor 4 having an arbitrary digital input, for example.

The data / address bus 2 is connected to the first fixed contact 5A of the bus switch 5. Further, the chip select (CS) and the read enable (R) from the master CPU 31 that controls the first bus system 3
D), write enable (WR: not required when the memory is a ROM), control signals (RAS, CAS) when the memory is a DRAM, and a signal (enable) indicating an available state of the shared memory 10 described later. Is connected to the RAM 32 and the ROM 33, and the first second fixed contact 5a of the bus switch 5 is connected.
Connected to.

Further, 6 is a key input device from the user, and this key input device 6 is a data / address bus 7
Connected to. The data / address bus 7 is a data / address bus which constitutes a second bus system 8 which processes a special effect of a video signal. A master CPU 81, a RAM 82, and a ROM 83 that control the second bus system 8 are connected to the data / address bus 7. The data / address bus 7 is also connected to a print head block 9 for printing.

The data / address bus 7 is also connected to the second fixed contact 5B of the bus switch 5. Further, the chip select (CS) and the read enable (R) from the master CPU 81 that controls the second bus system 8
D), write enable (WR: not required when the memory is a ROM), control signals (RAS, CAS) when the memory is a DRAM, and a signal (enable) indicating an available state of the shared memory 10 described later. Is connected to the RAM 82 and the ROM 83, and the second second fixed contact 5b of the bus switch 5 is connected.
Connected to.

The 1 movable contact 5X and the 2 movable contact 5x of the bus switch 5 are connected to the data / data of the shared memory 10.
Connected to address bus and control bus. The shared memory 10 has an interface that can be connected to both the first and second bus systems 3 and 8 described above.

Further, reference numeral 11 is a synchronization generating circuit, which is driven in synchronization with a synchronization signal of a video signal supplied to the free-running or input terminal 1. The signal from the synchronization generating circuit 11 is supplied to the master CPUs 31 and 81 that control the first and second bus systems 3 and 8.

Further, the signal from the synchronization generating circuit 11 is supplied to the switch control circuit 12 and, for example, during the horizontal blanking period of the video signal which is written and read into the shared memory 10 at a high speed, the bus switch 5 operates. Movable contacts 5X, 5x from the first fixed contacts 5A, 5a,
It is switched to the second fixed contacts 5B and 5b.

Therefore, in this apparatus, when the video signal is written from the input terminal 1 to the shared memory 10, the synchronization generating circuit 11 is driven in synchronization with the synchronization signal of the video signal supplied to the input terminal 1 to generate this synchronization. According to the signal from the circuit 11, the video signal is written to the shared memory 10 through the first bus system 3.

Further, when the video signal is read from the shared memory 10 to the arbitrary video monitor 4, the synchronization generating circuit 11 is driven by free running, and according to the signal from the synchronization generating circuit 11, it is optionally transmitted through the first bus system 3. The video signal is read out to the video monitor 4.

Then, the bus switch 5 is switched to the second fixed contacts 5B and 5b during high-speed writing and reading to and from the shared memory 10, for example, during a horizontal blanking period. As a result, during this period, the shared memory 10 is under the control of the second bus system 8 and data can be transferred between the shared memory 10 and the second bus system 8.

That is, during this period, the program control method directly performed by the master CPU 81 which controls the second bus system 8 and so-called direct memory access (D
Data can be transferred by block transfer by (MA). Then, using the transferred data, processing such as special effects of the video signal written in the shared memory 10 and printing are performed.

Thus, according to the above-mentioned device, the plurality of bus systems 3 and 8 and the plurality of bus systems 3 and 8 are provided.
Shared memory 10 having an interface that can be connected to all of the above, a bus switch 5 that connects the shared memory 10 to each of the plurality of bus systems 3 and 8, and a switch control circuit that controls the switching timing of the bus switch 5. 12 and a plurality of bus systems 3, 8
By making it possible to arbitrarily change the connection form between the shared memory 10 and the shared memory 10, a plurality of bus systems can operate by sharing a single memory, and the same configuration can be achieved in different bus systems with a simple configuration. It is possible to perform processing using data.

That is, in the above-mentioned device, when the same data is used in a plurality of independent bus systems, all the bus systems do not need to have memories for storing data, and the data storage unit is provided at one place. Therefore, the number of memories for storing data can be reduced. Also,
By performing maintenance on one location, it can be reliably reflected on all bus systems.

Further, data transfer can be performed asynchronously. For this reason, it is not necessary to wait for permission of the transfer partner at the time of transfer, so that there is no waste of time. Further, even when the transfer is performed by interruption, the processing in the own bus system is not interrupted by the transfer of the data from the other. Therefore, the processing in each bus system can be smoothly performed, and the processing efficiency can be improved.

Further, the present invention is not limited to the memory control device used in the above video printer device, but is generally applied when different bus systems use the same data. Therefore, a general embodiment is as follows. In the following description, three bus systems 3, 8, and 13 are provided, but the number of bus systems may be larger.

Therefore, first in FIG. 2, the switch control circuit 1
This is the case where 2 takes the initiative and controls the switching of the bus switch 5. In this case, as shown in the drawing, only the start timing of switching is supplied by an external signal, and the switch control circuit 12 switches the bus systems 3, 8 and 13 in order.

According to this, the connection period to each bus system 3, 8, 13 by switching is constant,
If the external signal is periodic, each bus system 3, 8, 1
Switching with 3 becomes periodic, and each bus system 3,
The shared memory 10 of the master CPUs 8 and 13 can be periodically accessed.

Therefore, when each bus system 3, 8, 13 uses the same data in the shared memory 10, the switch control circuit 12 sequentially switches to each bus system 3, 8, 13 so that each master CPU Is shared memory 10
It is possible to access the data and read the data when the processing timing is good. It should be noted that each master CPU can know whether or not the shared memory 10 is available from the signal (enable) indicating the available state from the shared memory 10.

Further, FIG. 3 shows each bus system 3, 8, 1
In this case, switching of the bus switch 5 by the switch control circuit 12 is controlled according to the chip select (CS) signal from the switch 3. In this case, as shown in the figure, the chip select (CS) signal in the control buses (shown by broken lines) of the bus systems 3, 8, 13 is the switch control circuit 12.
Is supplied to. In this case, each bus system 3, 8, 1
The connection period of 3 and the shared memory 10 can be changed according to the length of the chip select (CS) signal. Alternatively, this connection period can be generated by the switch control circuit 12.

Therefore, for example, when data is transferred from the first bus system 3 to the second bus system 8, the shared memory is first used by using the chip select (CS) signal from the first bus system 3. Transfer the data to 10. After that, the chip select (CS) signal from the second bus system 8 is used to transfer the data from the shared memory 10 to the memory in the second bus system 8.

In this way, also in this example, data can be transferred from the first bus system 3 to the second bus system 8. Each master CPU sends a signal (enable) indicating the available state from the shared memory 10.
From e), it is possible to know whether the shared memory 10 is available.

Further, FIG. 4 shows that the switch control circuit 12 has
This is a case where an external signal corresponding to each bus system 3, 8, 13 is input, and switching of the bus switch 5 is controlled according to this signal. In this case, the external signal is a signal generator independent of each bus system 3, 8, 13 or
By using the synchronizing signal of the video signal or the like, the switching can be performed at a timing different from each of the bus systems 3, 8, and 13. Thereby, the connection period itself can be changed by an external signal, for example. Alternatively, this connection period can be generated by the switch control circuit 12.

Therefore, when data is transferred from the first bus system 3 to the second bus system 8 by utilizing, for example, a synchronizing signal of a video signal, a vertical blanking period (horizontal blanking during synchronization). Data is transferred to the shared memory 10 during the ranking period). After that, data is transferred from the shared memory 10 to the memory in the second bus system 8 during the horizontal blanking period.

In this way, data can be transferred from the first bus system 3 to the second bus system 8 also in this example. Each master CPU sends a signal (enable) indicating the available state from the shared memory 10.
From e), it is possible to know whether the shared memory 10 is available.

As described above, the bus is switched by the bus switch and the shared memory is set as the master C of each bus system.
By performing control that can be managed by the PU, it is possible to use the same data or transfer data between independent bus systems.

[0042]

According to the present invention, a plurality of bus systems, a memory having an interface connectable to all of the plurality of bus systems, a switching means for switching and connecting the memories to the plurality of bus systems, and It is composed of control means for controlling the switching timing of the switching means, and by allowing the connection form of multiple bus systems and memories to be changed arbitrarily, multiple bus systems operate by sharing a single memory. It has become possible to perform processing using the same data in different bus systems with a simple configuration.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an example of a case where a memory control device according to the present invention is used in, for example, a video printer device to perform processing such as a special effect on an input video signal and perform printing.

FIG. 2 is a configuration diagram of another example of a memory control device according to the present invention.

FIG. 3 is a configuration diagram of another example of the memory control device according to the present invention.

FIG. 4 is a configuration diagram of another example of the memory control device according to the present invention.

[Explanation of symbols]

 1 Digital Video Signal Input Terminal 2 Data / Address Bus 3 First Bus System 31 CPU 32 RAM 33 ROM 4 Digital Input Video Monitor 5 Bus Switch 6 Key Input Device 7 Data / Address Bus 8 Second Bus System 81 CPU 82 RAM 83 ROM 9 print head block 10 shared memory 11 synchronization generation circuit 12 switch control circuit

Claims (5)

[Claims] 1. A plurality of bus systems, a memory having an interface capable of connecting to all of the plurality of bus systems, a switching means for switching and connecting the memories to the plurality of bus systems, and a switching of the switching means. And a control means for controlling the timing of the memory control device, wherein the connection form between the plurality of bus systems and the memory can be arbitrarily changed. 2. The memory control device according to claim 1, wherein the control means is controlled based on a synchronizing signal of a signal written in the memory. 3. The memory control device according to claim 1, wherein the control means is controlled based on selection signals from the plurality of bus systems. 4. The memory control device according to claim 1, wherein the control means is controlled based on a control signal from the outside. 5. The memory control device according to claim 1, wherein a video signal is written in the memory through a first bus system of the plurality of bus systems, and at least during a horizontal blanking period of the video signal, A memory controller for reading the memory through a second bus system of the plurality of bus systems.