JP2005078599A - Computer system and its electronic circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a computer system with high generality for applying a computer system which performs data transfer among a plurality of buses to various systems and a computer system which is equipped with such electronic circuit. <P>SOLUTION: This computer system is provided with a system bus I/F 211 connected to an MPU, each interface such as a local bus I/F214, an address decoder 216 for decoding an address signal to be outputted by the MPU, and for generating device selection signals(/IO_CS0 to /IO_CS7) and a register 17 bus-connected to the address decoder 216. The register 17 is stored with information showing to which bus each of devices corresponding to those device selection signals is connected, that is to which interface each of those devices is connected. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a computer system and an electronic circuit thereof, and more specifically to a highly versatile computer system capable of applying a computer system for transferring data between a plurality of buses to various systems and an electronic circuit thereof. .

  A computer system is configured by connecting various devices, specifically, chips on which devices are configured, by a bus, with a processor (MPU) as a center.

  In a computer system in which a processor and a plurality of devices are connected to one bus, a device selection signal is directly output from the processor, or an address from the processor is decoded to generate a device selection signal, and a device to be accessed Can be designated to transfer data (see, for example, Patent Document 1).

  However, recent computer systems generally have multiple buses due to demands for high functionality and high speed, and even if a device to be accessed is simply specified by a device selection signal, the device is connected to any bus. If the bus connection is not controlled depending on whether or not the data is transferred, data cannot be transferred between the processor and the designated device.

Therefore, a computer system having a plurality of buses by providing an ASIC (gate array) in which a plurality of buses, one of which is connected to the processor, is connected in the computer system, and the gate array controls the coupling of the buses. Even so, a computer system for designating a device to be accessed and transferring data has been proposed.
Japanese Patent Laid-Open No. 5-257819

  However, the above-described conventional computer system has low versatility because the relationship between the device and the bus is fixed in advance, and an ASIC (gate array) must be designed and manufactured for each system. There was a problem that the burden was heavy.

  The present invention has been made in view of such circumstances, and a highly versatile electronic circuit capable of applying a computer system that performs data transfer between a plurality of buses to various systems, and such an electronic circuit. An object is to provide a computer system provided.

  A computer system according to a first aspect of the present invention is a plurality of buses including one bus to which a processor is connected, and is connected to one of the plurality of buses, and is selectively accessed by a selection signal output from the processor. And a bus-to-bus controller that controls data transfer between the buses, wherein the device selected by the selection signal is connected to any of the buses Storage means for storing device information indicating whether the processor is connected, and the inter-bus controller is selected based on the device information stored in the storage means by the bus to which the processor is connected and the selection signal It is characterized in that it controls data transfer with the bus to which the device is connected.

  In such a computer system according to the first invention, device information indicating which of the plurality of buses the device selected by the selection signal output from the processor is connected to is stored in the storage means. Then, based on the device information stored in the storage means, data is transferred between the bus to which the processor is connected and the bus to which the device selected by the selection signal is connected.

  A computer system according to a second invention is the computer system according to the first invention, wherein the inter-bus control unit includes an internal bus and a plurality of interfaces connecting the plurality of buses via the internal bus. The interface connected to the bus to which the processor is connected is connected to the bus to which the device selected by the selection signal is connected based on the device information stored in the storage means Further includes means for granting a right to occupy the internal bus.

  In such a computer system according to the second invention, the interface connected to the bus to which the processor is connected is connected to the device selected by the selection signal based on the device information stored in the storage means. The bus occupation right of the internal bus is given so as to transfer data to and from the interface connected to the existing bus.

  A computer system according to a third invention is characterized in that, in the computer system according to the first invention or the second invention, the device information stored in the storage means is rewritable from the outside.

  In such a computer system according to the third invention, the storage means can rewrite information, and device information to be stored in the storage means is rewritten to information given from the outside.

  An electronic circuit of a computer system according to a fourth aspect of the present invention includes an internal bus, a plurality of interfaces connected via the internal bus, and an address decoder that decodes an address signal input from the outside to generate a device selection signal And an electronic circuit of a computer system for controlling data transfer between the buses, wherein the interface occupies the internal bus based on a device selection signal generated by the address decoder. It is characterized by comprising a storage unit for storing information for designating.

  In the electronic circuit of the computer system according to the fourth aspect of the present invention, on any interface among the plurality of interfaces based on the device selection signal generated by the address decoder decoding the address signal input from the outside. Information specifying whether to occupy the internal bus is stored in the storage unit.

  According to the computer system of the present invention, device information indicating which of the plurality of buses the device selected by the selection signal output from the processor is connected to is stored in the storage unit from the outside. Therefore, the computer system for transferring data between a plurality of buses can be applied to various systems by appropriately changing the device information stored in the storage means. Therefore, it is not necessary to design and manufacture the inter-bus control unit for each system, and the man-hour and cost burden can be reduced.

  According to the electronic circuit of the computer system according to the present invention, information indicating which interface occupies the internal bus is stored in the storage unit from the outside based on the device selection signal generated by the address decoder. Therefore, data transfer between a plurality of buses can be applied to various systems by appropriately changing information stored in the storage unit from the outside. Therefore, it is not necessary to design and manufacture an electronic circuit for each system, and an excellent effect is achieved such that the burden on man-hours and costs can be reduced.

  Hereinafter, the present invention will be specifically described with reference to the drawings showing embodiments thereof. FIG. 1 is a block diagram showing an internal configuration example of a multifunction peripheral as an embodiment of a computer system of the present invention.

  The multifunction machine as a computer system of the present invention has functions such as reading of a document image, copy output (printout) and transmission by facsimile communication, and printout of data received by facsimile communication. Various functions as described above are realized in accordance with a computer program stored in the (read-only memory) 12.

  The internal configuration of the MFP as the computer system of the present invention shown in FIG. 1 includes a system bus 20 directly connected to the MPU 11 as a control center, and a local bus 30 and a panel bus 50 that are not directly connected to the MPU 11. A plurality of buses, and the buses 20, 30, and 50 are connected by a gate array 21 that functions as an inter-bus control unit that is an electronic circuit of the present invention, and data transfer between the buses is switched. Yes.

  The MPU 11 is connected via the system bus 20 to the ROM 12 and the SRAM 14 used as various information holding memories. The MPU 11 is also connected to the gate array 21 via the system bus 20.

  The gate array 21 is connected to the SDRAM 22 used as an image memory, and is connected to the system bus 20, the panel bus 50, and the local bus 30 described above.

  The system bus 20 has a modem 23, an NCU 24, a reading image processing circuit 36, etc., the panel bus 50 has an operation panel 51, the local bus 30 has a printing image processing circuit 31, a printing memory controller 33, and a printing use. A codec 34, a reading memory controller 38, a reading codec 39, and the like are connected.

  The operation panel 51 includes character keys, numeric keys, speed dial keys, one-touch dial keys, various function keys, and a display device such as an LCD, which are necessary for operating the multi-function peripheral that is the computer system of the present invention.

  A printer engine 32 and the above-described memory controller 33 are connected to the print image processing circuit 31 connected to the local bus 30. The memory controller 33 is directly connected to the local bus 30 and is also connected to an SDRAM 35 used as a print work area.

  The printer engine 32 is provided in a printing unit (printer) (not shown). The encoded image data is sent from the local bus 30 to the print codec 34 to be decoded (decoded) into the print data, and then supplied from the print image processing circuit 31 to the printer engine 32 via the memory controller 33. .

  A CCD 37 and the memory controller 38 are connected to the reading image processing circuit 36 connected to the system bus 20. The memory controller 38 is directly connected to the local bus 30 and is also connected to an SDRAM 40 used as a work area for reading.

  The CCD 37 is provided in a reading unit (scanner) (not shown). The signal read by the CCD 37 is processed by the reading image processing circuit 36 and converted into, for example, monochrome binary image data. The converted image data is sent from the memory controller 38 to the reading codec 39 and coded (encoded), and then output to the local bus 30.

  The modem 23 and the NCU 24 are connected to the gate array 21 via the system bus 20, but are also connected to each other. The modem 23 is a facsimile modem capable of facsimile communication. The NCU 24 is hardware that performs operations for closing and opening an analog line with the public switched telephone network (PSTN). The NCU 24 connects the modem 32 to the public switched telephone network as necessary, and communicates with other facsimile apparatuses. Controls facsimile communication.

  A typical operation of the multi-function peripheral which is the computer system of the present invention having the above-described configuration is as follows.

  Facsimile image data received by the modem 23 via the NCU 24 by facsimile communication from another facsimile machine via the public telephone exchange network is output to the system bus 20 and stored in the SDRAM 22 via the gate array 21. Further, the image data read by the CCD 37 of the reading unit and converted by the reading image processing circuit 36 is supplied from the memory controller 38 to the reading codec 39 and encoded, and then output to the local bus 30 to be gate array. The data is stored in the SDRAM 22 via 21.

  When facsimile image data stored in the SDRAM 22 is transmitted by facsimile, the facsimile image data is output to the system bus 20 via the gate array 21 and transmitted to the public telephone exchange network via the modem 23 and NCU 24. When printing out the facsimile image data stored in the SDRAM 22, the facsimile image data is output to the local bus 30 via the gate array 21, decoded by the print codec 34, and printed from the print image processing circuit 31 to the printer. It is output to the engine 32 and printed out.

  Input / output of data to / from the SDRAM 22 as described above is performed without the MPU 11 by DMA transfer by the DMA controller of the gate array 21.

  On the other hand, the MPU 11 can perform read / write access to each device connected to each bus via the gate array 21. The access is controlled by control signals input / output from the MPU 11 and the gate array 21. Each control signal will be described below. A signal having “/” added to the head of the signal name means that it is low active (significant when it is low level).

  From the MPU 11 to the gate array 21, signals of / MPU_CS (MPU device selection signal), / MPU_RD (MPU read signal), and / MPU_WR (MPU write signal) are applied. / MPU_CS is a higher-level device selection signal that designates a device to which data is to be transferred, / MPU_RD is a signal that identifies that the access target is read, and / MPU_WR is a signal that identifies that the access target is write is there.

  / IO_CS0 (0th device selection signal) is sent from the gate array 21 to the operation panel 51, / IO_CS1 (first device selection signal) is sent from the gate array 21 to the modem 23, and from the gate array 21 to the image processing circuit 31 for printing. / IO_CS2 (second device selection signal), / IO_CS3 (third device selection signal) from the gate array 21 to the memory controller 33, and / IO_CS4 (fourth device selection signal) from the gate array 21 to the print codec 34. ) Is / IO_CS5 (fifth device selection signal) from the gate array 21 to the memory controller 38, and / IO_CS6 (sixth device selection signal) is read from the gate array 21 to the codec 39 for reading from the gate array 21. To the image processing circuit 36 / IO_CS7 (7th Vice selection signal) are given respectively. Further, / IO_WR (IO write signal) and / IO_RD (IO read signal) are also supplied from the gate array 21 to each device.

  Accordingly, the gate array 21 selects the operation panel 51 / IO_CS0, the modem 23 / IO_CS1, and the print image processing circuit 31 in accordance with the / MPU_CS signal supplied from the MPU 11 and the address for selecting a device. / IO_CS2, select memory controller 33 / IO_CS3, select codec 34 for printing / IO_CS4, select memory controller 38 / IO_CS5, select codec 39 for reading / IO_CS6, select image processing circuit 36 for reading A device to which data is to be transferred is selected by making any of IO_CS7 active (low level). Then, the gate array 21 outputs the / IO_RD signal or the / IO_WR signal to cause the device selected by the device selection signal to read or write data, thereby performing the operation as described above. It becomes possible.

  Next, the configuration of the gate array 21 which is the electronic circuit of the present invention will be described with reference to the drawings showing an example thereof. FIG. 2 is a block diagram showing a configuration example of a gate array which is an electronic circuit of the computer system of the present invention.

  In the gate array 21, a system bus I / F 211, an SDRAM I / F 213, a local bus I / F 214, a DMAC (DMA controller) 215, an address decoder 216, and the like are connected to the internal bus 210. A register 217 is connected to the address decoder 216.

  The system bus I / F 211 is an interface to the system bus 20 of the gate array 21, and the signals / MPU_CS, / MPU_WR, and / MPU_RD output from the MPU 11 are input to the system bus I / F 211. The gate array 21 performs data transfer with the modem 23, the NCU 24, and the reading image processing circuit 36 via the system bus 20. The system bus I / F 211 also functions as an interface to the panel bus 50 of the gate array 21, and the gate array 21 performs data transfer with the operation panel 51 via the panel bus 50. The system bus I / F 211 is connected to the panel bus 50 via a buffer (not shown), and controls connection to the panel bus 50 by turning on / off the buffer.

  The SDRAM I / F 213 is an interface for connecting the gate array 21 and the SDRAM 22, and the gate array 21 performs data transfer with the SDRAM 22.

  The local bus I / F 214 is an interface to the local bus 30 of the gate array 21, and the gate array 21 is connected via the local bus 30 to the print image processing circuit 31, the memory controller 33, the print codec 34, the memory controller 38, Data is transferred to and from the reading codec 39.

  The address decoder 216 decodes the address signal for device selection and / MPU_CS output from the MPU 11 and input from the internal bus 210 via the system bus I / F 211, thereby the aforementioned / IO_CS0, / IO_CS1,. , / IO_CS7 is made active (low level).

  Next, the operation of the gate array 21 that controls data transfer between the MPU 11 and the device specified by / IO_CS0, / IO_CS1,..., / IO_CS7 will be described.

  In the register 217, for each of / IO_CS0, / IO_CS1,..., / IO_CS7, to which bus the device corresponding to the device selection signal is connected, that is, to which interface is connected. Are stored in association with each other. The device information stored in the register 217 is written into the register 217 by the MPU 11 when the power is turned on, for example. More specifically, device information corresponding to the configuration of the device and bus of the computer system (in this example, a multifunction device) is set in the computer program stored in the ROM 12, and the computer program is executed. Is written to the register 217.

  In the register 217, for example, for / IO_CS0 = “L” (low level), the operation panel 51 is connected to the panel bus 50, and the interface to the panel bus 50 is the system bus I / F 211. The device information shown is stored. The register 217 is connected to the system bus 20 for the modem 23 or the reading image processing circuit 36 for / IO_CS1 = “L” or / IO_CS7 = “L”. Device information indicating that the face is the system bus I / F 211 is stored. Further, the register 217 stores image processing for printing for / IO_CS2 = "L", / IO_CS3 = "L", / IO_CS4 = "L", / IO_CS5 = "L", or / IO_CS6 = "L". Device information indicating that the circuit 31, the memory controller 33, the print codec 34, the memory controller 38, or the read codec 39 is connected to the local bus 30, and the interface to the local bus 30 is the local bus I / F 214. Is remembered.

  The address decoder 216 decodes the address signal and / MPU_CS input from the MPU 11, generates / IO_CS0, / IO_CS1,..., / IO_CS7, and outputs them to the corresponding device. However, as described above, only one of / IO_CS0, / IO_CS1,..., / IO_CS7, that is, only the device selection signal corresponding to the device to be accessed becomes active.

  Based on the device information stored in the register 217, the system bus I / F 211 appropriately outputs / BS_REQ1 to the SDRAM I / F 213 and / BS_REQ2 to the local bus I / F 214. / BS_REQ1 and / BS_REQ2 are request signals for requesting the right to occupy the internal bus 210 to each interface. Only one of / BS_REQ1 and / BS_REQ2 becomes active and the internal bus 210 Request bus ownership. When the active device selection signal in / IO_CS0, / IO_CS1,..., / IO_CS7 is / IO_CS0, / IO_CS1, or / IO_CS7, there is no need to transfer data with the MPU 11 via the internal bus 210. Therefore, it is not necessary to request the bus occupation right of the internal bus 210.

  On the other hand, the SDRAM I / F 213 that receives / BS_REQ1 outputs / BS_ACK1, and the local bus I / F 214 that receives / BS_REQ2 outputs / BS_ACK2 to the system bus I / F 211, respectively. / BS_ACK1, / BS_ACK2 is an approval signal indicating that the bus occupancy right has been approved for each request signal. By outputting (replying) the approval signal to the system bus I / F 211, / IO_CS2, / IO_CS3 ..., / IO_CS6 to establish a data transfer path between the bus to which the active device is connected and the bus to which the MPU 11 is connected.

  The address decoder 216 generates / IO_RD and / IO_WR from / MPU_RD and / MPU_WR input from the MPU 11 and outputs them to each device. / IO_RD is a signal for identifying that the access target is read, and / IO_WR is a signal for identifying that the access target is writing, and transfers (reads or writes) data between the MPU 11 and the device. Let it be done. If the active device selection signal among / IO_CS0, / IO_CS1,..., / IO_CS7 is / IO_CS1 or / IO_CS7, the device is connected to the same system bus 20 as the MPU 11, and the data There is no need to establish a transfer path. That is, the address decoder 216 performs data transfer by outputting a device selection signal and / IO_RD or / IO_WR to the device. When the active device selection signal is / IO_CS0, the data transfer path to the system bus 20 to which the MPU 11 is connected is established by turning on the above-described buffer, and / IO_RD or / IO_WR Is transferred to the device to perform data transfer.

  As described above, the significance of the present invention is that the register 217 for storing the device information indicating which bus is connected to the device corresponding to the device selection signal, that is, which interface is connected to the computer system. (In this embodiment, it is added to the multi-function peripheral). By doing so, the device information stored in the register 217 is changed from the outside so that data between the buses corresponding to each system configuration can be obtained. Transfer can be controlled. Therefore, it is not necessary to design and manufacture a gate array for each system. Therefore, it is possible to provide a highly versatile gate array with excellent man-hours and costs, and a computer system including such a gate array.

  In the above-described embodiment, the register 217 for storing device information indicating which bus is connected to the device selected by the device selection signal, that is, which interface is connected to the gate array 21. However, it may be provided outside the gate array. In such a case, the gate array and the register are connected by a signal line, and the device information stored in the register is stored. Should be obtained.

  In the above-described embodiment, the devices that can be selected by the MPU 11 are the operation panel 51, the modem 23, the print image processing circuit 31, the memory controller 33, the print codec 34, the memory controller 38, the read codec 39, and the read. However, this is merely an example, and even when the MPU 11 can select a larger number or a smaller number of devices, the gate array should be configured according to the number of selectable devices. Needless to say, this is possible.

  Furthermore, in the above-described embodiment, the register 217 is a software rewritable device, and the device information is read from the ROM 12 when the power is turned on and written into the register 217 under the control of the MPU 11. The register 217 may be a hardware writable device such as a fuse ROM or EEPROM, and device information is written by a ROM writer or the like according to the configuration of the device of the computer system (in the embodiment, a multi-function peripheral) and the bus. Such a form may be sufficient.

  Furthermore, in the above-described embodiment, each signal is low active (significant when low), but each signal may be high active (significant when high), It is not necessary that all signals be unified as either low active or high active.

1 is a block diagram illustrating an internal configuration example of a multifunction peripheral as an embodiment of a computer system of the present invention. FIG. It is a block diagram which shows the example of a gate array structure which is an electronic circuit of the computer system of this invention.

Explanation of symbols

11 MPU
12 ROM
DESCRIPTION OF SYMBOLS 20 System bus 21 Gate array 23 Modem 30 Local bus 31 Image processing circuit for printing 33 Memory controller 34 Codec for printing 36 Image processing circuit for reading 38 Memory controller 39 Codec for reading 50 Panel bus 51 Operation panel 211 System bus I / F
214 Local bus I / F
215 DMAC
216 Address decoder 217 Register

Claims (4)

A plurality of buses including one bus to which a processor is connected, a plurality of devices connected to one of the plurality of buses and selectively accessed by a selection signal output from the processor, and between each bus A computer system comprising an inter-bus controller for controlling data transfer in
Storage means for storing device information indicating which of the plurality of buses the device selected by the selection signal is connected to;
The inter-bus controller is configured to transfer data between a bus to which the processor is connected and a bus to which a device selected by the selection signal is connected based on device information stored in the storage unit. A computer system characterized in that it is designed to control the above. The inter-bus control unit includes an internal bus and a plurality of interfaces that connect the plurality of buses via the internal bus,
The interface connected to the bus to which the processor is connected is connected to the interface connected to the bus to which the device selected by the selection signal is connected based on the device information stored in the storage means. 2. The computer system according to claim 1, further comprising means for granting a bus occupation right of the internal bus.   3. The computer system according to claim 1, wherein the device information stored in the storage unit is rewritable from the outside. Equipped with an internal bus, a plurality of interfaces connected via the internal bus, and an address decoder that decodes an address signal input from the outside to generate a device selection signal, and controls data transfer between each bus A computer system electronic circuit,
An electronic circuit of a computer system, comprising: a storage unit that stores information designating which interface occupies the internal bus based on a device selection signal generated by the address decoder.

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