JP2005078598A - Computer system and its electronic circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic circuit with high generality for applying a computer system which performs data transfer through DMA among a plurality of buses without using any processor to various systems and a computer system equipped with such electronic circuit. <P>SOLUTION: This computer system is provided with a system bus I/F 211 connected to an MPU, each interface such as a local bus I/F 214, a DMAC 215 which inputs data transfer request signals(/DREQ0, /DREQ1, /DREQ2) from each device and a register 217 connected to the DMAC215. The register 217 is stored with information showing to which bus each of transfer origin devices and transfer destination devices corresponding to those data transfer request signals /DERQ0, /DREQ1, and /DREQ2 is connected, that is, to which interface each of those devices is connected. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a computer system and its electronic circuit, and more specifically, it is possible to apply a computer system employing direct memory access (DMA) for transferring data without intervention of a processor (MPU) to various systems. The present invention relates to a highly versatile computer system and its electronic circuit.

  A computer system is configured by connecting various devices, specifically, chips on which devices are configured, by a bus, with a processor (MPU) as a center. Further, a direct memory access (hereinafter referred to as “DMA”) method is known in which data is transferred between a plurality of devices connected to a bus without interposing a processor, thereby realizing high-speed data transfer (for example, DMA) (for example, (See Patent Document 1).

By the way, in recent years, there has been a demand for further increase in functionality and speed of computer systems. In order to parallelize data transfer, a plurality of buses are provided in the system, and an ASIC (gate gate) for controlling the coupling of these buses There has been proposed a computer system provided with an array.
JP-A-8-235107

  However, when data transfer is performed by a DMA controller (hereinafter referred to as DMAC), if the device to be accessed cannot be recognized to which bus is connected, the bus serving as the data transfer path cannot be selected and combined. Data transfer cannot be performed. The relationship between the device and the bus can be fixed to the gate array in hardware, but if that is done, the gate array cannot be applied to other systems, and an ASIC (gate array) is designed for each system. In addition, there is a problem that the burden on the man-hour and the cost is large.

  The present invention has been made in view of such circumstances, and has high versatility in which a computer system that performs DMA data transfer between a plurality of buses without using a processor can be applied to various systems. An object is to provide an electronic circuit and a computer system including such an electronic circuit.

  According to a first aspect of the present invention, there is provided a computer system including a plurality of buses including a single bus connected to a processor, a plurality of devices connected to any of the plurality of buses, and a data transfer request signal output from each device. Based on a computer system comprising an inter-bus control unit for controlling data transfer between each bus without interposing the processor, wherein the inter-bus control unit includes a direct memory access controller, and each device includes the device Storage means for storing device information indicating which of the plurality of buses is connected, and a bus for direct memory access is connected based on the device information stored in the storage means Thus, the data transfer is controlled.

  In such a computer system according to the first invention, device information indicating which of the plurality of buses each device is connected to is stored in the storage means, and stored in the storage means. Based on the device information, the bus for direct memory access is connected to transfer data.

  A computer system according to a second invention is the computer system according to the first invention, wherein the inter-bus control unit includes an internal bus and a plurality of interfaces connecting the plurality of buses via the internal bus. And the direct memory access controller is connected to each interface connected to each bus to which the data transfer source device and the data transfer destination device are connected based on the device information stored in the storage means. It has means for granting a bus occupation right of the internal bus.

  In the computer system according to the second invention, each direct memory access controller is connected to the data transfer source device and the data transfer destination device based on the device information stored in the storage means. The right to occupy the internal bus is given to transfer data to and from each interface connected to the bus.

  A computer system according to a third invention is characterized in that, in the computer system according to the first invention or the second invention, the device information stored in the storage means is rewritable from the outside.

  In such a computer system according to the third invention, the storage means can rewrite information, and device information to be stored in the storage means is rewritten to information given from the outside.

  An electronic circuit of a computer system according to a fourth invention comprises an internal bus, a plurality of interfaces connected via the internal bus, and a direct memory access controller, and is intended to control data transfer between the buses. An electronic circuit of a computer system comprising a storage unit for storing information designating which interface occupies the internal bus based on a data transfer request signal input from the outside. And

  In the electronic circuit of the computer system according to the fourth aspect of the present invention, information for designating which of the plurality of interfaces occupies the internal bus based on the data transfer request signal input from the outside Is stored in the storage unit.

  According to the computer system of the present invention, the device information indicating which of the plurality of buses each device is connected to is stored in the storage means from the outside. By appropriately changing the device information stored in the storage means, a computer system that performs data transfer by DMA between a plurality of buses can be applied to various systems. Therefore, it is not necessary to design and manufacture the inter-bus control unit for each system, and the man-hour and cost burden can be reduced.

  Further, according to the electronic circuit of the computer system according to the present invention, based on the data transfer request signal input from the outside, information indicating which interface occupies the internal bus is stored in the storage unit from the outside. Thus, by appropriately changing the information stored in the storage unit from the outside, data transfer by DMA between a plurality of buses can be applied to various systems. Therefore, it is not necessary to design and manufacture an electronic circuit for each system, and an excellent effect is achieved such that the burden on man-hours and costs can be reduced.

  Hereinafter, the present invention will be specifically described with reference to the drawings showing embodiments thereof. FIG. 1 is a block diagram showing an internal configuration example of a multifunction peripheral as an embodiment of a computer system of the present invention.

  The multifunction machine as a computer system of the present invention has functions such as reading of a document image, copy output (printout) and transmission by facsimile communication, and printout of data received by facsimile communication. Various functions as described above are realized in accordance with a computer program stored in the (read-only memory) 12.

  The internal configuration of the MFP as the computer system of the present invention shown in FIG. 1 includes a system bus 20 directly connected to the MPU 11 as a control center, and a local bus 30 and a panel bus 50 that are not directly connected to the MPU 11. A plurality of buses, and the buses 20, 30, and 50 are connected by a gate array 21 that functions as an inter-bus control unit that is an electronic circuit of the present invention, and data transfer between the buses is switched. Yes.

  The MPU 11 is connected via the system bus 20 to the ROM 12 and the SRAM 14 used as various information holding memories. The MPU 11 is also connected to the gate array 21 via the system bus 20.

  The gate array 21 is connected to the SDRAM 22 used as an image memory, and is connected to the system bus 20, the panel bus 50, and the local bus 30 described above.

  The system bus 20 has a modem 23, an NCU 24, a reading image processing circuit 36, etc., the panel bus 50 has an operation panel 51, the local bus 30 has a printing image processing circuit 31, a printing memory controller 33, and a printing use. A codec 34, a reading memory controller 38, a reading codec 39, and the like are connected.

  The operation panel 51 includes character keys, numeric keys, speed dial keys, one-touch dial keys, various function keys, and a display device such as an LCD, which are necessary for operating the multi-function peripheral that is the computer system of the present invention.

  A printer engine 32 and the above-described memory controller 33 are connected to the print image processing circuit 31 connected to the local bus 30. The memory controller 33 is directly connected to the local bus 30 and is also connected to an SDRAM 35 used as a print work area.

  The printer engine 32 is provided in a printing unit (printer) (not shown). The encoded image data is sent from the local bus 30 to the print codec 34 to be decoded (decoded) into the print data, and then supplied from the print image processing circuit 31 to the printer engine 32 via the memory controller 33. .

  A CCD 37 and the memory controller 38 are connected to the reading image processing circuit 36 connected to the system bus 20. The memory controller 38 is directly connected to the local bus 30 and is also connected to an SDRAM 40 used as a work area for reading.

  The CCD 37 is provided in a reading unit (scanner) (not shown). The signal read by the CCD 37 is processed by the reading image processing circuit 36 and converted into, for example, monochrome binary image data. The converted image data is sent from the memory controller 38 to the reading codec 39 and coded (encoded), and then output to the local bus 30.

  The modem 23 and the NCU 24 are connected to the gate array 21 via the system bus 20, but are also connected to each other. The modem 23 is a facsimile modem capable of facsimile communication. The NCU 24 is hardware that performs operations for closing and opening an analog line with the public switched telephone network (PSTN). The NCU 24 connects the modem 32 to the public switched telephone network as necessary, and communicates with other facsimile apparatuses. Controls facsimile communication.

  A typical operation of the multi-function peripheral which is the computer system of the present invention having the above-described configuration is as follows.

  Facsimile image data received by the modem 23 via the NCU 24 by facsimile communication from another facsimile machine via the public telephone exchange network is output to the system bus 20 and stored in the SDRAM 22 via the gate array 21. Further, the image data read by the CCD 37 of the reading unit and converted by the reading image processing circuit 36 is supplied from the memory controller 38 to the reading codec 39 and encoded, and then output to the local bus 30 to be gate array. The data is stored in the SDRAM 22 via 21.

  When facsimile image data stored in the SDRAM 22 is transmitted by facsimile, the facsimile image data is output to the system bus 20 via the gate array 21 and transmitted to the public telephone exchange network via the modem 23 and NCU 24. When printing out the facsimile image data stored in the SDRAM 22, the facsimile image data is output to the local bus 30 via the gate array 21, decoded by the print codec 34, and printed from the print image processing circuit 31 to the printer. It is output to the engine 32 and printed out.

  Input / output of data to / from the SDRAM 22 as described above is performed without the MPU 11 by DMA transfer by the DMA controller of the gate array 21.

  The DMA transfer is controlled by a control signal connected to each bus and input / output from each device and the gate array 21. Each control signal will be described below. A signal having “/” added to the head of the signal name means that it is low active (significant when it is low level).

  / DREQ0 (0th data transfer request signal) is sent from the modem 23 to the gate array 21, / DREQ1 (first data transfer request signal) is sent from the print codec 34 to the gate array 21, and the read codec 39 is sent to the gate array 21. / DREQ2 (second data transfer request signal) is applied to each.

  On the other hand, the gate array 21 that has received the data transfer request establishes a connection between the bus to which the data transfer source device is connected and the bus to which the data transfer destination device is connected. / DACK0 (0th data transfer approval signal) is sent to the modem 23, / DACK1 (first data transfer approval signal) is sent from the gate array 21 to the print codec 34, and / DACK2 is sent from the gate array 21 to the read codec 39. (Second data transfer approval signal) is respectively provided.

  In other words, each device requests data transfer to the gate array 21, and the gate array 21 connects the bus to which the data transfer source device is connected to the bus to which the data transfer destination device is connected. After the establishment, DMA can be performed by giving a signal indicating that to the device that has requested the data transfer. When performing DMA, in order to avoid data collision with the MPU 11, a hold signal (wait signal) is output to the MPU 11, and the operation of the MPU 11 is temporarily stopped before memory access is performed.

  Next, the configuration of the gate array 21 which is the electronic circuit of the present invention will be described with reference to the drawings showing an example thereof. FIG. 2 is a block diagram showing a configuration example of a gate array which is an electronic circuit of the computer system of the present invention.

  In the gate array 21, a system bus I / F 211, an SDRAM I / F 213, a local bus I / F 214, a DMAC 215, an address decoder 216, and the like are connected to the internal bus 210. In addition, a register 217 is connected to the address decoder 216 by a bus, and the register 217 is also connected to the DMAC 215.

  The system bus I / F 211 is an interface of the gate array 21 to the system bus 20, and the gate array 21 performs data transfer with the modem 23, the NCU 24, and the reading image processing circuit 36 via the system bus 20. The system bus I / F 211 also functions as an interface to the panel bus 50 of the gate array 21, and the gate array 21 performs data transfer with the operation panel 51 via the panel bus 50. The system bus I / F 211 is connected to the panel bus 50 via a buffer (not shown), and controls connection to the panel bus 50 by turning on / off the buffer.

  The SDRAM I / F 213 is an interface for connecting the gate array 21 and the SDRAM 22, and the gate array 21 performs data transfer with the SDRAM 22.

  The local bus I / F 214 is an interface to the local bus 30 of the gate array 21, and the gate array 21 is connected via the local bus 30 to the print image processing circuit 31, the memory controller 33, the print codec 34, the memory controller 38, Data is transferred to and from the reading codec 39.

  Next, the operation of the gate array 21 that controls data transfer between devices by DMA without using the MPU 11 will be described.

  In the register 217, for each of / DREQ0, / DREQ1, and / DREQ2, to which bus the transfer source device and the transfer destination device corresponding to the data transfer request signal are connected, that is, which Is stored in association with device information indicating whether it is connected to the interface. The device information stored in the register 217 is written into the register 217 by the MPU 11 when the power is turned on, for example. More specifically, device information corresponding to the configuration of the device and bus of the computer system (in this example, a multifunction device) is set in the computer program stored in the ROM 12, and the computer program is executed. Is written to the register 217.

  In the register 217, for example, the modem 23 is connected to the system bus 20 in order to control the DMA transfer operation between the modem 23 and the SDRAM 22 with respect to / DREQ0 = "L" (low level). Device information indicating that the interface to the bus 20 is the system bus I / F 211 and that the interface to the SDRAM 22 is the SDRAM I / F 213 is stored.

  The register 217 has a print codec 34 connected to the local bus 30 to control the DMA transfer operation between the print codec 34 and the SDRAM 22 with respect to / DREQ1 = "L". Device information indicating that the interface to the bus 30 is the local bus I / F 214 and that the interface to the SDRAM 22 is the SDRAM I / F 213 is stored.

  Further, in the register 217, the read codec 39 is connected to the local bus 30 in order to control the DMA transfer operation between the read codec 39 and the SDRAM 22 for / DREQ2 = "L". Device information indicating that the interface to the bus 30 is the local bus I / F 214 and that the interface to the SDRAM 22 is the SDRAM I / F 213 is stored.

  The DMAC 215 refers to the device information stored in the register 217 from / DREQ0, / DREQ1 and / DREQ2 input from each device, and / BREQ0 to the system bus I / F 211 and / BREQ1 to the SDRAM I / F 213. , / BREQ2 is output to the local bus I / F 214, respectively. For each / DREQ0, / DREQ1, / DREQ2, any one of / BREQ0, / BREQ2 and / BREQ1, that is, a signal corresponding to the device that should access SDRAM22 and SDRAM22 is active. . / BREQ0, / BREQ1, and / BREQ2 are request signals for requesting the right to occupy the internal bus 210 to each interface, and any one of / BREQ0, / BREQ1, and / BREQ2 becomes active. Requests the right to occupy the internal bus 210.

  Specifically, for example, when / DREQ0 = "L", in order to perform DMA transfer between the modem 23 and the SDRAM 22, with reference to the register 217, / BREQ0 and / BREQ1 are made active ("L"), The bus channel between the modem 23 and the SDRAM 22 is turned on.

  When / DREQ1 = "L", in order to perform DMA transfer between the print codec 34 and the SDRAM 22, with reference to the register 217, / BREQ2 and / BREQ1 are made active ("L"), and the print codec 34 and the SDRAM 22 are turned on.

  Further, when / DREQ2 = "L", in order to perform the DMA transfer between the reading codec 39 and the SDRAM 22, the register 217 is referred to and / BREQ2 and / BREQ1 are made active ("L") to read the codec. The bus channel between 39 and SDRAM 22 is turned on.

  On the other hand, the system bus I / F 211 that receives / BREQ0 outputs / BACK0, the SDRAM I / F213 that receives / BREQ1 outputs / BACK1, and the local bus I / F 214 that receives / BREQ2 outputs / BACK2 to the DMAC 215. . / BACK 0, / BACK 1, / BACK 2 are approval signals indicating that the bus occupancy right has been approved for each request signal. By outputting (replying) the approval signal to the DMAC 215, / DREQ 0, / DREQ 1, / A data transfer path between the device that has output DREQ2 and the SDRAM 22 is established.

  The DMAC 215 outputs / DACK0 to the modem 23 that requested / DREQ0, / DACK1 to the print codec 34 that requested / DREQ1, and / DACK2 to the read codec 39 that requested / DREQ2. And that the data transfer path has been established. By receiving this notification, each device transfers (reads or writes) data to / from the SDRAM 22 via the internal bus 210 without interposing the MPU 11.

  As described above, the significance of the present invention is to which bus the transfer source device and the transfer destination device are respectively connected to the data transfer request signals of / DREQ0, / DREQ1, and / DREQ2. In other words, a register 217 for storing device information indicating which interface is connected to each of the interfaces is added to the computer system (in this embodiment, a multi-function peripheral). By doing so, the register 217 stores the information. By changing the device information setting from the outside, data transfer (DMA) between the buses corresponding to each system configuration can be controlled. Therefore, it is not necessary to design and manufacture a gate array for each system. Therefore, it is possible to provide a highly versatile gate array with excellent man-hours and costs, and a computer system including such a gate array.

  In the above-described embodiment, in response to the data transfer request signal, which bus is connected to the transfer source device and the transfer destination device, that is, which interface is connected to each. In the above description, the register 217 for storing the device information is built in the gate array 21, but it may be provided outside the gate array. In such a case, the gate array and the register are connected to the signal line. And the device information stored in the register may be acquired.

  In the above-described embodiment, there are three devices that perform data transfer by DMA, such as the modem 23, the print codec 34, and the read codec 39. However, this is merely an example, and a larger or smaller number of devices. It goes without saying that data transfer by DMA can also be handled by configuring a gate array according to the number of devices.

  Furthermore, in the above-described embodiment, the register 217 is a software rewritable device, and the device information is read from the ROM 12 when the power is turned on and written into the register 217 under the control of the MPU 11. The register 217 may be a hardware writable device such as a fuse ROM or an EEPROM, and device information is written by a ROM writer or the like according to the configuration of the device of the computer system (multifunction device in the embodiment) and the bus. Such a form may be sufficient.

  Furthermore, in the above-described embodiment, each signal is low active (significant when low), but each signal may be high active (significant when high), It is not necessary that all signals be unified as either low active or high active.

1 is a block diagram illustrating an internal configuration example of a multifunction peripheral as an embodiment of a computer system of the present invention. FIG. It is a block diagram which shows the example of a gate array structure which is an electronic circuit of the computer system of this invention.

Explanation of symbols

11 MPU
12 ROM
20 System bus 21 Gate array 22 SDRAM
23 Modem 30 Local Bus 34 Codec for Printing 39 Codec for Reading 50 Panel Bus 211 System Bus I / F
214 Local bus I / F
215 DMAC
217 registers

Claims (4)

A plurality of buses including a single bus to which a processor is connected; a plurality of devices connected to any of the plurality of buses; and the processor intervening based on a data transfer request signal output from each device. A computer system comprising an inter-bus control unit that controls data transfer between the buses,
The inter-bus controller includes a direct memory access controller,
Storage means for storing device information indicating which of the plurality of buses each device is connected to;
A computer system characterized in that, based on device information stored in the storage means, a data access control is performed by setting a bus for direct memory access to a connected state. The inter-bus control unit includes an internal bus and a plurality of interfaces that connect the plurality of buses via the internal bus,
The direct memory access controller, based on the device information stored in the storage means, is connected to each interface connected to each bus to which a data transfer source device and a data transfer destination device are connected. The computer system according to claim 1, further comprising means for granting a bus occupation right of the bus.   3. The computer system according to claim 1, wherein the device information stored in the storage unit is rewritable from the outside. An electronic circuit of a computer system comprising an internal bus, a plurality of interfaces connected via the internal bus, and a direct memory access controller, and for controlling data transfer between the buses,
An electronic circuit of a computer system, comprising: a storage unit that stores information designating which interface occupies the internal bus based on a data transfer request signal input from the outside.

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