JP2002024159A - Controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a controller capable of updating a system program by operating a CPU on the side of a CPU bus on the basis of a new system program stored in an external memory even when connecting a connecting part capable of connecting the relevant external memory storing the new system program for update to the side of a DMA bus. SOLUTION: The external memory connecting part is connected to the DMA bus and on the other hand, an access control means is provided for controlling access from the CPU to the external memory on the DMA bus. The CPU updates the relevant system program by writing it in an internal memory on the CPU bus on the basis of the system program stored in the relevant external memory by accessing the external memory on the DMA bus through the access control means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a control device applicable to control of facsimile communication, data communication and the like.

[0002]

2. Description of the Related Art A system program is stored in a rewritable internal memory such as a flash memory, and the CPU accesses the memory via a CPU bus to read and execute the system program, thereby performing a predetermined control process. In a control device such as a device, the system program stored in its internal memory is updated to a new system program stored in an external memory connected to the device in the form of an IC card or the like in order to correct a defect or improve a function. You may need to.

However, since the CPU cannot perform a rewriting operation based on the old system program in the internal memory that is being rewritten with the new system program for updating, the CPU cannot perform the rewriting operation based on the new system program stored in the external memory. A rewrite operation needs to be performed.

On the other hand, the control device has a DMA bus in addition to the CPU bus accessed by the CPU.
Some devices are also equipped with such a DMA bus to increase the speed of data transfer. For example, an IC card with a built-in external memory for function expansion such as an optional large-capacity storage memory or a hard disk is used as a DMA bus. Some are connected to the side.

[0005]

In the case of such an IC card connected to the DMA bus, even if an external memory storing a system program is connected to a control device to update the system program, The CPU on the CPU bus cannot access and read the system program stored in the external memory on the DMA bus and perform a control operation based on the system program. Therefore, in order to connect an external memory storing a system program in the form of an IC card to the control device and update the system program in the internal memory, C
IC for updating system program on PU bus side
Since the connector for connecting the card must be mounted, the connector for the IC card needs to be mounted on both the DMA bus and the CPU bus, and there is a problem that the device cost is increased.

The present invention has been made in view of the above circumstances, and even when a connection unit capable of connecting an external memory storing a new system program for updating is connected to the DMA bus side, the CPU on the CPU bus side. It is an object of the present invention to provide a control device that can operate based on a new system program stored in the external memory and update the system program.

[0007]

According to a first aspect of the present invention, there is provided a control device wherein a CPU accesses a rewritable internal memory storing a system program via a CPU bus and stores the system program in the internal memory. While the CPU performs predetermined control processing based on the above, the CPU accesses the external memory connected to the external memory connection unit and executes the system program stored in the external memory based on the system program stored in the external memory. In a control device for writing to the internal memory and updating a system program stored in the internal memory, the external memory connection unit is connected to a DMA bus, and the external memory on the DMA bus is controlled by the CPU. An access control means for controlling access to the external memory connected to the connection unit The CPU accesses the external memory connected to the external memory connection unit on the DMA bus via the access control means when the system program is updated, and updates the system program stored in the external memory. And updating the system program by writing the system program to the internal memory on the CPU bus.

According to a second aspect of the present invention, in the control device, a rewritable internal memory storing a system program is stored in a CP.
U performs predetermined control processing based on a system program stored in the internal memory by accessing via the CPU bus, while the CPU accesses an external memory connected to the external memory connection unit and A controller that writes a system program stored in the external memory to the internal memory based on the system program stored in the internal memory and updates the system program stored in the internal memory; The external memory to be transferred to the DMA bus or the CP
A setting terminal for selecting and setting which of the U buses to connect to, and the external memory connected to the external memory connection unit connected to the CPU bus or the DMA bus according to the setting by the setting terminal. Access control means for controlling access from the CPU to control access to the external memory by the CPU;
When updating the system program, the PU accesses the external memory via the access control means and writes the system program to the internal memory on the CPU bus based on the system program stored in the external memory. It is characterized in that the system program is updated.

According to a third aspect of the present invention, in the control device, a rewritable internal memory storing a system program is stored in a CP.
U performs predetermined control processing based on a system program stored in the internal memory by accessing via the CPU bus, while the CPU accesses an external memory connected to the external memory connection unit and A controller that writes a system program stored in the external memory to the internal memory based on the system program stored in the internal memory and updates the system program stored in the internal memory; The external memory to be transferred to the DMA bus or the CP
A setting register for setting and storing which of the U buses to connect to in accordance with an instruction from the CPU, and an external memory connection unit connected to the CPU bus or DMA bus in accordance with the setting of the setting register. Access control means for controlling access to the external memory connected to the external memory by the CPU and controlling access to the external memory by the CPU; The memory is accessed via the access control means, and the system program is updated by writing the system program to the internal memory on the CPU bus based on the system program stored in the external memory.

[0010]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
An embodiment of the present invention will be described in detail by dividing into first, second and third embodiments.

First, FIG. 1 shows a block configuration of a facsimile apparatus 100 as a control apparatus according to the first embodiment, and FIG. 2 shows a block configuration of a chip select control unit 12 of the facsimile apparatus 100 according to the first embodiment. Show.

In the facsimile apparatus 100 shown in FIG. 1, a CPU 1 is a microcomputer which controls the entire apparatus according to a system program stored in an internal flash memory 2 which is an electrically rewritable read-only memory.

The internal flash memory 2 is accessed and read by the CPU 1 via the CPU bus 5, and stores a system program for controlling the entire apparatus.

The RAM 3 is connected to the CPU bus 5 and
A random access memory used for a stack area, a work area of the system, and the like, which is necessary when the PU 1 performs a control operation according to a system program stored in the internal flash memory 2.

The CPU bus I / O is an I / O that is connected to the CPU bus 5 and exchanges data with the CPU 1. For example, it consists of various keys required for transmission, reception, copy, an operation unit with switches, a network control unit and a communication control unit,
Blocks such as an NCU that performs these controls and that transfer relatively small amounts of data are connected to blocks that require immediacy.

The CPU bus 5 is a signal line for transferring data to and from each unit connected to the CPU 1.

The DMAC 6 is a controller that controls data transfer without passing through the CPU. Normal DMA
In the transfer, the block on the DMA bus 9 cannot be accessed from the CPU 1 on the CPU bus 5 side. However, in the first embodiment and second and third embodiments described later, the CPU 1
However, each block on the DMA bus 9 can be accessed.

The RAM 7 is directly accessed by the DMAC 6 and exchanges data with each DMA bus I / O 8.

The DMA bus I / O 8 is an I / O connected to the DMA bus 9. For example, a scanner unit that optically scans a document and encodes the image information, and compresses / compresses the image information. Blocks for transferring a large amount of data, such as an image processing unit for performing expansion and a plotter unit for physically converting image data from a transmission destination via the image processing unit, are connected.

The DMA bus 9 is a signal line for exchanging data with each unit connected to the DMAC 6.

An IC card connector 10 serving as an external memory connection unit is a connector for mounting an IC card, and is connected to the DMA bus 9 in the first embodiment.

The IC card connector 10 can be mounted with an IC card mounted with an external memory according to various purposes. For example, a flash memory storing a function expansion program, a card mounted with a RAM, A RAM card that stores registration data and the like, a hard disk card that stores a large amount of data such as image information, and the like are mounted.

The first embodiment and second and third embodiments to be described later
In the embodiment, the flash card 11 in which the new system program for updating the system program stored in the internal flash memory 2 is stored in the external flash memory 11a built in is attached to the IC card connector 10.

The chip select control unit 12 has a specific configuration shown in FIG. 2. In FIG. 2, the chip select control unit 12 includes a DMA bus address decoder 13 and a CP.
U bus address decoder 14 and DMAC controller 1
5.

The DMA bus address decoder 13 has a
The address generated by the AC 6 is decoded to generate an external flash memory CS which is a chip select signal of the external flash memory 11 a in the flash guard 11.

The CPU bus address decoder 14 has a CP
The address generated by U1 is decoded to generate a CPU bus CS which is a selection signal for the external flash memory 11a in the flash card 11.

When the CPU bus CS signal is asserted, the DMAC control unit 15 asserts a CPU wait signal to the CPU 1 and asserts a DMA bus request signal to the DMAC 6. Then, when the DMA bus permission signal is asserted from the DMAC 6, the CPU wait signal and the DMA bus request signal are negated.

In the first embodiment having the above configuration, the CPU 1
Performs a program fetch from the internal flash memory 2 to control each unit of the apparatus. When a system program update request is made from an operation unit or the like connected to the CPU bus I / O 4, the IC card connector 10 Jump to a predetermined address of the external flash memory 11a built in the connected flash card 11a.

Here, in the first embodiment, the CPU 1
The operation of each unit when the user accesses the external flash memory 11a for updating the system program will be described.

When the CPU 1 outputs the address of the external flash memory 11a, the CPU bus address decoder 14 in the chip select control unit 12 asserts a CPU bus CS signal which is a selection signal of the external flash memory 11a.

When the CPU bus CS signal is asserted, the DMAC control unit 15 asserts a CPU wait signal to the CPU 1 and a DMAC signal to the DMAC 6.
Assert the bus request signal.

When the CPU wait signal is asserted, the CPU 1 inserts a wait in the bus cycle.

When the DMA bus request signal is asserted, the DMAC 6 performs bus arbitration, and
When the bus 9 becomes available, it asserts a DMA bus permission signal. At this time, the DMAC 6 outputs the address generated by the CPU 1 to the DMA bus 9, and the DMA bus address decoder 13 asserts the external flash memory CS. The DMAC 6 generates a strobe signal together with the chip select signal, and outputs the strobe signal to the external flash memory 11a.
To access.

When the DMA bus control signal is asserted, the DMAC controller 15 negates the wait signal and the DMA bus request signal.

On the other hand, when the wait signal is negated, the CPU 1 reads data from the external flash memory 11a via the DMAC 6.

The CPU 1 repeats the above operation, fetches a program from the external flash memory 11a, and copies the system program stored in the external flash memory 11a to the internal flash memory 2.

When the copying of the system program is completed, the CPU 1 returns to the predetermined address of the internal flash memory 2 and ends the updating of the system program.

As described above, in the first embodiment, the CPU 1 on the CPU bus 5 accesses the external flash memory 11a on the DMA bus 9 and operates according to the new system program stored in the external flash memory 11a. With the new system program, the old system program stored in the internal flash memory 2 can be updated.

Next, the block configuration of the facsimile apparatus 100 according to the second and third embodiments is shown in FIG.
FIG. 4 shows a block configuration of the chip select control unit 12 of the facsimile apparatus 100 according to the second embodiment, and FIG. 5 shows a block configuration of the chip select control unit 12 of the facsimile apparatus 100 according to the third embodiment.

The facsimile apparatus 100 according to the second and third embodiments shown in FIG. 3 is different from the facsimile apparatus 100 according to the first embodiment shown in FIG. In the second embodiment, the IC card connector 10 to which the IC card 11 is connected can be selectively assigned to either the DMA bus 9 or the CPU bus 5, and the chip select control unit 12 has the configuration shown in FIG. The third embodiment has the same configuration as the facsimile apparatus 100 according to the first embodiment shown in FIG. 1 except that it is configured as shown in FIG.

The chip select control unit 12 according to the second embodiment shown in FIG.
CPU bus address decoder 14, DMAC controller 1
5, a multiplexer 16, and a setting terminal 17.

The DMA bus address decoder 13 outputs
The address generated by the AC 6 is decoded, and a DMA bus CS, which is a chip select signal of the external flash memory 11a in the flash guard 11, is generated.

The CPU bus address decoder 14 has a CP
The address generated by U1 is decoded to generate a CPU bus CS which is a selection signal for the external flash memory 11a in the flash card 11.

When the CPU bus CS signal is asserted, the DMAC controller 15 asserts a CPU wait signal to the CPU 1 and asserts a DMA bus request signal to the DMAC 6. Then, when the DMA bus permission signal is asserted from the DMAC 6, the CPU wait signal and the DMA bus request signal are negated.

The multiplexer 16 multiplexes the DMA bus CS and the CPU bus CS, and sets
, The external flash memory CS which is a chip select signal of the external flash memory 11a is generated. The setting terminal 17 is a terminal for setting whether the external flash memory 11a in the flash card 11 connected to the IC card connector 10 is connected to the CPU bus 5 or the DMA bus 8. is there.

In the second embodiment having the above configuration, the CPU 1
Performs a program fetch from the internal flash memory 2 to control each unit of the apparatus. When a system program update request is made from an operation unit or the like connected to the CPU bus I / O 4, the IC card connector 10 Jump to a predetermined address of the external flash memory 11a built in the connected flash card 11a.

Here, in the second embodiment, the CPU 1
The operation of each unit when the user accesses the external flash memory 11a for updating the system program will be described.

The operation in this case includes a case where the IC card connector 10 is allocated to the DMA bus 9 and a case where the IC card connector 10 is allocated to the CPU bus 5 by setting the setting terminal 17.

First, the case of assignment to the DMA bus 9 will be described.

When the CPU 1 outputs the address of the external flash memory 11a, the CPU bus address decoder 14 in the chip select control section 12 asserts a CPU bus CS signal which is a selection signal of the external flash memory 11a.

When the CPU bus CS signal is asserted, the DMAC control unit 15 asserts a CPU wait signal to the CPU 1 and a DMAC signal to the DMAC 6.
Assert the bus request signal.

When the CPU wait signal is asserted, the CPU 1 inserts a wait in the bus cycle.

When the DMA bus request signal is asserted, the DMAC 6 performs bus arbitration, and
When the bus 9 becomes available, it asserts a DMA bus permission signal. At this time, the DMAC 6 outputs the address generated by the CPU 1 to the DMA bus 9, and the DMA bus address decoder 13 asserts the external flash memory CS. The multiplexer 16 outputs a DMA bus CS as an external flash memory CS signal in accordance with the setting of the setting terminal 17.
Output a signal. The DMAC 6 generates a strobe signal at the timing of the external flash memory CS signal,
Access the external flash memory 11a.

When the DMA bus control signal is asserted, the DMAC control unit 15 negates the wait signal and the DMA bus request signal.

On the other hand, when the wait signal is negated, the CPU 1 reads data from the external flash memory 11a via the DMAC 6.

The CPU 1 repeats the above operation, fetches a program from the external flash memory 11a, and copies the system program stored in the external flash memory 11a to the internal flash memory 2.

When the copying of the system program is completed, the CPU 1 returns to the predetermined address of the internal flash memory 2 and ends the updating of the system program.

Next, a case where the IC card connector 10 is allocated to the CPU bus 5 by setting the setting terminal 17 will be described.

When the CPU 1 outputs the address of the external flash memory 11a, the CPU bus address decoder 14 in the chip select control section 12 asserts a CPU bus CS signal which is a selection signal of the external flash memory 11a.

When the CPU bus CS is asserted, the multiplexer 16 outputs the CPU bus CS as the external flash memory CS according to the setting of the setting terminal 17. C
The PU1 generates a strobe signal at the timing of the external flash memory CS and accesses the external flash memory 11a.

The CPU 1 repeats the above operation, fetches a program from the external flash memory 11a, and copies the system program stored in the external flash memory 11a to the internal flash memory 2.

When the copying of the system program is completed, the CPU 1 returns to a predetermined address of the internal flash memory 2 and ends the updating of the system program.

The chip select control unit 12 according to the third embodiment shown in FIG.
CPU bus address decoder 14, DMAC controller 1
5, a multiplexer 16, and a setting register 18.

The DMA bus address decoder 13 outputs
The address generated by the AC 6 is decoded, and a DMA bus CS, which is a chip select signal of the external flash memory 11a in the flash guard 11, is generated.

The CPU bus address decoder 14 has a CP
The address generated by U1 is decoded to generate a CPU bus CS which is a selection signal for the external flash memory 11a in the flash card 11.

When the CPU bus CS signal is asserted, the DMAC controller 15 asserts a CPU wait signal to the CPU 1 and asserts a DMA bus request signal to the DMAC 6. Then, when the DMA bus permission signal is asserted from the DMAC 6, the CPU wait signal and the DMA bus request signal are negated.

The multiplexer 16 multiplexes the DMA bus CS and the CPU bus CS, and generates an external flash memory CS which is a chip select signal of the external flash memory 11a according to the setting of the setting register 18. The setting register 18 determines whether the external flash memory 11a in the flash card 11 connected to the IC card connector 10 is connected to the CPU bus 5 or not.
A register for setting whether or not to be connected to the MA bus 8, which is accessed and set by the CPU 1.

In the third embodiment having the above configuration, the CPU 1
Performs a program fetch from the internal flash memory 2 to control each unit of the apparatus. When a system program update request is made from an operation unit or the like connected to the CPU bus I / O 4, the IC card connector 10 Jump to a predetermined address of the external flash memory 11a built in the connected flash card 11a.

Here, in the third embodiment, the CPU 1
The operation of each unit when the user accesses the external flash memory 11a for updating the system program will be described.

The operation in that case is as follows.
8, the IC card connector 10 is connected to the DMA bus 9
And may be assigned to the CPU bus 5.

First, the case where the data is allocated to the DMA bus 9 will be described.

When the CPU 1 outputs the address of the external flash memory 11a, the CPU bus address decoder 14 in the chip select control unit 12 asserts a CPU bus CS signal which is a selection signal of the external flash memory 11a.

When the CPU bus CS signal is asserted, the DMAC control unit 15 asserts a CPU wait signal to the CPU 1 and a DMAC signal to the DMAC 6.
Assert the bus request signal.

When the CPU wait signal is asserted, CPU 1 inserts a wait in the bus cycle.

When the DMA bus request signal is asserted, the DMAC 6 performs bus arbitration, and
When the bus 9 becomes available, it asserts a DMA bus permission signal. At this time, the DMAC 6 outputs the address generated by the CPU 1 to the DMA bus 9, and the DMA bus address decoder 13 asserts the external flash memory CS. The multiplexer 16 outputs a DMA bus CS signal as an external flash memory CS signal according to the setting of the setting register 18. The DMAC 6 generates a strobe signal at the timing of the external flash memory CS signal and accesses the external flash memory 11a.

When the DMA bus control signal is asserted, the DMAC control unit 15 negates the wait signal and the DMA bus request signal.

On the other hand, when the wait signal is negated, the CPU 1 reads the data in the external flash memory 11a via the DMAC 6.

The CPU 1 repeats the above operation, fetches a program from the external flash memory 11a, and copies the system program stored in the external flash memory 11a to the internal flash memory 2.

When the copying of the system program is completed, the CPU 1 returns to a predetermined address in the internal flash memory 2 and ends the updating of the system program.

Next, by setting the setting register 18, the IC
The case where the card connector 10 is allocated to the CPU bus 5 will be described.

When the CPU 1 outputs the address of the external flash memory 11a, the CPU bus address decoder 14 in the chip select control unit 12 asserts a CPU bus CS signal which is a selection signal of the external flash memory 11a.

When the CPU bus CS is asserted, the multiplexer 16 outputs the CPU bus CS as the external flash memory CS according to the setting of the setting register 18. The CPU 1 generates a strobe signal at the timing of the external flash memory CS,
Access 1a.

The CPU 1 repeats the above operation, fetches a program from the external flash memory 11a, and copies the system program stored in the external flash memory 11a to the internal flash memory 2.

When the copying of the system program is completed, the CPU 1 returns to the predetermined address of the internal flash memory 2 and ends the updating of the system program.

As described above, according to the second or third embodiment, the IC card connector 10 as an external memory connection portion
The system program can be rewritten regardless of whether the device is connected to the DMA bus 9 or the CPU bus 5, and even if the connection destination bus of the IC card connector 10 is different for each model, the system circuit can be flexibly updated with the same circuit configuration. Can respond.

In the above-described embodiment, the control device according to the present invention is applied to control of a facsimile machine. However, the present invention is not limited by the control contents, and other various control devices may be used. Is similarly applicable.

[0087]

According to the first aspect of the present invention, an external memory for rewriting a system program is connected.
Even in a system in which an external memory connection unit such as an IC card connector is mounted on a DMA bus, the system program can be updated by an external memory connected to the external memory connection unit. Therefore, there is no need to mount a wasteful IC card connector or the like, and the effect that the cost of the apparatus can be reduced can be obtained.

According to the second aspect of the present invention, whether the external memory is connected to the CPU bus or the DMA bus, the system program can be rewritten by the external memory by setting the setting terminal. Therefore, it is possible to cope with the update of the system program with the same circuit configuration without changing the circuit configuration for each model, and it is possible to reduce the apparatus cost.

According to the third aspect of the present invention, whether the external memory is connected to the CPU bus or the DMA bus, the system program is rewritten by the external memory by setting the setting register. Therefore, it is possible to cope with the update of the system program with the same circuit configuration without changing the circuit configuration for each model, and it is possible to reduce the apparatus cost.

[Brief description of the drawings]

FIG. 1 is a diagram showing a block configuration according to a first embodiment of a facsimile machine as a control device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a block configuration of a chip select control unit of the facsimile apparatus according to the first embodiment.

FIG. 3 is a diagram showing a block configuration according to second and third embodiments of a facsimile apparatus as a control apparatus according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating a block configuration of a chip select control unit of the facsimile apparatus according to the second embodiment.

FIG. 5 is a diagram illustrating a block configuration of a chip select control unit of a facsimile apparatus according to a third embodiment.

[Explanation of symbols]

 Reference Signs List 1 CPU 2 Internal flash memory 3 RAM 4 CPU bus I / O group 5 CPU bus 6 DMAC 7 RAM 8 DMA bus I / O group 9 DMA bus 10 IC card connector 11 Flash card 11a External flash memory 12 Chip select control unit 13 DMA Bus address decoder 14 CPU bus address decoder 15 DMAC controller 16 multiplexer 17 setting terminal 18 setting register

Claims (3)

[Claims] 1. A CPU accesses a rewritable internal memory in which a system program is stored via a CPU bus, and performs predetermined control processing based on the system program stored in the internal memory. A system in which an external memory connected to an external memory connection unit is accessed, and a system program stored in the external memory is written to the internal memory based on the system program stored in the external memory and stored in the internal memory. In the control device for performing a program update process, the external memory connection unit is connected to a DMA bus,
An access control unit for controlling access to the external memory connected to the external memory connection unit on the DMA bus by the CPU, wherein the CPU updates the external program on the DMA bus when a system program is updated. An external memory connected to a memory connection unit is accessed via the access control means, and based on the system program stored in the external memory, the system program is written to the internal memory on the CPU bus to execute the system program. A control device characterized by updating. 2. A CPU accesses a rewritable internal memory in which a system program is stored via a CPU bus, and performs predetermined control processing based on the system program stored in the internal memory. A system in which an external memory connected to an external memory connection unit is accessed, and a system program stored in the external memory is written to the internal memory based on the system program stored in the external memory and stored in the internal memory. In a control device for performing a program update process, an external memory connected to the external memory connection unit is set to a DMA.
A setting terminal for selectively setting the connection to the bus or the CPU bus, and the external memory connected to the external memory connection unit connected to the CPU bus or the DMA bus according to the setting by the setting terminal By controlling access from the CPU to the
An access control unit for controlling access to the external memory, wherein the CPU accesses the external memory via the access control unit and updates the system program stored in the external memory when the system program is updated. The system program based on the CPU
A control device for updating a system program by writing to the internal memory on a bus. 3. A CPU accesses a rewritable internal memory in which a system program is stored via a CPU bus, and performs predetermined control processing based on the system program stored in the internal memory. A system in which an external memory connected to an external memory connection unit is accessed, and a system program stored in the external memory is written to the internal memory based on the system program stored in the external memory and stored in the internal memory. In a control device for performing a program update process, an external memory connected to the external memory connection unit is set to a DMA.
A setting register for setting and storing which of the bus and the CPU bus to connect to in accordance with an instruction from the CPU, and the external memory connected to the CPU bus or the DMA bus in accordance with the setting of the setting register An access control unit for controlling access from the CPU to the external memory connected to the connection unit, and controlling access to the external memory by the CPU;
When updating the system program, the PU accesses the external memory via the access control means and writes the system program to the internal memory on the CPU bus based on the system program stored in the external memory. A control device for updating a system program.