JP2000013639A - Image signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an output image from being unpleasant to look at even in the case of a system that has different frame rates between input and output. SOLUTION: A frame memory 9 has an address control circuit which has capacity for plural images and outputs an address to store image data in the memory 9 or to read it so as to prevent output data passing. The memory 9 has an address control circuit 8 which has capacity for plural images and outputs an address to store image data in the memory 9 or to read it so as to prevent input data passing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal processing apparatus suitable for preventing overtaking in an output screen when a liquid crystal projector has different input / output frame rates.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram around a frame memory for converting an input frame rate and an output frame rate.

The data flow will be described. As shown in FIG. 4, image data output from an A / D converter 1 is temporarily stored in an input buffer 2 and is written by an address control block 5 to write data 6 for one screen. The data is written to the frame memory 3 having a capacity.

At this time, data is written into the frame memory 3 at a timing according to the input frame rate.

On the other hand, output data is read from the frame memory 3 by a read address 7 output from the address control block 5.

At this time, data is read from the frame memory 3 at a timing according to the output frame rate.

When the output frame rate is higher than the input frame rate, as shown in FIG. 5, after the input data of the M frame N line indicated by the write address is written, the output data becomes the output data of the M frame N line indicated by the read address. , And the output data of line M + 1 of the frame should be read out. However, since no input data is written, the output data of line N + 1 of the frame M-1 is read out, and the output data is overtaken in the screen. .

When the input frame rate is higher than the output frame rate, as shown in FIG. 6, after reading the output data of the M frame N lines indicated by the read address, the input data is changed to the M + 1 frame N lines indicated by the write address, and M + 1 When writing the input data of the frame N + 1 line and then reading the output data, the output data of the M frame N + 1 line should be read, but the M + 1 frame N + 1 line data is read, and the input data Overtaking occurs.

[0009]

As described above, in the prior art, in a system having different frame rates for input and output, overtaking occurs in the screen, resulting in a very unsightly screen.

An object of the present invention is to prevent an output screen from becoming unsightly even in a system having different frame rates for input and output.

[0011]

According to a first aspect of the present invention, a frame memory having a data capacity of two screens and having two first and second memory areas, and input frame data are firstly stored. The first memory area is written, the second memory area is written later, and the output data is read out from the first memory area first, read out from the second memory area later, and the output frame is output from the input frame rate. When the rate is high, after the reading of the previous frame data stored in the second memory area is completed,
When reading the current frame data of the memory area of the above, it is determined that the input current frame data is to be overtaken in the first memory area in consideration of the value of the input data write address being written to the first memory area. And an address control unit for controlling output data to read previous frame data in the second memory area.

According to a second aspect of the present invention, a frame memory having a data capacity of two screens and having two first and second memory areas, and input frame data are first stored in the first memory area. , Later written to the second memory area, the output data is first read from the first memory area, later read from the second memory area, and when the input frame rate is higher than the output frame rate, After reading certain line data of the current frame data stored in the first memory area,
When starting to write frame data one after another in the memory area of the first memory area, it is determined whether or not the input data overtakes the output data in the first memory area. , And an address control unit for controlling writing of the frame data one after another to the first memory area.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG.
Has a data capacity of two screens. As shown in FIG. 2, it is assumed that the memory area therein is divided into A and B halves, each of which can hold data for one screen.

The address control unit 8 controls the address so that the input frame data is written in the order of the memory areas A and B. The address control unit controls the address so that the output data is read from the memory areas A and B in order.

When the output frame rate is higher than the input frame rate, as shown in FIG. 1, the output data finishes reading the M-1 frame data in the B area, and then, when reading the M frame data in the A area, the output data is written in the A area. Considering the value of the input data write address in the area, if the input M frame data is overtaken in the area A, the address control unit 8
If the judgment is made in step (1), M-1 frame data in the B area is read again as output data.

With this control, it is possible to prevent the output data from overtaking in the screen when the output frame rate is higher than the input frame rate, so that the output screen does not become unsightly.

When the input frame rate is higher than the output frame rate, as shown in FIG. 3, after the output data reads M frame N line data in the A area, the input data starts writing M + 2 frame data in the A area ( The M + 1 frame data has already been written in the B area), and the address control unit 8 determines whether the input data overtakes the output data in the A area, and if it determines that it overtakes, stops writing the subsequent M + 2 frame data. I do.

Then, writing to the area A is started again from the M + 3 frame data.

With this control, it is possible to prevent the overtaking of input data in the screen, which occurs when the input frame rate is higher than the output frame rate, so that the output screen does not become unsightly.

[0020]

According to the present invention, in a frame memory having a capacity of a plurality of screens, when input frame data is sequentially written in different areas in the frame memory, when the output frame rate is higher than the input frame rate, the frame rate of the frame is increased. When the first data is read, if it is determined that the output data reading will overtake the input data writing in the same frame memory area, the currently read frame data is read again to prevent the overtaking in the screen.

When it is determined that the input frame data exceeds the output frame data in the same frame memory area when the input frame rate is higher than the output frame rate,
Writing is stopped, and writing is started again from the next frame data in the same frame memory area so that no overtaking occurs in the screen.

Thus, a buffer for a plurality of frames is provided in the frame memory, and overtaking in the screen can be prevented by the overtaking determination address control of the input / output data.

[Brief description of the drawings]

FIG. 1 is a block diagram of the present invention.

FIG. 2 is a diagram showing a frame memory when passing output data according to the present invention.

FIG. 3 is a diagram showing a frame memory when passing input data according to the present invention.

FIG. 4 shows a block diagram of the prior art.

FIG. 5 is a diagram showing a frame memory at the time of overtaking output data according to the related art.

FIG. 6 is a diagram showing a frame memory when passing input data according to the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 A / D converter 2 Input buffer 3 Frame memory 4 Output buffer 5 Address control part 6 Write address 7 Read address

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 5/12 G09G 5/12 H04N 5/073 H04N 5/073 B F-term (Reference) 5C006 AF02 AF03 AF04 AF06 AF07 AF23 AF44 BB11 BC16 BF02 EC11 FA08 5C020 AA14 5C021 PA58 PA62 PA79 YC04 5C080 AA10 BB05 DD01 EE19 JJ02 JJ05 5C082 AA02 BA20 BB26 BC03 BC19 BD02 CA81 CA84 CA85 CB01 DA54 DA55 DA57 DA06 DA65 MM67

Claims (2)

[Claims] 1. A frame memory having a data capacity of two screens and having two first and second memory areas, and input frame data are first written into the first memory area, Writing to a second memory area, output data is first read from the first memory area, later read from the second memory area, and when the output frame rate is higher than the input frame rate, the second memory area After reading the previous frame data stored in the first memory area, when reading the current frame data of the first memory area next, the value of the input data write address being written to the first memory area is considered, If it is determined that the input current frame data is to be overtaken in the first memory area, the output data reads the previous frame data in the second memory area. Image signal processing device including an address controller for controlling the Suyo. 2. A frame memory having a data capacity of two screens and having two first and second memory areas, and input frame data are written into the first memory area first, Writing to a second memory area, output data is first read from the first memory area, later read from the second memory area, and when the input frame rate is higher than the output frame rate, the first memory area After reading out certain line data of the current frame data stored in the first memory area, when starting to write frame data one after another in the first memory area, whether the input data overtakes the output data in the first memory area. If it is determined that it is overtaken, the subsequent writing of subsequent frame data is stopped, and the first frame data is returned from the successive frame data. Image signal processing device including an address controller for controlling to start writing to the memory area.