JP2982611B2 - Image processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for inputting image data from an image data input device such as a scanner or a storage device such as a semiconductor memory, performing predetermined processing on the input image data, and outputting the result. The present invention relates to an image data output device such as a printer or an image processing device for outputting to a storage device such as a magnetic disk device or a semiconductor memory.

[0002]

2. Description of the Related Art With the spread of workstations and digital copiers, digital image data processing methods have been diversified, and the processing speed has been increasing at the same time. In an image processing apparatus in which coordinate data of an original image is stored, such as shading correction and gradation correction, for example, the image processing apparatus can be inserted in the middle of the flow of image data between a scanner and a printer. On the other hand, in an image processing apparatus in which input data is converted into a data structure having a different data structure, such as data compression, or where coordinate data of an original image is not stored, such as in a rotation process, a storage medium such as a magnetic disk device or a semiconductor memory is used. The image data temporarily stored in the device is input, and the processing result is output to the storage device for temporarily storing the processing result. Generally, since image data has a large capacity, an inexpensive storage device is used.
M (DRAM) is often used. However, inexpensive storage devices require a long data access time, making high-speed processing difficult.

As an example of means for solving this problem, as disclosed in Japanese Patent Application Laid-Open No. 3-261575, data handled by an image processing apparatus is exchanged with the outside via a first-in first-out (FIFO) memory. There is something that is. In this prior art, the input FI
By providing the FO memory and the output FIFO memory simultaneously in one image processing apparatus, it is possible to perform the image processing at the highest speed regardless of the external data processing speed.

[0004]

As the system becomes more complicated, the storage device and the like are designed to be shared, and the storage device connected to one image processing apparatus is shared with other devices. become. Then, when the image processing apparatus reads and writes data from the storage device, the access is arbitrated with the access to the storage device of another device, and the data cannot be read / written at a desired timing. In such a case, the desired image data is
Despite not being written to IFO memory, FI
Performs a read operation from the FO memory,
FI even though there is no room to write data to memory
A write operation is performed on the FO memory.
In the prior art, this point is not sufficiently taken into consideration, and measures have been taken by increasing the capacity of the FIFO memory in the input / output stage.

The present invention has been made in view of such circumstances, and even in a system in which input of image data or output of a processing result is not performed at a desired timing, an input FIFO memory and an output FIFO memory can be used. It is an object of the present invention to provide an apparatus capable of performing image processing favorably without increasing the capacity of a FIFO memory for use.

[0006]

In order to achieve the above object, the present invention provides an input FIFO memory for temporarily storing input data to be processed, reading image data from the input FIFO memory and performing image processing on the image data. An image processing unit having latch means for holding an intermediate result of processing, an output FIFO memory for temporarily storing output data of a processing result in the image processing unit, an input FIFO memory, and an output FIFO
A control unit that detects the state of the memory and controls the operation of the image processing unit, wherein the control unit controls the latch operation of the latch unit based on the states of the input FIFO memory and the output FIFO memory. I do.

[0007]

According to the present invention, a FIFO memory is provided in each of the input / output stages, and the image processing operation is controlled in accordance with the state of the input FIFO memory and the state of the output FIFO memory.
Since the latch means for controlling the latch operation based on the state of the memory and the output FIFO memory and holding the intermediate result of the image processing is provided, the input or output side is remarkably compared with the operation speed of the image processing section. Even if the data transfer speed is different, the image processing result is not lost.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic configuration diagram of the present invention. Image data VD to be processed is first stored in the input FIFO memory 1. By reading the image data from the input FIFO memory 1, the data is taken into the image processing unit 3. The image processing unit 3 is a circuit that performs a predetermined operation on input image data, and performs, for example, filter processing, orthogonal transformation processing, image rotation, image compression / decompression processing, and the like. Here, the description will be made assuming that the image processing unit 3 performs an image compression process. The result processed by the image processing unit 3 is temporarily written to the output FIFO memory 2, and the processing result ODATA can be read from the output FIFO memory 2 at an arbitrary time from outside.

The input FIFO status information 5 and the output FI shown in FIG.
The FO state information 6 indicates a state where each FIFO memory is full of data that has not been read (hereinafter simply referred to as full) or a state where no new data has been written to the FIFO memory (hereinafter simply referred to as empty). It is a signal to represent. The control circuit 4 outputs a control signal 7 for performing control such as stopping or restarting the operation of the image processing unit 3 according to the input FIFO state information 5 and the output FIFO state information 6. When the input FIFO memory 1 is in the empty state, there is no data to be processed by the image processing unit 3, and if the operation of the image processing unit 3 is continued at this time, invalid data is fetched and the processing is continued. Therefore, when the input FIFO state information 5 indicates an empty state, the control circuit 4 outputs a control signal 7 for stopping the image processing unit 3 so as not to take in invalid data into the image processing unit 3. Also,
When the output FIFO memory 2 is full, the image processing unit 3
Cannot be written to the output FIFO memory 2, and even if new processed data is generated from the image processing unit 3 after this point, it cannot be temporarily stored. Therefore, when the output FIFO state information 6 indicates the full state, the control circuit 4 outputs a control signal 7 for stopping the image processing unit 3 so that the image processing unit 3 does not generate new processed data. The restart of the image processing unit 3
This is performed when the control circuit 4 detects that the empty state of the input FIFO state information 5 is released or that the full state of the output FIFO state information 6 is released.

FIG. 2 is a timing chart for explaining the normal operation of the image processing apparatus according to the present invention. During the assertion period of the image data input request signal IREQ to the input FIFO memory 1, the image data VD is supplied to the image data input strobe signal IA.
The image data is written to the input FIFO memory 1 by transferring in synchronization with the CK, and the EM is transmitted by the first IACK.
When the PTY signal goes high, the input FIFO memory 1
Indicates that the empty state has been released. When this state is detected by the operation clock RCLK of the image processing unit 3, the image data is input from the input FIFO memory 1 to the image processing unit 3 as RDATA. In the figure, D # 1 indicates intermediate processing data, and D # n indicates final processing data. In the example of the data compression processing as shown in FIG. 2, since there is always data in the input FIFO memory 1, the input FIFO memory read signal IFRD is continuously input so that the input FIFO memory 1
Although the image data transfer from the memory 1 to the image processing unit 3 is performed continuously, for example, the image processing unit 3 increases the output data amount compared to the input data amount as in the decompression process. In the processing device, image data is intermittently read from the input FIFO memory 1 according to the operation of the image processing unit 3.

FIG. 3 is a schematic internal block diagram of the image processing section 3 which operates according to the timing chart shown in FIG. The image processing unit 3 includes n intermediate processing units 11 to 13 and a latch circuit 1 that holds an output of each processing unit by a clock RCLK.
The output of each latch is input to the next intermediate processing unit. The control signal ENB of the latch circuit corresponds to the control signal 7 in FIG. 1. For example, when ENB is at a high level, the data on the input side is taken in by RCLK and output at the same time, and when ENB is at a low level, it depends on the state of RCLK. However, the data on the input side is not taken in, and the data immediately before ENB goes low is output.

The image data R captured by the image processing unit 3
DATA is sequentially processed through a plurality of intermediate processing units in synchronization with RCLK. The first intermediate processing data D # 1 is eventually written to the output FIFO memory 2 as final processing data D # n. As a result, the empty state of the output FIFO memory 2 is released, and the external data read request signal ORCQ is asserted. The OREQ in FIG.
OREQ continues to be asserted as long as there is data that can be read out in the output FIFO memory 2 because the signal matches the signal indicating the empty state of the output FIFO memory 2 and the read-out strobe signal OACK is input during the OREQ assertion period to perform image processing. Data ODATA is read from the output FIFO memory 2. When batch reading of output data in a predetermined word unit is permitted, every time a data amount of a predetermined word unit is accumulated in the output FIFO memory 2, the output FIFO memory 2
REQ may be asserted. In FIG. 2, since there is always room for writing data in the output FIFO memory 2, by continuously inputting the output FIFO memory write signal OFWR, data transfer from the image processing unit 3 to the output FIFO memory 2 is continuously performed. However, for example, the image processing unit 3
In an image processing apparatus in which the output data amount is smaller than the input data amount as in the compression processing, data is intermittently written to the output FIFO memory 2 according to the operation of the image processing unit 3. FIG. 4 is a timing chart for explaining the characteristic operation of the present invention.

FIG. 4 shows a data read request signal OREQ.
Since the read strobe signal OACK is not immediately input even when the output FIFO memory 2 is asserted, the output FIFO memory 2
Is 8 words, the 8th final processing data D #
The output FIFO memory 2 becomes full from time t1 when n is written to the output FIFO memory 2. At time t2, the FULL signal indicates a low level full state,
The writing to the output FIFO memory 2 is not performed and the time t2
Thereafter, the output FIFO memory write signal OFWR stops until the FULL signal goes high and the full state is released. At this time, the image data is continuously read from the input FIFO memory 1 to the image processing unit 3 until the time t1, and in this state, the data is stored in the latch circuits provided at the outputs of the respective intermediate processing units shown in FIG. Is held. When new data is input to each intermediate processing unit at time t2, the data D # n stored in the final latch circuit 16 shown in FIG. 3 is pushed out to the output FIFO memory 2 side. In order to prevent this, control signals ENB of latch circuits 14 to 16 included in image processing unit 3 shown in FIG.
Becomes low level and stops the operation of the latch circuit while the full state continues from time t1 when the output FIFO memory 2 becomes full. At the same time, the supply of the input FIFO memory read signal IFRD is stopped. When the full state of the output FIFO memory 2 is released by the input of the read strobe signal OACK, the ENB signal goes to a high level. Will be resumed.

At time t4, the last data stored in the input FIFO memory 1 is read out, so that the EMPTY signal indicating the state of the input FIFO memory 1 changes to low level. When the data is read from the input FIFO memory 1 at the time t5, meaningless data is inserted into the valid data string. To prevent this,
The supply of the input FIFO memory read signal IFRD is stopped, and the control signals ENB of the latch circuits 14 to 16 included in the image processing unit 3 shown in FIG. 3 are changed from the time t4 when the input FIFO memory 1 becomes empty to the empty state. Is low level, the operation of the latch circuit is stopped. Image data input strobe signal IACK
When the input FIFO memory 1 has been released from the empty state by the input of the
The latch operation of the latch circuits 14 to 16 and the image processing are restarted from the time t6 detected by CLK.

In the present invention, the latch operation of the latch circuit for storing and holding the intermediate result of the image processing is controlled by the state of the input FIFO memory and the output FIFO memory, so that the supply of the image data after the start of the image processing. Even if the processing is stopped halfway or the processing result is not quickly taken out of the image processing apparatus, the processing result up to that point is not lost and there is no need to process meaningless data.

[0016]

As described above, according to the present invention, a FIFO memory is provided in each of the input stage and the output stage of the image processing section, and the state of the input FIFO memory and the output FIFO are provided.
Since the operation of the image processing unit is controlled according to the state of the memory, even if the data transfer speed on the input side or output side is significantly different from the operation speed of the image processing unit, the image processing result can be obtained. It is possible to provide an image processing apparatus that can be applied to a wide range of systems without losing it.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a schematic configuration of an image processing apparatus according to the present invention.

FIG. 2 is a timing chart illustrating a normal operation of the image processing apparatus according to the present invention.

FIG. 3 is a schematic internal block diagram of an image processing unit 3;

FIG. 4 is a timing chart illustrating a characteristic operation of the present invention.

[Explanation of symbols]

1 ... input FIFO memory, 2 ... output FIFO memory, 3
... Image processing unit, 4 ... control circuit, 5 ... input FIFO status information, 6 ... output FIFO status information, 7 ... control signals, 11 to 11
13: intermediate processing unit, 14-16: latch circuit

Claims (1)

(57) [Claims] An image processing unit comprising: an input FIFO memory for temporarily storing input data to be processed; image data read from the input FIFO memory for image processing; and latch means for holding an intermediate result of the image processing. When,
An output FIFO memory for temporarily storing output data of a processing result in the image processing unit, an input FIFO memory, and an output FIFO
By detecting the state of the O memory and a control unit for controlling the operation of the image processing unit, inputs the control unit latch operation of said latch means FIF
Control based on the status of O memory and output FIFO memory
An image processing apparatus comprising: