JP3414049B2 - Image processing device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus suitable for use in, for example, a video printer.

[0002]

2. Description of the Related Art A video printer is known in which image data of a desired scene is stored in a memory and the image data is printed out on photographic paper. It is convenient to use this video printer, for example, to capture a scene in which ingredients and the like are introduced in a cooking program and save the photographic paper on which the data is printed.

The video printer is provided with a memory for storing desired image data. The memory stores, for example, one frame of video data. Then, the video data is read from the memory and printed out on photographic paper.

[0004]

The memory described above is managed by the main bus master and the sub bus master. When the sub bus master accesses the memory at the video rate and is displaying data on the monitor, the main bus master can access the memory only during the blanking period, which is inefficient in memory utilization. turn into.

Therefore, an object of the present invention is to enable the main bus master to access the memory for a period longer than the blanking period while displaying the data written in the memory on a monitor, so that the memory can be effectively utilized. It is to provide a possible image processing device.

[0006]

SUMMARY OF THE INVENTION According to the present invention, a first bus master and a second bus master which are independent of each other, and a memory in which a video signal is written and which is managed by the first and second bus masters are provided. And a switching means for switching between the first and second bus masters, and the first bus master can access the memory in a period longer than the blanking period of the video signal.

[0007]

The first bus master and the second bus master are connected to the storage element that stores the video signal. The first bus master can access the storage element for a period longer than the blanking period of the video signal.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram when an image processing apparatus according to the present invention is applied to a memory of a video printer. The memory of the video printer shown in FIG. 1 is managed by the main bus master and the sub bus master. The bus master may be, for example, a DMAC (Direct Memory Access Controller) or a DMA.
A built-in CPU can be applied.

The video signal supplied from the outside is A / D converted, and then the terminals 1b and 1c in the sub-bus master 1 are connected.
Is written in the memory 2 via. The memory 2 is, for example, a frame memory. The video signal read from the memory 2 and output via the terminals 1c and 1a in the sub-bus master 1 is D / A converted and then supplied to a monitor (not shown). The main bus master 3 is connected to the terminal 1b. A memory 4, a memory 5, ... Are connected to the main bus master 3. Also,
Although not shown, a device such as a print head (not shown) for printing is connected to the main bus master 3. Further, the sub-bus master 1 is input with various parameters such as a reduction ratio of an image displayed on the monitor and a display position / display frame.

For example, in the memory 4, the supplied video signal is not subjected to any processing. Therefore, the video signal as it is is output from the memory 4. The memory 5 performs a predetermined processing on the supplied video signal. A video signal for printing, for example, is stored in the memory provided together with the memory 4, the memory 5, and the like. The terminal 1a and the terminal 1b are switched by the terminal 1c provided in the sub-bus master 1. That is, by connecting the terminal 1a to the memory 2,
The memory 2 is managed by the sub bus master 1. The memory 2 is managed by the main bus master 3 by connecting the terminal 1b to the memory 2. The switch 6 also sends a signal for notifying the main bus master 3 of the connection state of the bus.

FIG. 2A is a timing chart showing access timing to the memory 2, and FIG. 2B is a timing chart showing monitor output timing. When the video signal from the memory 2 is not output to the monitor, the memory 2 is connected to the main bus master 3, and the video signal stored in the memory 2 is transferred to, for example, the memory 5. Memory 5
Performs a predetermined processing on the video data. Thus, the system of the main bus master 3 can process the video signal regardless of the system of the sub bus master 1. The video data processed in the memory 5 is stored in the memory 2 while the sub bus master 1 is not accessing the memory 2. During this period, the memory 2 can be accessed only by the main bus master 3.

FIG. 3 is a detailed block diagram of the sub-bus master 1. The bus is divided into a data bus system and a control bus system. The control bus system includes signals necessary for memory control such as address, RAS, CAS, WE, and OE. The video signal is supplied to the A / D conversion circuit 12 via the input terminal 11. The digital video signal output from the A / D conversion circuit 12 is subjected to predetermined data processing in the data processing circuit 24, and then,
It is supplied to the terminal 13a of the switch 13. Also, the video signal via the input terminal 11 is supplied to the sync signal separation circuit 14. The sync signal separation circuit 14 separates the sync signal from the video signal. This synchronization signal is sent to the AFC / timing generation circuit 15. The AFC / timing generation circuit 15 generates a control reference signal such as a write clock and a bus switching signal. The AFC / timing generation circuit 15 is connected to the terminal 16a of the switch 16 so that the control reference signal is supplied to the terminal 16a. Further, the AFC / timing generation circuit 15 is connected to the terminal 17a of the switch 17, so that the bus switching signal is supplied to the terminal 17a.

The terminal 16c of the switch 16 is connected to the memory control system generation circuit 18. The memory control system generation circuit 18 generates a signal such as an address necessary for memory control based on the control reference signal. Memory control system generation circuit 1
The output signal of 8 is supplied to the terminal 19b of the switch 19. The bus switching signal supplied to the switch 19 and the switch 20 via the terminal 17c of the switch 17 is used as a bus switching signal for the main bus master and the sub bus master. The control system of the main bus master is connected to the terminal 19a of the switch 19 to which the bus switching signal is supplied. The data system of the main bus master is connected to the terminal 20a of the switch 20 to which the bus switching signal is supplied. As mentioned above,
Various memories are connected to the main bus master. The terminal 19c of the switch 19 is connected to the control system of the memory 2, and the terminal 20c of the switch 20 is connected to the data system of the memory 2. The terminal 20b of the switch 20 is connected to the terminal 13c of the switch 13.

The terminal 16b of the switch 16 and the switch 1
The terminal 17 b of No. 7 is connected to the timing generation circuit 21. The timing generation circuit 21 uses a built-in timing generator to generate a bus switching signal and a control reference signal. These signals are the synchronization signal generation circuit 22.
Is supplied to. The sync signal generation circuit 22 generates a sync signal based on the supplied signal. This synchronization signal is supplied to the adder circuit 23. Switch 1 terminal 1
The video data read from the memory via 3b is
The data processing circuit 25 performs predetermined processing and then supplies the data to the terminal 26a of the switch 26. An image frame data generation circuit 27 is connected to the terminal 26c of the switch 26. The data processing circuit 25 reduces the image displayed on the monitor. The timing generation circuit 21 shortens the access period to the memory 2 and releases the memory 2 to the main bus master outside this period. Image frame data generation circuit 2
7 generates image frame data. Further, the timing generation circuit 21 outputs a signal for replacing the area of the memory 2 where the video data is not displayed within the monitor effective screen.

The switch 26 is switched by a control signal output from the timing generation circuit 21. The signal obtained through the terminal 26b of the switch 26 is D /
It is supplied to the A conversion circuit 28. The analog video signal converted by the D / A conversion circuit 28 is supplied to the adder 23. The adder 23 adds a sync signal to the analog video signal. Then, it is output to the monitor via the output terminal 29.

In such a circuit, the switch 13, during H and V blanking during data writing.
16 and 17 terminals 13c, 16c and 17c are terminals 1
3a, 16a and 17a. The video signal output from the data processing circuit 24 is written in the memory 2 via the switch 13 and the switch 20. Next, the terminal 20c of the switch 20 is switched to the terminal 20a,
The memory 2 is connected to the data system of the main bus master. On the other hand, the control system signal generated by the memory control system generation circuit 18 is passed through the switch 19 to
It is supplied to the memory 2 in the sub-bus master system. The memory 2 is controlled by this signal.

At the time of reading data, the terminals 13c and 16 of the switches 13, 16 and 17 are provided during V blanking.
c and 17c are switched to terminals 13b, 16b and 17b. The operation thereafter is the same as that at the time of writing data. However, at the time of reading, since there is no reference signal such as a synchronization signal, in the timing generation circuit 21,
A bus switching signal and a control system reference signal are generated.

As described above, while the data in the memory 2 is not being output to the monitor, the memory 2 is managed by the main bus master, and the data processed by the memory 5 etc. is transferred to the memory 2. After that, the next data stored in the memory 2 is transferred to the memory 5 by an amount necessary for processing. By configuring the sub-bus master 1 as described above, it is possible to improve the utilization efficiency of the bus and other devices.

In the sub-bus master 1 shown in FIG. 3, the sync signal is separated on the input side before the A / D conversion circuit 12, but the sync signal is separated from the video signal after A / D conversion. You may do it. Also, on the output side, a digital synchronizing signal is internally generated, and the synchronizing signal is added to the signal read from the memory before D
/ A conversion may be performed.

FIGS. 4, 5 and 6 are diagrams showing images displayed on the monitor when different parameters are supplied to the sub-bus master. FIG. 4 shows a video signal when no parameter is designated for the sub-bus master. In this case, since all the video signals during the memory access period by the sub master are output to the monitor 31, the memory access is performed at the same time when the V blanking period and the H blanking period end, and the monitor is enabled. The video signal is displayed over the entire screen. FIG. 5 shows a video signal when a parameter relating to the display frame is designated as the sub bus master. In this case,
Memory access is performed from the positions in the V and H directions corresponding to the parameters of the display frame, and the video signal of only the area of the display frame 32 is displayed on the monitor. FIG. 6 shows a video signal when the parameter relating to the reduction ratio is designated as the sub-bus master. In this case, similarly to the description with reference to FIG. 5, memory access is performed from the position in the V direction and the H direction corresponding to the parameter of the reduction rate, and the video signal reduced only in the area of the reduction rate frame 33 is displayed on the monitor. Is output.

In the above embodiment, the image processing apparatus according to the present invention is applied to a video printer, but the present invention is not limited to this and other equipment to which the present invention can be applied. Also in, it is possible to obtain the same effect as that of the above-described embodiment.

[0022]

According to the present invention, while the video data read from the memory is output as a monitor, the main bus master is operated during the period when the memory is not accessed at the video rate, that is, the period longer than the original blanking period. You can access the memory.

[Brief description of drawings]

FIG. 1 is a block diagram when an image processing apparatus according to the present invention is applied to a memory of a video printer.

FIG. 2 is a timing diagram regarding a memory and a monitor.

FIG. 3 is a detailed block diagram of a sub-bus master.

FIG. 4 is a diagram showing an example of video data displayed on a monitor.

FIG. 5 is a diagram showing an example of video data displayed on a monitor.

FIG. 6 is a diagram showing an example of video data displayed on a monitor.

[Explanation of symbols]

1 sub bus master 3 Main bus master 27 Image frame data generation circuit 32 display frames 33 Reduction rate frame

Front page continued (72) Inventor Kayo Ishii 6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation (72) Inventor Kazumasa Miyazaki 6-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Incorporated (72) Inventor Toshiyuki Iijima 6-735 Kitashinagawa, Shinagawa-ku, Tokyo Sony Corporation (56) Reference JP-A-7-284054 (JP, A) JP-A-59-226581 ( (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04N 5/76-5/956

Claims (2)

(57) [Claims] 1. A first bus master and a second bus master which are independent of each other, a memory in which a video signal is written and which is managed by the first and second bus masters, and the first and second bus masters. An image processing device comprising: switching means for switching between two bus masters, wherein the first bus master can access the memory during a period longer than the blanking period of the video signal. 2. The image processing apparatus according to claim 1, wherein the parameter relating to the video signal is supplied to the second bus master.