JPH09297665A - Image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform the input of data to an image processing means and the input/output of data to a system bus in parallel to each other by cutting the connection between the system bus and a buffer storage means via a separation means. SOLUTION: The local buses A23 and B21 can be separated from each other by a gate circuit 22 for a compression device 7 in an image processing mode. Thus, a control part 28 sends a signal to a bus bridge 20 in a write cycle (1) set to a RAM buffer 24 and the data are successively outputted to a local bus B from a buffer included in the bridge 20 synchronously with a clock signal. Then the part 28 sets the circuit 22 in a conductive state and outputs the data of the bus B to a local bus A. In a read cycle (2) and a DMA write cycle (4) of the buffer 24, the part 28 sets the circuit 22 in a non-conductive state and separates the buses A and B from each other. Thereby, both operations (2) and (4) can be simultaneously carried out.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus such as a printer, a copying machine, a facsimile apparatus, etc.
The present invention relates to an image processing device having a high-speed image processing function.

[0002]

2. Description of the Related Art In a conventional image processing apparatus, especially in recent printers, the resolution and the printing speed are improved, and the data transfer rate is the most important in connecting the printer to the system bus of the image data input / output apparatus. It is one of the factors. Therefore, in order to realize high-speed printing, it is necessary to increase the data transfer speed including image processing.

As a method for improving the data transfer rate,
For example, Japanese Patent Application Laid-Open No. 4-256186 discloses a method of compressing data in a control device and transferring the compressed data to a printer to reduce the transfer data amount. In this system, the compression circuit in the control device locally reads out the image data stored in the image memory, compresses it, and outputs it to the printer. On the printer side, the received compressed image data is decompressed by a decompression circuit and printed out.

[0004]

In the conventional method as described above, the maximum transfer speed to the printer is determined by the time required for the compression processing, because the compression processing itself does not have any means for improving the transfer speed. It will be.

As a method of compressing the data sent to the printer, generally, the method shown in FIG. 8 can be considered.
The system bus 51 includes a CPU 52, a ROM 53, and an RA.
An M54, a compression device 55, and a decompression device 56 are connected, and a printer 57 is connected to the decompression device 56.
In addition, the compression device 55 includes the bus bridge 61 and the first FI.
It is composed of an FO 62, a compression circuit 63, and a second FIFO 64.

To explain the operation of this system, the RAM 54
During the period of reading the data from the RAM 54, the data read from the RAM 54 passes through the bus bridge 61 to the first FIF.
It is sent to O62. When the data is stored in the first FIFO 62, the compression circuit 63 performs a compression operation, and the compressed data is stored in the second FIFO 64. Next, RA
In the data writing period to M54, the second FIFO 6
The compressed data stored in No. 4 is written in the RAM 54 via the bus bridge 61. The data reading period from the RAM 54 and the data writing period to the RAM 54 are alternately performed. On the other hand, the compressed data stored in the RAM 54 is sent to the printer 57 via the decompression device 56. According to this method, the decompressor 56 is expanded from the RAM 54.
The amount of data sent to is reduced and the transfer speed is improved.

However, during the data writing period to the RAM 54, there is a problem that the data compression operation by the compression circuit 63 is not performed because the data in the first FIFO 62 is exhausted, and the compression processing speed is slow. Therefore, there is a problem that high-speed image processing / printing is difficult.

An object of the present invention is to solve the above-mentioned problems of the prior art and to provide an image processing apparatus capable of high-speed image processing.

[0009]

In order to achieve the above object, the present invention provides a system bus in an image processing apparatus, and a buffer storage means for temporarily holding image data input from the system bus. Image processing means for inputting data read from the buffer storage means and performing compression or expansion processing, data input to the image processing means, and data input / output to / from the system bus operate in parallel. In addition, it is characterized in that it comprises a control means for controlling data transfer between the respective means, and a separation means controlled by the control means and disconnecting the connection between the system bus and the buffer storage means at least during the parallel operation. is there.

According to the present invention, with the above configuration, it becomes possible to operate the input of data to the image processing means and the input / output of data to the system bus in parallel. It will be possible to greatly improve the operating efficiency. As a result, the processing speed of the image processing apparatus can be improved.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 2 is a block diagram showing a system configuration example of a printer control apparatus which is an embodiment of the image processing apparatus of the present invention. The CPU 1 controls the entire device according to a control program stored in the ROM 2. RA
M3 is used as a work area for processing and a buffer for image information. The disk device (DISK) 4 is, for example, a hard disk device and stores image information or programs. The printer 5 is a device for printing the input image information, and the decompression device 6 is, for example, R
The image data stored in AM3 or DISK4 is restored to the original data and output.

The compression device 7, which will be described in detail later, is a RAM.
3 or DISK 4, image information is input, compression processing is performed, and the compressed image data is output to the RAM 3 or DISK 4 again. The LAN interface circuit 8 is a circuit for interfacing with an external LAN 10, and image information to be printed is input from another workstation connected to the LAN 10 via the circuit. The system bus 9 connects each circuit in the device. In addition to the LAN, for example, the input of image information is 1
A removable information recording medium such as a parallel or serial interface circuit of 1: 1 or a floppy disk device may be used.

FIG. 1 is a block diagram showing the configuration of the compression device 7 of FIG. The bus bridge 20 is the system bus 9
Connected to the local bus B21 and performs two functions. One is to execute a writing / reading process of parameters and status information from the CPU 1 to the control unit 28 and the compression processing unit 26, and the other is to execute a DMA transfer process. In the DMA transfer process, the bus bridge 20 serves as a bus master on the system, and reads / writes to the RAM 3 (or DISK 4).
Perform write access. For this reason, a data buffer exists in the bus bridge 20.

The gate circuit 22 as a separating means is connected between the local bus B21 and the local bus A23,
The tri-state bus driver outputs data on the local bus B21 to the local bus A23 under the control of the control unit 28. The RAM buffer 24, which is a buffer storage unit, is a RAM that stores image data DMA-transferred from the RAM 3 through the gate circuit 22, and is composed of, for example, an SRAM having a capacity of 32 kbytes. FI
The FO-2 (25) is a FIFO buffer having a capacity of, for example, about 4 kbytes, and buffers the image data read from the RAM buffer 24 under the control of the control unit 28.

The compression processing section 26 which is an image processing means is
Image data is read from IFO-2 (25) and the CPU
Based on the method instructed from 1, the compression processing is performed using a general compression algorithm, and the result is output to the FIFO-1 (27). The FIFO-1 (27) is also a FIFO buffer having a capacity of about 4 kbytes.
When a certain amount (for example, half) of data is accumulated in the buffer, the data is DMA-transferred to the RAM 3 (or DISK 4) via the local bus B21 and the bus bridge 20 under the control of the control unit 28. The control unit 28
The compression processing unit 2 has a configuration and operation as described below.
In 6, the transfer operation of the image data is controlled so that the compression processing can be executed without delay.

FIG. 3 is a block diagram showing the structure of the control unit 28. The arbiter A31 is a circuit that arbitrates contention for access to the local bus A23, and includes a plurality of control units 3
This is a circuit which inputs the bus request signals from Nos. 4 and 35 and gives the bus use permission signal to only one of the control units according to the method described later with reference to FIG. Arbiter A3
1 also performs timing control of writing / reading to / from the RAM buffer 24.

The arbiter B30 is a circuit that arbitrates contention for access to the local bus B21, and receives bus request signals from a plurality of control units 32 to 34, respectively.
It is a circuit that gives a bus use permission signal to only one of the control units by the round robin method. It should be noted that the permission signal continues to be output until the control unit given the permission completes one transfer cycle.

The slave write control section 32 is sent from the CPU 1 via the bus bridge 20, and the control section 2
8) A write / read access to a register inside or the compression processing unit 26 is accepted, and a bus request signal is sent to the arbiter B30 in order to use the local bus B21. Then, with permission, the slave write cycle shown by the dotted line (3) in FIG. 1 is controlled. When the transfer is completed, the arbiter B30 is notified of the end.

The DMA write control unit 33 uses, for example, FI.
The amount of data stored in FO-1 is monitored, and transfer control is started when more than half of the data is stored, and arbiter B3
When the bus use permission is obtained from 0, the compressed image data is read from the FIFO-1 (27), and the dotted line (4) in FIG.
As shown in, local bus B21, bus bridge 20
A DMA write cycle for performing a DMA transfer to the RAM 3 via When the buffer of the bus bridge 20 is full, this cycle is interrupted, and at the end of the cycle, the arbiter B30 is notified of the end.

The DMA read control unit 34 is activated by an instruction from the CPU 1 and controls the DMA transfer from the RAM 3 to the RAM buffer 24. Therefore, it is necessary to obtain the bus use permission from both the arbiter A31 and the arbiter B30. When the permission is obtained, the gate circuit 22 is controlled to be in the conductive state, the write address and the write control signal are given to the RAM buffer 24, and output from the bus bridge 20 as indicated by the dotted line (1) in FIG. DMA read (R to write image data to RAM buffer 24
AM buffer write) cycle is executed.

Under the control of the CPU 1, the RAM read control unit 35 reads the image data from the RAM buffer 24, and as shown by the dotted line (2) in FIG.
2 (25). The control unit 28 having the above-described functions can be created by individual hardware or can be realized by a storage program type control device.

FIG. 5 shows the DMA read controller 3 of FIG.
4 is a flowchart showing the operation (processing) of the RAM read control unit 35 and the arbiter A31. This process is roughly divided into three parts, and S1 to S7 in FIG.
M buffer read cycle, S8 to S12 are loops waiting for a use permission signal from the arbiter A31, S13 to S20
Is a DMA read (RAM buffer write) cycle. In step S1, it is determined whether the read counter R_CTR in the RAM read control unit 35 is 0 or not. This R_CTR is set with a read data amount (for example, 4 kbytes) from the CPU 1, and
It is decremented by one every one (eg, 1 byte) transfer. Therefore, if R_CTR is not 0, there remains data to be transferred.

If the result of the determination in step S1 is negative (there is data), the process proceeds to step S2, and a predetermined value is preset in the interval counter R_INT which counts the number of data transferred in one read cycle.
For example, if the number of data transferred in one read cycle is 4 bytes, the predetermined value 4 is preset in R_INT. In step S3, the RAM read control unit 35 sends an output enable signal (OE) and a chip select signal (C) to the RAM buffer 24.
S) is output and at the same time the read address is output. Based on these signals, one image data is read from the RAM buffer 24 and stored in the FIFO-2.

In step S4, R_CTR and R_INT are decremented by -1, respectively. Note that the read address is also sequentially updated (+1) here, and is reset when the maximum value is reached. In step S5, R_CTR
Is determined to be 0, and if the result is affirmative, the process proceeds to step S8, but if the result is negative, step S6.
Move to In step S6, R_INT is 0
If the result is affirmative, the process proceeds to step S8. If the result is no, the process proceeds to step S7. In step S7, it is determined whether or not there is a vacancy in the FIFO-2. If the result is negative, the process proceeds to step S8, but if the result is affirmative, the process returns to step S3 to return the data from the RAM buffer 24. Repeat reading.

In step S8, it is determined whether the write counter W_CTR in the DMA write control unit 33 is 0 or not. This W_CTR has a write data amount set by the CPU 1 and is transferred each time one data is transferred.
1 is done. Therefore, if W_CTR is not 0, there remains data to be DMA-transferred. If the determination result of step S8 is affirmative, the process returns to step S1, but if not, the process proceeds to step S9. In step S9, a predetermined value (for example, 4) is preset in the interval counter W_INT that counts the number of data transferred in one write cycle.

In step S10, the arbiter B3
It is determined whether or not the bus use permission signal W_GNT from 0 is 1 (permission). If the result is affirmative, the process proceeds to step S15, but if not, step S15.
Go to 11. In step S11, W_IN
T is decremented by 1, and in step S12, it is determined whether or not W_INT is 0. If the result is negative, the process returns to step S10, but if the result is affirmative, the process proceeds to step S1. The processing of steps S10 to S12 is processing for waiting for the use permission signal from the arbiter B, and when the W_GNT signal becomes 1, the processing immediately proceeds to step S1.
The write processing of 5 or less is performed.

In step S13, it is determined whether or not W_CTR is 0. If the determination result is affirmative, the process returns to step S1, but if not, step S14.
Move to In step S14, it is determined whether or not W_GNT is 1, and if affirmative, step S14
Proceed to 15. In step S15, a predetermined value (for example, 4) is preset in the interval counter W_INT.
In step S16, the DMA read control unit 34
Outputs a write enable signal (WE) and a chip select signal (CS) to the RAM buffer 24 from
At the same time, the write address is output. Further gate circuit 2
An operation signal is output to 2. Based on these signals, image data is stored in the RAM buffer 24 from the bus bridge 20 via the local bus B and the gate circuit 22.

In step S17, W_CTR and W_INT are decremented by -1, respectively. The write address is also sequentially updated (+1) here, and is reset when the maximum value is reached. In step S18, W_C
It is determined whether or not TR is 0. If the result is affirmative, the process proceeds to step S1, but if the result is negative, the process proceeds to step S19. In step S19, W_I
It is determined whether NT is 0, and if the result is affirmative, the process proceeds to step S1, but if the result is no, the process proceeds to step S20. In step S20, it is determined whether or not there is data to be transferred in the buffer in the bus bridge 20. If the result is negative, the process proceeds to step S16, but if the result is affirmative, the process returns to step S1.

By performing the above processing, if there is data to be transferred, the data are transferred collectively by the number preset in each interval counter,
When both a write request and a read request exist, they are processed alternately.

FIG. 7 is a time chart showing the operation of the RAM buffer 24. FIG. 7A shows the operation when the CPU 1 sets an arbitrary value in R_CTR when the image data is already stored in the RAM buffer 24. In such a case, the process proceeds from step S1 to S2 in the flowchart of FIG.
The image data is read the number of times preset to R_INT (for example, four times). When R_INT becomes 0, the process proceeds from step S6 to S8, and when W_CTR is 0, the process returns to S1 again and the read cycle is repeated. Even when the value is set only in W_CTR, the write cycle of steps S16 to S20 is repeated in the same form as in FIG. 7A.

FIG. 7B shows a process when the CPU 1 sets a value in W_CTR during execution of the read cycle of FIG. 7A, and when writing to W_CTR is executed at an arbitrary timing, The process moves from step S6 to step S8 and step S9. And arbiter B
A bus request signal is sent to the bus 30, but a permission signal W_G is issued while the bus is being used by another control unit.
NT does not become 1. Therefore, it waits until W_GNT becomes 1 the number of times preset in W_INT in the maximum step S9. This means that if waiting indefinitely, the read processing of steps S3 to S7 is not executed, and the FIFO
This is to prevent the data of -2 from being lost.

When W_GNT becomes 1, step S15
The image data is written in the RAM buffer 24 the number of times preset to W_INT. And
When W_INT becomes 0, steps S19 to S
Returning to 1, if R_CTR is not 0, the process proceeds to step S2 to execute the reading process this time. Therefore, R_
When both CTR and W_CTR are not 0, the read cycle and the write cycle are alternately executed, and the number of transfer data in each cycle can be set arbitrarily.

FIG. 4 is a waveform diagram showing signal waveforms in each transfer cycle. The left side of FIG. 4 is the RAM buffer 24
In this case, the local bus B shown in the upper part and the local bus A shown in the lower part operate in synchronization with each other. First, the control unit 28 sends a buffer read enable signal BUF_RE (negative logic: 0 is active, other signals are the same) to the bus bridge 20, and data is read from the buffer in the bus bridge 20 in synchronization with the clock signal CLK. Local bus B in order
Is output to The control unit 28 controls the gate enable signal GA
The gate circuit 22 is turned on by TE_EN, and the data on the bus B21 is output to the bus A23. Also RA
The WE, CS signal and write address signal are generated for the M buffer 24 to write the data on the bus A.
In this example, four pieces of data are written in one write cycle, but the number can be arbitrarily set in R_INT.

The right side of FIG. 4 shows the operations of the read cycle (2) from the RAM buffer 24 and the DMA write cycle (4). In this case, the control unit 28 controls the gate circuit 2 by the gate enable signal GATE_EN.
The bus B21 and the bus A23 are separated from each other by setting the switch 2 to the non-conductive state. Therefore, these operations (2) and (4) can be executed simultaneously. The slave write cycle (3) can be executed simultaneously with the read cycle (2).

Although the embodiment has been described above, the following modifications are also possible. FIG. 6 shows the second gate circuit 22.
FIG. 3 is a circuit diagram showing an example of the embodiment. In printers etc.,
For example, when performing double-sided printing, it is necessary to rotate the image by 180 degrees. In this case, it is necessary to reverse the array of image data and also the pixel array in each image data. In the second embodiment of the gate circuit, the pixel data array inverting means is provided in the gate circuit 22.

In FIG. 6, the image data on the local bus B21 received by the bus receiver 30 is connected as it is to the input terminal group A of the selector 31, and the most significant bit is at the least significant bit position. Further, the least significant bits are rearranged so that they are located at the most significant bit positions and are connected to the input terminal group B of the selector 31. If the control signal input from the control unit 28 to the terminal C is 0, the selector 31 outputs the data of the terminal group A to the output terminal group O,
If it is 1, the data of the terminal group B is output. The tri-state bus driver circuit 32 outputs the data output from the selector 31 to the local bus A based on the control signal from the control unit.

With such a circuit, the bit array in each image data can be inverted. For example, if the image data in the RAM 3 is rearranged under the control of the CPU 1, 180
Image data inverted once is obtained. Alternatively, if one page of image data can be stored in the RAM buffer 24, the data may be rearranged by reversing the writing order and the reading order to the RAM buffer 24.

As described in detail above, in the image processing apparatus of this embodiment, the gate circuit 22 can separate the local bus A23 and the local bus B21. Therefore, from the RAM buffer 24 to the FIFO
-2 can be performed in parallel with the transfer of the compressed data stored in the FIFO-1 to the RAM3, and the compression processing unit 26 can be operated without stopping or in a short stop period. Therefore, the compression processing speed can be significantly improved as compared with the conventional case. Also,
In the image processing apparatus of this embodiment, the RA is adjusted by adjusting the value of the interval counter, for example.
The data input speed to the M buffer 24 and the data transfer speed to the FIFO-25 can be independently controlled, and the processing in the compression processing unit can be controlled so as to be executed without delay. Although the arbiter B needs to be permitted during the writing process to the RAM buffer 24, the waiting time can be shortened by sending the bus request in advance.

Although an example of performing compression processing as image processing has been disclosed as an embodiment, the present invention can be applied to, for example, decompression processing or any other image processing.

[0040]

As described above, in the present invention,
In the image processing apparatus, the separation means is provided so that the connection between the system bus and the buffer storage means can be disconnected. Therefore, data input from the buffer storage means to the image processing means for performing compression or expansion processing. And, it becomes possible to operate the data including the data after the image processing and the input / output to / from the system bus in parallel.
The operation efficiency of the image processing means can be greatly improved as compared with the conventional one. Therefore, the image processing apparatus can be operated at high speed. Moreover, since the speed of the image processing apparatus does not become a bottleneck in the transfer speed to the printer, there is an effect that the printing speed can be increased as a whole.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a compression device 7 in FIG.

FIG. 2 is a block diagram showing a system configuration example of a printer control device according to an embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a control unit 28.

FIG. 4 is a waveform diagram showing a signal waveform in each transfer cycle.

FIG. 5 is a flowchart showing operations of a DMA read control unit 34, a RAM read control unit 35, and an arbiter A31.

FIG. 6 is a circuit diagram showing a second embodiment of the gate circuit 22.

FIG. 7 is a time chart showing the operation of the RAM buffer 24.

FIG. 8 is a block diagram showing a conventional system configuration example of a printer control device.

[Explanation of symbols]

1 ... CPU, 2 ... ROM, 3 ... RAM, 4 ... Disk device, 5 ... Printer, 6 ... Decompression device, 7 ... Compression device, 8 ...
LAN interface, 9 ... System bus, 10 ... L
AN, 20 ... Bus bridge, 21 ... Local bus B, 2
2 ... Gate circuit, 23 ... Local bus A, 24 ... RAM
Buffer, 25 ... FIFO-2, 26 ... Compression processing unit, 2
7 ... FIFO-1, 28 ... control unit

Claims (13)

[Claims] 1. An image processing apparatus for compressing and storing image data, decompressing the image data and outputting the decompressed image to a printer. A buffer for temporarily holding a system bus and image data input from the system bus. A storage unit, an image processing unit that inputs data read from the buffer storage unit and performs compression or expansion processing, a data input to the image processing unit, and a data input / output to / from the system bus. Control means for controlling data transfer between the respective means so as to operate in parallel, and separation means controlled by the control means and disconnecting the connection between the system bus and the buffer storage means at least during the parallel operation. An image processing apparatus comprising: 2. The image processing apparatus according to claim 1, wherein the control unit deactivates the separation unit when transferring image data from the system bus to the buffer storage unit, and the system bus and buffer storage unit. An image processing apparatus, characterized in that it is connected to a means. 3. The image processing apparatus according to claim 1, wherein the data input / output to / from the system bus at the time of operating the separation means includes data image-processed by the image processing means. Processing equipment. 4. An image processing apparatus for compressing and storing image data, decompressing the image data, and outputting the compressed image data to a printing apparatus, a system bus, a local bus connected to the system bus, and a transmission from the system bus. Buffer storage means provided on the local bus for storing the compressed data or decompressed data, and the local bus for compressing or decompressing the compressed data or decompressed data read from the buffer storage means. Compression / expansion processing means for transferring the data to the system bus via the separation means, separation means for separating the connection of the local bus between the system bus and the buffer storage means, the separation means, and a target sent from the system bus. Control means for controlling a transfer operation for transferring compressed data or decompressed data to the system bus via the local bus. An image processing device characterized by the above. 5. The image processing apparatus according to claim 4, wherein the control unit connects the buffer storage unit and the system bus and transfers the buffer when the image data is transferred from the system bus to the buffer storage unit. An image processing apparatus, wherein when the image data is output from the storage means to the compression / expansion processing means, the separation means is controlled so as to separate the connection between the buffer storage means and the system bus. 6. The image processing apparatus according to claim 4, wherein the control unit is a system of image data processed by the compression / expansion processing unit when the image data is output from the buffer storage unit to the compression / expansion processing unit. An image processing device characterized in that transfer to a bus is processed in parallel. 7. The image processing apparatus according to claim 4, wherein the control means transfers data from the system bus to the control means when outputting image data from the buffer storage means to the compression / expansion processing means. An image processing apparatus characterized in that parallel processing is performed. 8. The image processing apparatus according to claim 4, wherein the control unit reads the compressed data or the decompressed data from the buffer storage unit while inverting the data and outputs the data to the compression / decompression processing unit. An image processing device characterized by the above. 9. The image processing apparatus according to claim 4, wherein the buffer storage unit is composed of SRAM. 10. The image processing apparatus according to claim 4, wherein a FIFO is provided before and after the compression / expansion processing means. 11. The image processing apparatus according to claim 4, wherein the separation unit connects the local bus to a first local bus connected to the system bus, the buffer storage unit, and the compression / expansion processing unit. And a second local bus that is used to separate the image processing apparatus. 12. The image processing apparatus according to claim 4, wherein the separating unit includes a data array inverting unit. 13. The image processing apparatus according to claim 4, wherein the separating unit is composed of a gate circuit.