JPH0667917A - Diagnostic system for memory access controller - Google Patents

Abstract

PURPOSE:To diagnose hardware areas peculiar to respective devices at a high speed by means of a memory access controller itself. CONSTITUTION:This system is provided with a CS address register 100 where a leading address in diagnostic execution is set and the address in updated, a comparator 220 detecting a final address in diagnostic execution and resetting diagnostic start FF 210 and the CS address register 100, a CS read register means 104 storing the output of a control memory 103, request holding F/F 160-163 generating/outputting request holding signals and suppressing the reception of requests, reply suppressing F/F 170-173 suppressing the transmission of reply signals, buffers 110-113 selecting, inputting and receiving a request code, address data and a request address, the request code and data, which are the outputs of the CS read register 104 by the output of the CS read register 104 and a selective circuit 118 executing busy check, judging priority and outputting one request.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a diagnostic system for a memory access control device connected to a main memory.

[0002]

2. Description of the Related Art Conventionally, a memory access control device is diagnosed by control from a diagnostic processing device after startup processing, and a hardware area such as a port section unique to each device is actually connected to another device. Or with a specific diagnostic program.

[0003]

In the above-mentioned conventional diagnostic method for the memory access control device, before connecting the arithmetic processing unit and the input / output processing unit, the hardware area such as a port unit peculiar to each device is preliminarily set. There is a problem that the memory access control device itself cannot execute the diagnosis at the same high speed as in a state where the device is connected to each device.

[0004]

According to the method of the present invention, a request source device number, a request code, a request address, and a request source device number are internally provided in a memory access control device diagnostic system for performing main memory access processing from a plurality of access request sources. A control memory having write data and a field for controlling the inside of the memory access control device, a steady detection means for detecting that there is no valid request in the memory access control device, and an output of the steady detection means
When it is "1", the diagnosis start flag means is set to "1" when an instruction from the processor is received, and when the diagnosis start flag means is "1", the execution start address for the diagnosis to the control memory Is set, and the address is updated further, the diagnostic start flag means and the comparing means for resetting the address register when the final address of the diagnostic execution is detected, the register means for storing the output of the control memory, and A request hold signal that generates and outputs a request hold signal to the request source device indicated by the register means, and a request hold device that suppresses acceptance of the request, and a reply inhibit means that suppresses sending of a reply signal to the request source device indicated by the register means 7, and a request. The request code and address data from the original and the request address which is the output of the register means. Address, a request code, and a reception buffer for selectively inputting data by the output of the register means, and a selection means for performing a busy check of a plurality of requests from the reception buffer, further determining a priority, and outputting one request, It is characterized in that it has a request processing means for processing a request to the selecting means, and the diagnosis of the memory access control device can be performed at high speed not only at startup but also after startup.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

The memory access controller according to the present embodiment is connected to a request request source such as an arithmetic processing unit (EPU0, EPU2) or an input processing unit (IOP0, IOP2) and the main storage device 140. In this embodiment, EPU0, EPU2, IO are used as request request sources.
It has four devices, P0 and IOPP2. The memory access control device is roughly composed of a request reception port unit and a request processing unit.

In the figure, 210 is an AN of the diagnostic start signal from the diagnostic processing device and the output 360 of the steady detection circuit 300.
This is the diagnosis start F / F set by D. Start diagnosis F /
The F210 is reset when the CS address register 100 shows a constant value and the diagnostic program ends.

A steady detection circuit 300 detects that there is no valid request in the memory access control device, and outputs "1" only for one clock as a pulse at the time of steady. The input is a steady signal 310 indicating that there is no valid request in the reception buffer 110 and the buffer read register 114 for EPU0, and EPU2.
Steady signal 320 for IOP0, steady signal 330 for IOP0, steady signal 3 for IOP2
40, and a request processing unit steady signal 35 indicating that there is no request being processed in the request processing unit 120.
It is 0. The output 360 of the steady detection circuit is input to the AND gate 400.

The output of the diagnosis start F / F 210 gives a set instruction to the address register 100, the CS address is updated to +1 every clock, and the diagnosis program is executed. 220 is the CS address register 100
It is a comparator that detects that the output of the output has reached a constant value.
Reference numeral 100 denotes a CS address register that holds a read / write address of CS (CONTRACTURE STRAGE), and operates as a 11 counter while the set signal from the diagnosis start F / F 210 is output.

Reference numeral 101 denotes a CS to CS 103 at the time of initial setting.
The write data register is used by the diagnostic processor to set the write address and write signal at the start. 1
Reference numeral 02 is a CS write signal register for receiving a write signal to the CS from the diagnostic processing device, 103 is a CS, which is a control field inside the memory access control device (details will be described later), device designation, request code, request address and data. Have.

FIG. 2A shows the contents of the field at address 0 of CS 103. The contents are ALL0 and nothing is done as an operation. The contents of the internal fields are, as shown in FIG. 2B, a hit indicating the setting / cancellation of request hold for each device, the setting / cancellation of the reply suppression mode, the request code in CS103, the request address, and the validity control of data. Consists of. All of these commands are valid for the device specified in the device specification field.

The contents of the device designation field are shown in FIG.
As shown in Figure 4, EPU0 and EP are composed of 4 bits from the left.
U2, IOP0, and IOP2 are shown. It is possible to specify at the same time. The command in the internal control field is valid for the device specified. Therefore, the request hold setting and reply suppression mode of the internal control field are ″
If it is 1 "and the device designation field is all bits" 1 ", EPU0, EPU2, IPO
0, IOP2 request hold F / F and reply inhibition F / F are set to "1".

The field of the request code has the same format as the interface with each device, and read / write
A request address / data field having a bit indicating an operation such as a write operation and a mask bit corresponding to a byte at the time of partial writing has the same format as the interface with each device.

Reference numeral 104 denotes a CS reading register which receives the output of the CS 103, and 105 generates and outputs a control signal to each section from the output of the CS reading register 104 on the AND date.

Here, a rough processing flow at the time of executing the diagnosis will be described. For the diagnosis corresponding to each device, a request is output from the contents of CS 103 inside the memory access control device and is output to each port, so it conflicts with the request from the request source, so it must be suppressed during the execution of the diagnosis. Therefore, request hold F / Fs 160, 161, and
162 and 163. Further, since the diagnostic command is generated and executed in the memory access control device, the reply to this request should not be sent to each device. Therefore, reply suppression F / Fs 170, 17 corresponding to each device
1,172,173.

The diagnostic processing device requests the request hold F / Fs 160 to 163 and the reply suppression F / F for the diagnostic target.
170 to 173 are set, and the command to be executed next is instructed (specifically, the CS address in which the request to be processed is stored is given). When the diagnosis is completed, request hold F / Fs 160 to 163 and reply suppression F / F
F170 to 173 are cancelled, and the process ends in a state in which a request from the request source can be accepted.

The command for realizing such an operation is C
It is stored as a micro instruction inside S103,
The diagnostic processor executes by providing the trajectory signal and the address.

The AND date 105 generates AND conditions in the internal control field and the device designation field to generate a request hole setting signal, a cancel signal and a reply F / F setting signal, and a cancel signal, respectively. Furthermore, the reception buffer 110
.. to 113 are instructed to fetch the request code, request address, and request data in the CS read register 104.

Reference numeral 110 denotes a reception buffer that receives a request from EPU0. Normally, the request from EPU0 is input, but the request code / address valid bit in the CS read register 104 is "1" and the CS
When the device designation in the read register 104 is EPU0, the request code, address, and data output from the CS read register 104 are input. 111,11
Reference numerals 2 and 113 are reception buffers for EPU2, IOP0 and IOP2, respectively. 114 is a reception buffer 110
It is a buffer read register that receives an output and outputs it to the request processing unit 120. Reference numerals 115, 116 and 117 are buffer read registers for EPU2, IOP0 and IOP2, respectively.

Reference numeral 118 is a buffer read register 11
One request processing unit 1 that performs a busy check of the requests stored in 4, 115, 116, and 117
A selection circuit that outputs to 20 and a request processing unit 120 that inputs and processes the request of the output of the selection circuit 118,
The main memory 140 is read, a write request is output, and a reply data is received. Reference numeral 130 denotes a reply destination determination circuit, which determines the request source of the request and outputs each reply signal and reply data. Reference numeral 140 denotes a main storage device, which inputs the requester from the request processing unit 120 and returns reply data. 151,152,15
3, 154 are EPU0, EPU2, IOP0,
It is a reply data register for IOP2.

Reference numeral 160 denotes a request hold F / F which outputs a signal for suppressing the transmission of requests to EPU0.
It is set or canceled by the output of the read register 104. It is set before the diagnosis of EPU0 is made, and it is released after the diagnosis of EPU0 is completed. 161,1
62 and 163 are EPU2, IOP0 and IOP2, respectively.
Request hold F / F for.

Numeral 170 is a reply inhibition F / F for suppressing the reply signal to EPU0, and request hold F / F.
Similar to F160, it is set and released by the output of the CS read register 104. When this F / F or "1", the reply signal to EPU0 is suppressed at all.
This is because a contradiction occurs when a reply is sent to a request that is not issued by EPU0 during the execution of the diagnosis.
/ F160 and reply suppression F / F170 are set to "1", and are released at the same time when the diagnosis is completed. 171,17
Numerals 2 and 173 are reply suppression F / Fs for EPU2, IOP0 and IOP2, respectively.

Reference numeral 180 denotes a reply signal of the EPU0 from the reply destination determination circuit 130 and a request inhibition F / F17.
This is a reply valid register for ANDing the outputs of 0. Only when this output is "1", the contents of the reply data register 151 have meaning. 181,182,1
83 and 184 are EPU2, IOP0 and IOP, respectively
It is a reply valid register for 2.

Further, a bus is provided for reporting a failure of the memory access control unit to the diagnostic processing unit. Therefore, the diagnostic processing device can recognize the fault of the memory access control device by the presence or absence of the fault report after the diagnosis.

In this embodiment, all the hardware areas including each port portion are automatically included in the memory access control device alone while the system is being set up or after the operation processing device and the input / output processing device are not connected. The diagnosis of can be executed at high speed. Furthermore, since the (port) diagnosis can be performed on a plurality of devices at the same time, the processing can be performed at extremely high speed.

FIG. 3 shows another embodiment of the present invention. In this embodiment, an OR gate 500 is provided, and by logically adding the forced stop instruction from the diagnosis processing device with the output of the comparator, it is possible to freely stop at any timing even during diagnosis. Different from the first embodiment.

[0028]

As described above in the present embodiment, according to the present invention, before connecting the arithmetic processing unit and the input / output processing unit, the diagnosis of all the hardware areas including the interface part is performed in advance. There is an effect that the access control device itself can execute at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing detailed information of CS fields according to the present invention.

FIG. 3 is a block diagram of another embodiment of the present invention.

[Explanation of symbols]

 100 CS address register 101 CS write data register 102 CS write signal register 103 CS (CONTROL STRAGE) 104 CS read register 105 AND gate 110 reception buffer 111 reception buffer 112 reception buffer 113 reception buffer 114 buffer read register 115 buffer read register 116 Buffer read register 117 Buffer read register 118 Selection circuit 120 Request processing unit 130 Reply destination determination circuit 140 Main storage device 151 Reply data register 152 Reply data register 153 Reply data register 154 Reply data register 160 Request hold F / F 161 Request hold F / F 162 Request Ho F / F 163 Request hold F / F 170 Reply suppression F / F 171 Reply suppression F / F 172 Reply suppression F / F 173 Reply suppression F / F 180 Reply valid register 181 Reply valid register 182 Reply valid register 183 Reply valid register 210 Diagnosis start F / F 220 Comparator 300 Steady detection circuit 310 Steady signal 320 Steady signal 330 Steady signal 340 Steady signal 350 Request processing unit Steady signal 360 Steady detection circuit output 400 AND circuit 500 OR circuit

Claims (2)

[Claims] 1. A diagnostic method for a memory access control device for performing main memory access processing from a plurality of access request sources, wherein a request source device number, a request code, a request address, write data, and the inside of the memory access control device are internally provided. A control memory having a field for controlling, a steady detection means for detecting that there is no valid request in the memory access control device, and an instruction from the processing device when the output of the steady detection means is "1" A diagnosis start flag means which is sometimes set to "1", and an address register which, when the diagnosis start flag means is "1", sets an execution start address for diagnosis to the control memory and further updates the address. When the final address of diagnosis execution is detected, the diagnosis start flag means and the address register are detected. Comparator for resetting the output of the control memory, register means for storing the output of the control memory, request hold means for generating and outputting a request hold signal to the request source device indicated by the register means, and suppressing request acceptance, and the register means The reply inhibiting means for suppressing the sending of the reply signal to the request source device indicated by 7 and the request code, the address data from the request source and the request address, the request code and the data output from the register means are output by the register means. A reception buffer for selectively inputting, a selection means for performing a busy check of a plurality of requests from the reception buffer, further determining a priority and outputting one request, and a request processing means for processing a request to the selection means. Have memory access Memory access control device diagnostic method characterized in that it can be diagnosed at high speed not only at startup but also after startup. 2. The diagnostic method for a memory access control device according to claim 1, further comprising a forced diagnostic stop means, wherein starting and stopping of diagnostic execution can be freely set by the diagnostic processing device.