JP2013168173A - Memory controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide technique to avoid or reduce possibility of unintended rewriting of data, due to repeated readout of data from a nonvolatile memory.SOLUTION: A memory controller 2 widely performs error detection about non-readout addresses except readout addresses in all the memory cell array areas. Thus, by performing the error detection about an address at which error occurs without readout access, it is possible to detect occurrence of the error at the address. Accordingly, it is possible to prevent "read disturb phenomenon" in which repeated readout access to a readout address may probably cause the error at a non-readout address except the readout address.

Description

  The present invention relates to a technique for avoiding or reducing the possibility that data is unintentionally rewritten by repeatedly reading data from a nonvolatile memory.

  Among non-volatile memories, NAND flash memories are used in large quantities in SD memory cards and the like because they can be highly integrated and reduced in manufacturing cost by a simple circuit configuration, and can be easily written by users.

  Recently, NAND flash memory has been adopted in game machines and the like. When the NAND flash memory is used in a game machine or the like, writing does not occur and continuous reading occurs. That is, NAND flash memories are increasingly being used like ROM.

  However, in game machines and the like, since a specific program is often read repeatedly, it has begun to be pointed out that the program may be rewritten unintentionally. Such a phenomenon is called a “Read Disturb” phenomenon, and the mechanism in which this phenomenon occurs will be briefly described below.

  FIG. 11 is a schematic diagram of a NAND flash memory. The NAND flash memory includes bit lines 41 and word lines 42, 43, 44, memory cells 52, 53, selection transistors 54, and the like wired in a lattice pattern.

  Consider a case where binary data (“0” or “1”) stored in the memory cell 52 is read. In this case, the memory cell 52 is called a selected cell 52 and the memory cell 53 is called a non-selected cell 53. First, the bit line 41 to which the selected cell 52 belongs is specified by the selection transistor 54. Next, a low gate voltage V (Low) = 0 V is applied to the word line 42 to which the selected cell 52 belongs. Then, a high gate voltage V (High) to 5 V is applied to the word line 43 to which the non-selected cell 53 belongs.

  At this time, since the non-selected cell 53 is in a weak write state, electrons are trapped and accumulated in the floating gate of the non-selected cell 53. That is, by repeatedly reading the binary data stored in the selected cell 52, the threshold voltage of the non-selected cell 53 is shifted, and the binary data stored in the non-selected cell 53 is intentionally changed from “1” to “0”. There is a possibility of rewriting without.

  However, even if the binary data stored in the non-selected cell 53 is unintentionally rewritten, the function of the non-selected cell 53 can be restored when the data is erased all at once before being newly written. it can. However, when continuous reading occurs without writing, the function of the non-selected cell 53 cannot be recovered.

US Patent Application Publication No. 2005/0210184 JP-A-8-129510

  Patent Document 1 provides a means for avoiding a “Read Disturb” phenomenon by a control method inside a memory cell. However, the method disclosed here is a method applicable to a memory having a specific cell structure, and is not a method applicable to other cell structures. That is, it is not a measure that can avoid the “Read Disturb” phenomenon without depending on the cell structure of the memory.

  Patent Document 2 provides a means for performing error detection. However, the method disclosed herein is a method of detecting an error only for a read address, and is not a method of detecting an error for a non-read address other than the read address. In other words, it is not a measure that can avoid the “Read Disturb” phenomenon, because it is not detected that an error has occurred at that address until a read access is made to the address where the error has occurred.

  Accordingly, an object of the present invention is to provide a technique for avoiding or reducing the possibility that data is unintentionally rewritten by repeatedly reading data from a nonvolatile memory.

  In order to solve the above-described problem, the invention described in claim 1 is a memory controller that accesses a memory cell array in response to a memory access request from a host system, and whether or not the memory cell array is accessed. And an access determination means for detecting an error for an address selected using a predetermined algorithm at a timing when the memory cell array is not accessed. Is characterized in that if the data read from the memory cell array in response to a request from the host system is output to the host system, it is determined that the memory cell array is not accessed.

  According to a second aspect of the present invention, the memory controller according to the first aspect further comprises read address error detecting means for detecting an error for the read address.

  According to a third aspect of the present invention, in the memory controller according to the first or second aspect, the selected address error detection means selects an error detection start address at a certain error detection timing, and the certain error detection timing and Means for performing error detection on an address related to the error detection start address at a subsequent error detection timing.

  According to a fourth aspect of the present invention, in the memory controller according to the first or second aspect, the selection address error detection means selects an error detection start address every time an error detection timing arrives, and the error detection Means for performing error detection on an address related to the error detection start address at the timing.

  According to a fifth aspect of the present invention, in the memory controller according to the first or second aspect, the selection address error detection means selects an error detection start address each time an error detection timing arrives, and the error detection start Means for performing error detection on the address.

  According to a sixth aspect of the present invention, in the memory controller according to any one of the third to fifth aspects, the error detection start address includes an address determined by random number generation.

  According to a seventh aspect of the present invention, in the memory controller according to any one of the third to fifth aspects, the error detection start address is an address that is likely to cause an error due to a read access. It is characterized by including.

  According to an eighth aspect of the present invention, in the memory controller according to any of the third to fifth aspects, the error detection start address includes an address where an error has occurred due to a read access.

  According to a ninth aspect of the present invention, in the memory controller according to any one of the third to fifth aspects, the error detection start address includes an address assumed to have a high importance.

  According to a tenth aspect of the present invention, in the memory controller according to any one of the first to ninth aspects, the access determining means includes means for determining whether or not write data is output to the memory cell array. It is characterized by that.

  The invention according to claim 11 is the memory controller according to any one of claims 1 to 9, wherein the access determining means includes means for determining whether or not access is requested from the host system. It is characterized by.

  According to a twelfth aspect of the present invention, in the memory controller according to any one of the first to ninth aspects, the access determining means includes means for determining whether or not the power state of the host system has been switched. It is characterized by.

  According to a thirteenth aspect of the present invention, in the memory controller according to any one of the first to twelfth aspects, an error that further requests error detection information from the host system and notifies the host system of the error detection information. A notification means.

  According to a fourteenth aspect of the present invention, in the memory controller according to the thirteenth aspect, the error notification means is an information storage means for storing error detection information and the error detection information is requested from the host system, and the information storage is performed. Means for notifying the host system of error detection information stored by the means.

  According to a fifteenth aspect of the present invention, in the memory controller according to the thirteenth aspect, when the error notification means detects that an error has occurred in the memory cell array, the host system requests error detection information. Means for generating an interrupt.

  The memory controller according to the present invention performs error detection not only for the read address but also for non-read addresses other than the read address. Therefore, even if an error occurs at a certain address, it is detected that an error has occurred at that address by performing error detection without performing read access for that address.

  Since the memory controller according to the present invention performs error detection for all memory cell array regions including the read address and the non-read address, it is possible to prevent the “Read Disturb” phenomenon from proceeding due to subsequent error correction.

It is a block diagram which shows the component of a memory system. It is a figure which shows the error detection scan in a memory cell array. It is a figure which shows the error detection scan in a memory cell array. It is a figure which shows the error detection scan in a memory cell array. FIG. 5 is a diagram illustrating a “Read Disturb” phenomenon in an SLC NAND flash memory. FIG. 5 is a diagram illustrating a “Read Disturb” phenomenon in an MLC NAND flash memory. It is a figure which shows the flow of a process in which a host system acquires data. It is a figure which shows the flow of a process in which a memory controller detects an error. It is a block diagram which shows the component of a memory system. It is a figure which shows the flow of a process in which a memory controller detects an error. 1 is a schematic diagram of a NAND flash memory.

{First embodiment}
<Components of the memory system>
Hereinafter, the first embodiment will be described with reference to the drawings. In the “Read Disturb” phenomenon, when data stored in a read address is repeatedly read, data stored in a non-read address other than the read address may be rewritten unintentionally. However, since the memory controller according to the present embodiment performs error detection for all the memory cell array regions including the read address and the non-read address, it is possible to prevent the “Read Disturb” phenomenon from proceeding by subsequent error correction. .

  However, the memory controller cannot perform error detection on the memory cell array when read access, write access, or the like is performed on the memory cell array. Therefore, the memory controller performs error detection on the memory cell array when it is determined that read access, write access, or the like is not performed on the memory cell array.

  However, the time for the memory controller to perform error detection at once for all memory cell array areas is usually longer than the time from the end of read access, write access, etc. to the next start. Therefore, when the memory controller determines that no read access, write access, or the like has been performed on the memory cell array, the memory controller performs error detection on selected addresses in all memory cell array regions.

  FIG. 1 is a block diagram showing components of the memory system according to the present embodiment. The memory system is, for example, an information processing apparatus, and includes a host system 1, a memory controller 2, a memory 3, and the like. FIG. 1 shows a case where read access is performed to the memory cell array.

  The host system 1 outputs a read command, a write command, and the like to the memory controller 2 in order to request the memory controller 2 for read access, write access, and the like to the memory cell array 31 that is a component of the memory 3. In addition, the host system 1 outputs a Status Read command to the memory controller 2 in order to acquire error information in the memory cell array 31 from the memory controller 2.

  In response to a request from the host system 1, the memory controller 2 performs read access, write access, and the like to the memory cell array 31. Further, when the memory controller 2 determines that read access, write access, or the like is not performed on the memory cell array 31, the memory controller 2 performs error detection processing on the memory cell array 31, and stores error information in the memory cell array 31. . The memory controller 2 receives a request from the host system 1 and notifies the host system 1 of error information in the memory cell array 31.

  The memory 3 stores data to be processed by the host system 1 in the memory cell array 31. As the memory 3 according to the present embodiment, a single-level cell (SLC) type or a multi-level cell (MLC) type NAND flash memory can be used. However, it is possible to implement this embodiment in a non-volatile memory where data stored at non-read addresses may be rewritten unintentionally when data stored at read addresses is repeatedly read. is there.

  The host system 1 includes a CPU 11, an access controller 12, and the like. The CPU 11 sets a read command, a write command, a Status Read command, and the like in the access controller 12. The access controller 12 receives a command issuance instruction from the CPU 11 and outputs a read command, a write command, a Status Read command, and the like to the memory controller 2.

  The memory controller 2 includes a host interface 21, a command analysis unit 22, a memory access control unit 23, an output buffer unit 24, a scan control unit 25, an error detection unit 26, an error information storage unit 27, a memory interface 28, and the like. .

  The host interface 21 is an interface for exchanging commands and data between the host system 1 and the memory controller 2.

  The command analysis unit 22 inputs a command from the host system 1 and determines whether the command is a read command, a write command, or a Status Read command.

  The memory access control unit 23 inputs a read command, a write command, and the like from the command analysis unit 22 and performs read access, write access, and the like to the memory cell array 31. In addition, when the memory access control unit 23 determines that read access or write access to the memory cell array 31 is not performed, the memory access control unit 23 requests an error detection process for the memory cell array 31 to be described later.

  The memory access control unit 23 determines that read access to the memory cell array 31 is not performed by confirming that an output buffer unit 24 described later outputs read data to the host system 1. Further, the memory access control unit 23 determines that the write access to the memory cell array 31 is not performed by confirming that the output buffer unit 24 does not output the write data to the memory 3.

  The output buffer unit 24 receives read data from the memory 3 and temporarily stores it. Then, the output buffer unit 24 outputs the read data to the host system 1. The output buffer unit 24 receives write data from the host system 1 and temporarily stores it. Then, the output buffer unit 24 outputs the write data to the memory 3.

  In response to a request from the memory access control unit 23, the scan control unit 25 specifies a scan address that is an error detection target for the memory 3. In addition, the scan control unit 25 inputs a Status Read command from the command analysis unit 22 and notifies the host system 1 of error information in the memory cell array 31.

  When the scan control unit 25 designates a scan address that is an error detection target, the scan control unit 25 selects an address for error detection in all the memory cell array regions. A method for selecting an address at which the scan control unit 25 performs error detection will be described later with reference to FIGS.

  The error detection unit 26 inputs scan data that is an error detection target from the memory 3. Then, the error detection unit 26 performs error detection on the scan data. The error information storage unit 27 stores error information for the scan data.

  The memory interface 28 is an interface for exchanging addresses and data between the memory controller 2 and the memory 3.

  The memory access control unit 23 outputs a read address, a write address, etc. requested from the host system 1. The scan control unit 25 outputs a scan address selected from the memory cell array region.

  The memory controller 2 performs read access and write access to the memory cell array 31 by the memory access control unit 23 and acquisition of scan data by the scan control unit 25 independently in different periods. As a result, the memory controller 2 can prevent the “Read Disturb” phenomenon from proceeding without simultaneously accessing the memory cell array 31 and acquiring the scan data.

<Scanning method for error detection>
Next, a method for selecting an address at which the scan control unit 25 performs error detection will be described with reference to FIGS. First, a method in which the scan control unit 25 performs scanning from the scan start address will be described. Next, a method in which the scan control unit 25 selects a scan start address will be described.

  2 to 4 are diagrams showing error detection scans in the memory cell array 31. FIG. 2 to 4, the scan start addresses 311 to 316 are indicated by hatching. In FIG. 2 and FIG. 3, the scan addresses 311S to 313S other than the scan start address are indicated by hatching. That is, the scanning methods in error detection shown in FIGS. 2 to 4 are different from each other. The scan start address and the scan address may be selected in any unit such as a page unit of the memory cell array 31, a block unit, or a predetermined equal unit of one block.

  In FIG. 2, the scan control unit 25 selects the scan start address 311 when receiving an operation request from the memory access control unit 23. Then, the scan control unit 25 executes address increment from the scan start address 311 until a stop request is received from the memory access control unit 23.

  When receiving a stop request from the memory access control unit 23, the scan control unit 25 interrupts the address increment. Then, when the scan control unit 25 receives an operation request from the memory access control unit 23 next time, the scan control unit 25 resumes the address increment from the scan address where the address increment is interrupted. Further, the scan control unit 25 interrupts the address increment when it receives a stop request from the memory access control unit 23 next time.

  The scan control unit 25 selects a scan address thereafter by the method described above. That is, when the scan control unit 25 receives an operation request from the memory access control unit 23, each address scan is performed. Then, a continuous scan address 311S is selected from the scan start address 311 through a plurality of address scans.

  When the scan control unit 25 first selects a scan address when receiving an operation request from the memory access control unit 23, the scan control unit 25 selects the scan address selected last when the operation request was received from the memory access control unit 23 last time. Need to recognize. Therefore, if the scan control unit 25 or other components of the memory controller 2 have a means for storing the scan address selected last when the operation request was received from the memory access control unit 23 last time. Good.

  In FIG. 3, the scan control unit 25 selects the scan start address 312 when receiving an operation request from the memory access control unit 23. Then, the scan control unit 25 performs an address increment from the scan start address 312 until a stop request is received from the memory access control unit 23, and selects the scan address 312S.

  When receiving a stop request from the memory access control unit 23, the scan control unit 25 stops address increment. The scan control unit 25 selects the scan start address 313 when receiving an operation request from the memory access control unit 23 next time. Then, the scan control unit 25 performs the address increment from the scan start address 313 until the next stop request is received from the memory access control unit 23, and selects the scan address 313S.

  The scan control unit 25 selects a scan address thereafter by the method described above. That is, when the scan control unit 25 receives an operation request from the memory access control unit 23, each address scan is performed. In each address scan, successive scan addresses are selected from each scan start address. In the case of FIG. 3, unlike the case of FIG. 2, a continuous scan address is not selected from a single scan start address through a plurality of address scans.

  In FIG. 4, the scan control unit 25 selects the scan start address 314 when receiving an operation request from the memory access control unit 23. Then, the scan control unit 25 selects the scan start addresses 315 and 316 when receiving an operation request from the memory access control unit 23 at the next time and the next time.

  The scan control unit 25 selects a scan address thereafter by the method described above. That is, when the scan control unit 25 receives an operation request from the memory access control unit 23, each address scan is performed. In each address scan, only each scan start address is selected. However, a plurality of scan start addresses may be selected in each address scan. In the case of FIG. 4, unlike the cases of FIGS. 2 and 3, in each address scan, a continuous scan address is not selected from each scan start address.

  2 to 4, error detection can be performed for a wide range of areas not limited to read addresses in all memory cell array areas by multiple address scans. Further, as a method for selecting a continuous scan address from the scan start address, not only a method by address increment but also a method by address decrement can be mentioned.

  Furthermore, as a generalized method of selecting a continuous scan address from the scan start address, a method of selecting a scan address related to the scan start address can also be used. That is, after selecting the scan start address, the scan address is selected based on the scan start address and a predetermined rule. For example, when a scan start address and a scan address are selected for each page of the memory cell array 31, there is a method of selecting a scan page every several pages from the scan start page. Further, there is a method of selecting the first page of the second block and the first page of the third block as the scan page when the first page of the first block is selected as the scan start page.

  The scanning method in error detection shown in FIGS. 2 to 4 can be used in combination. For example, using the method of FIG. 2 first, then using the method of FIG. 3, and finally using the method of FIG. 4 until the memory system is powered on and then turned off. You can also.

  Next, a method in which the scan control unit 25 selects a scan start address will be described. In the present embodiment, the following addresses can be given as scan start addresses: (1) an address selected by random number generation, (2) an address at which an error is likely to occur, and (3) an error in the past. The generated address, (4) the address where important data is stored.

  A method by which the scan control unit 25 selects a scan start address by generating a random number will be described. The scan control unit 25 determines, by random number generation, what page of which block is selected as the scan start address. Therefore, error detection can be performed for a wide area of the memory cell array 31 by multiple address scans.

  Here, the scan control unit 25 may select a scan start address using a random number generated by the host system 1. In this case, the host system 1 may output a command and a random number to the memory controller 2. If the host system 1 recognizes the address where the important data is stored, the host system 1 may select the scan start address by generating a random number from the address where the important data is stored. Further, the scan control unit 25 may select a scan start address using a command output from the host system 1. In this case, the scan control unit 25 may generate a random number using the command bit string.

  A method in which the scan control unit 25 selects an address that is highly likely to cause an error as the scan start address will be described. This error includes an error due to a “Read Disturb” phenomenon. FIG. 5 is a diagram illustrating the “Read Disturb” phenomenon in the SLC NAND flash memory. FIG. 6 is a diagram illustrating the “Read Disturb” phenomenon in an MLC NAND flash memory.

  In FIG. 5, the SLC memory cell array 32 includes a plurality of blocks such as blocks 321, 322, and 323. Each of the blocks 321, 322, and 323 includes a plurality of pages such as hatched pages 321P, 322P, and 323P.

  When the memory controller 2 performs read access to the page 321P, unselected cells constituting pages other than the page 321P in the block 321 are in a weakly written state. That is, the “Read Disturb” phenomenon may occur in pages other than the page 321P in the block 321. A state where the “Read Disturb” phenomenon occurs is virtually shown by using a square mark in a block 321.

  When the memory controller 2 performs read access to the pages 322P and 323P, a “Read Disturb” phenomenon may occur in pages other than the pages 322P and 323P in the blocks 322 and 323, respectively. A state in which the “Read Disturb” phenomenon occurs is virtually shown using circles and triangles in blocks 322 and 323, respectively.

  When the read access to the page 321P is completed, the scan control unit 25 can select not only the page 321P as the read address but also the block 321 other than the read address as the scan start address. When the scan control unit 25 selects the scan start address in this way, the scan control unit 25 may be notified of the read address from the memory access control unit 23.

  In FIG. 6, the MLC memory cell array 33 includes a plurality of blocks such as blocks 331, 332, and 333. The block 332 includes a plurality of pages such as a hatched page 332P.

  When the memory controller 2 performs read access to the page 332P, the “Read Disturb” phenomenon may occur in a page other than the page 332P in the block 332 and a related block other than the block 332. In FIG. 6, blocks 331 and 333 are described as related blocks other than the block 332. The appearance of the “Read Disturb” phenomenon is virtually shown using square marks, circle marks, and triangle marks in blocks 331, 332, and 333, respectively.

  When the read access to the page 332P is completed, the scan control unit 25 can select not only the page 332P that is the read address but also the blocks 331, 332, and 333 other than the read address as the scan start address. In the case of FIG. 6 as well, as in the case of FIG. 5, the scan control unit 25 may be notified of the read address from the memory access control unit 23. The scan control unit 25 or other components of the memory controller 2 may be provided with a diffusion table indicating that the “Read Disturb” phenomenon may be diffused to related blocks other than the read block.

  A method in which the scan control unit 25 selects an address where an error has occurred in the past as a scan start address will be described. This error includes an error due to a “Read Disturb” phenomenon. The scan control unit 25 may acquire information about addresses where errors have occurred in the past from the error information storage unit 27 or the like. Then, the scan control unit 25 may select an address or the like where an error has occurred most frequently in the past as a scan start address.

  A method in which the scan control unit 25 selects an address where important data is stored as a scan start address will be described. Information regarding the address where the important data is stored may be provided in the scan control unit 25 or other components of the memory controller 2. Then, the scan control unit 25 may select an address at which data that is assumed to be most important is stored as a scan start address.

  As described above, the scan control unit 25 performs scanning from the scan start address by the three methods described with reference to FIGS. Further, as the method by which the scan control unit 25 selects the scan start address, there are the four types of methods described immediately above. For this reason, there are twelve types of methods by which the scan control unit 25 selects an address for error detection. These 12 kinds of methods can be used properly according to the purpose.

  For example, when the scan control unit 25 selects a scan start address by generating a random number and performs an address scan by the method shown in FIG. 2, error detection can be easily performed for a wide area not limited to the read address. Further, when the scan control unit 25 selects an address where important data is stored as a scan start address and performs an address scan by the method of FIG. 4, error detection is concentrated on the address where the important data is stored. Can be done.

<Process flow>
Next, the processing flow will be described in the following order: (1) command issue, (2) data acquisition, (3) error detection, and (4) error notification. FIG. 7 is a diagram showing a flow of processing in which the host system 1 acquires data. FIG. 8 is a diagram showing a flow of processing in which the memory controller 2 detects an error. The process flow shown below is a process flow when the memory cell array 31 is read-accessed. However, a substantially similar processing flow can be executed even when write access or the like is performed on the memory cell array 31.

  The CPU 11 sets a read command or a Status Read command in the access controller 12 (step S11). Then, the CPU 11 outputs a read command or a Status Read command issuance instruction to the access controller 12 (step S12). The command analysis unit 22 inputs a read command or a Status Read command from the host system 1 via the host interface 21 (step S13).

  When determining that the read command has been input, the command analysis unit 22 outputs the read command to the memory access control unit 23 (“read command” in step S14). If the command analysis unit 22 determines that the Status Read command has been input, it outputs the Status Read command to the scan control unit 25 (“Status Read command” in step S14).

  First, a case where the command analysis unit 22 inputs a read command will be described (“read command” in step S14). The memory access control unit 23 decodes the read command and extracts a read address (step S21). Then, the memory access control unit 23 outputs a read address to the memory 3 via the memory interface 28 (step S22).

  The output buffer unit 24 inputs read data from the memory 3 via the memory interface 28 (step S23). Then, the output buffer unit 24 outputs read data to the host system 1 via the host interface 21 (step S24). The CPU 11 inputs read data from the access controller 12 (step S25) and processes the read data.

  The memory access control unit 23 monitors whether or not the output buffer unit 24 is outputting read data to the host system 1 using an output monitoring line. When the output buffer unit 24 outputs read data to the host system 1, read access to the memory cell array 31 is not performed. The memory access control unit 23 makes an operation request to the scan control unit 25 when it is confirmed that the output buffer unit 24 outputs read data to the host system 1. Upon receiving an operation request from the memory access control unit 23, the scan control unit 25 starts scan control (step S41).

  However, even when the output buffer unit 24 is outputting read data to the host system 1, there may be a case where the scan control unit 25 cannot secure a time for performing the error detection scan. For example, this is a case where the memory access control unit 23 inputs a read command that the host system 1 continuously outputs as a series of flows. In this case, the memory access control unit 23 may determine that the read command is to be continuously output so that no operation request is issued to the scan control unit 25.

  Here, the scan control unit 25 performs the scan control in addition to the case where the output buffer unit 24 outputs read data to the host system 1 and the following cases. First, the output buffer unit 24 may not output write data to the memory 3. In this case, the memory access control unit 23 makes an operation request to the scan control unit 25 when it is confirmed that the output buffer unit 24 does not output write data to the memory 3.

  Next, the host system 1 may not request the memory controller 2 for read access or write access to the memory cell array 31. Further, the host system 1 may be turned on or off. Further, the host system 1 may request the memory controller 2 to access a backup device other than the memory cell array 31. Even in these cases, since the memory controller 2 includes a CPU monitoring unit that monitors the CPU 11, the CPU monitoring unit makes an operation request to the scan control unit 25.

  The scan control unit 25 generates a scan address by the method for selecting an address for error detection described with reference to FIGS. 2 to 6 (step S42). Further, the scan control unit 25 temporarily stores the scan address. Then, the scan control unit 25 outputs a scan address to the memory 3 via the memory interface 28 (step S43).

  The error detection unit 26 inputs scan data that is an error detection target from the memory 3 via the memory interface 28 (step S44). Then, the error detection unit 26 performs error detection on the scan data (step S45). Here, the error detection unit 26 notifies the scan control unit 25 of error information.

  If no error is detected in the scan data, the scan control unit 25 erases the temporarily stored scan address.

  If an error is detected in the scan data, the scan control unit 25 notifies the error information storage unit 27 that an error has been detected in the temporarily stored scan address (step S46). Then, the scan control unit 25 erases the temporarily stored scan address.

  Next, a case where the command analysis unit 22 inputs a Status Read command will be described (“Status Read command” in step S14). The scan control unit 25 acquires error information from the error information storage unit 27. Then, the scan control unit 25 outputs Status data as error information to the host system 1 via the host interface 21 (step S31). The CPU 11 inputs Status data from the access controller 12 (step S32), and prepares for subsequent error correction.

  Here, there are cases where the host system 1 outputs a Status Read command to the memory controller 2 as follows. First, a periodic trigger may occur in the host system 1. Next, the host system 1 may be turned on or off. Furthermore, the number of times that the host system 1 outputs a read command may exceed a predetermined number.

  Further, the scan control unit 25 may notify the host system 1 by generating an interrupt that the error information has been notified from the error detection unit 26. The host system 1 can input Status data as error information by outputting a Status Read command to the scan control unit 25. Further, when the host system 1 inputs the status data, it may be input directly from the error information storage unit 27 instead of input via the scan control unit 25.

  Furthermore, the scan control unit 25, the error detection unit 26, and the error information storage unit 27 may be arranged in the host system 1. In this case, the host system 1 outputs the scan address to the memory controller 2 in the scan control unit 25 when the read command and the write command are not output to the memory controller 2. In the host system 1, the error detection unit 26 performs error detection on the scan data, and the error information storage unit 27 stores the error information.

{Second Embodiment}
In the first embodiment, the error detection unit 26 performs error detection on the data stored at the scan address. Then, the host system 1 acquires error information for the data stored at the scan address. In the second embodiment, the error detection unit 26 performs error detection on the data stored at the scan address and the read address. The host system 1 acquires error information for the data stored at the scan address and the read address.

  First, a memory system according to the second embodiment will be described with reference to FIG. In particular, differences between the memory system according to the first embodiment shown in FIG. 1 and the memory system according to the second embodiment shown in FIG. 9 will be described.

  The memory access control unit 23 outputs the read address not only to the memory 3 but also to the scan control unit 25. The scan control unit 25 receives the read address from the memory access control unit 23 and temporarily stores it. Also in the second embodiment, similarly to the first embodiment, the scan control unit 25 selects a scan address by itself and temporarily stores it.

  The error detection unit 26 inputs not only scan data but also read data from the memory 3. The error detection unit 26 performs error detection on scan data and read data. The error detection unit 26 notifies the scan control unit 25 of error information regarding the scan data and the read data. The scan control unit 25 stores error information about the scan data and read data in the error information storage unit 27.

  Next, a flow of processing in which the memory controller 2 detects an error in the read data will be described with reference to FIG. The processing flow from when the CPU 11 sets the read command to the access controller 12 (step S11) until the memory access control unit 23 extracts the read address (step S21) is the same as that of the first embodiment. .

  In the first embodiment, the memory access control unit 23 outputs the read address only to the memory 3 (step S22). However, in the second embodiment, the memory access control unit 23 outputs the read address not only to the memory 3 (step S22) but also to the scan control unit 25. The scan control unit 25 receives the read address from the memory access control unit 23 and temporarily stores it.

  The process flow from when the output buffer unit 24 inputs read data (step S23) to when the CPU 11 inputs read data from the access controller 12 (step S25) is the same as that of the first embodiment.

  The error detection unit 26 inputs read data from the memory 3 (step S51). The error detection unit 26 performs error detection on the read data (step S52). The error detection unit 26 notifies the scan control unit 25 of error information regarding the read data.

  If no error is detected in the read data, the scan control unit 25 erases the temporarily stored read address.

  If an error is detected in the read data, the scan control unit 25 notifies the error information storage unit 27 that an error has been detected in the temporarily stored read address (step S53). Then, the scan control unit 25 erases the temporarily stored read address.

  The flow of processing from when the scan control unit 25 starts scan control (step S41) until the scan control unit 25 notifies the error information storage unit 27 that an error has been detected for the scan address (step S46). This is the same as in the first embodiment. The processing flow from when the CPU 11 sets the Status Read command to the access controller 12 (step S11) until the CPU 11 inputs the status data from the access controller 12 (step S32) is the same as in the first embodiment. is there.

  The host system 1 can acquire error information about data stored at the scan address and the read address from the single error information storage unit 27. The host system 1 can prepare for subsequent error correction based on the error information.

1 Host system 2 Memory controller 3 Memory 11 CPU
12 Access controller 21 Host interface 22 Command analysis unit 23 Memory access control unit 24 Output buffer unit 25 Scan control unit 26 Error detection unit 27 Error information storage unit 28 Memory interface 31 Memory cell array

Claims (15)

A memory controller that accesses a memory cell array in response to a memory access request from a host system,
Access determining means for determining whether or not the memory cell array is being accessed;
A selection address error detection means for detecting an error for an address selected using a predetermined algorithm at a timing when the memory cell array is not accessed;
With
The access determining unit determines that the memory cell array is not accessed when data read from the memory cell array in response to a request from the host system is output to the host system. And memory controller. The memory controller of claim 1, further comprising:
Read address error detection means for performing error detection on the read address;
A memory controller comprising: The memory controller according to claim 1 or 2,
The selection address error detection means includes:
Means for selecting an error detection start address at a certain error detection timing and performing error detection on an address related to the error detection start address at the certain error detection timing and the subsequent error detection timing;
A memory controller comprising: The memory controller according to claim 1 or 2,
The selection address error detection means includes:
Means for selecting an error detection start address each time an error detection timing arrives, and performing error detection on an address related to the error detection start address at the error detection timing;
A memory controller comprising: The memory controller according to claim 1 or 2,
The selection address error detection means includes:
Means for selecting an error detection start address each time an error detection timing arrives, and performing error detection on the error detection start address;
A memory controller comprising: The memory controller according to any one of claims 3 to 5,
The error detection start address is
An address determined by random number generation,
A memory controller comprising: The memory controller according to any one of claims 3 to 5,
The error detection start address is
Addresses that are likely to cause errors due to read access,
A memory controller comprising: The memory controller according to any one of claims 3 to 5,
The error detection start address is
The address where the error occurred due to read access,
A memory controller comprising: The memory controller according to any one of claims 3 to 5,
The error detection start address is
An address that is assumed to be of high importance,
A memory controller comprising: The memory controller according to any one of claims 1 to 9,
The access determination means includes
Means for determining whether write data is output to the memory cell array;
A memory controller comprising: The memory controller according to any one of claims 1 to 9,
The access determination means includes
Means for determining whether access is requested by the host system;
A memory controller comprising: The memory controller according to any one of claims 1 to 9,
The access determination means includes
Means for determining whether the power state of the host system has been switched;
A memory controller comprising: The memory controller according to any one of claims 1 to 12, further comprising:
Error notification means for requesting error detection information from the host system and notifying the host system of error detection information;
A memory controller comprising: The memory controller of claim 13.
The error notification means includes
Information storage means for storing error detection information;
Means for requesting error detection information from the host system and notifying the host system of error detection information stored by the information storage means;
A memory controller comprising: The memory controller of claim 13.
The error notification means includes
Means for generating an interrupt for requesting error detection information by the host system when detecting that an error has occurred in the memory cell array;
A memory controller comprising:

Images