JPH0282344A - Program debugging method for multiprocessor system - Google Patents

Abstract

PURPOSE:To obtain accurate trace information indicating the instruction execution order of plural processors by resetting a flag to release memory occupation after writing trace information in a memory area. CONSTITUTION:When the space number, the address, or the like of a test and set instruction of, for example, a processor 10a is detected at the time of system debugging, the processor 10a refers to a semaphore flag. When the flag is not detected, the processor 10a gets the occupation right of a memory device 12 by its own semaphore control part 16a. When the flag is detected, another processor 10b or 10c has the occupation right of the memory device 12, and therefore, the processor 10a gets the occupation right of the memory device 12 by its own semaphore control part 16a after release of the occupation right due to flag reset. When write of trace information to the memory area of the memory device 12 is terminated, an address pointer is updated, and the flag is reset to release the memory occupation right. Thus, accurate trace information for debugging which indicates the instruction execution order of plural processors is obtained.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Action Examples Effects of the Invention [Summary] Information processing in multiprocessor systems Regarding a debugging method that is performed by writing trace information obtained each time a test and set instruction is executed during instruction execution when debugging a program in a device to a trace area of memory, the order in which instructions are executed by multiple processors is shown. A method for debugging programs in a multiprocessor system having a semaphore control unit that performs read, modify, and write operations on data stored in a semaphore area of a memory device, with the aim of obtaining a debugging method that requires accurate trace information. Among the instructions executed by the processor, trace information is detected for the test and set instruction, and after detecting the information, the semaphore flag is referred to, and when the flag is not detected, the flag is set and memory is occupied, and the flag is detected. Sometimes, it is configured to wait for a flag reset, set a flag, occupy the memory, write trace information in the memory area, and then reset the flag and release the memory occupation.

[Industrial application field]

The present invention provides a multiprocessor system that performs multiprocessing by writing trace information obtained each time a test and set instruction is executed during instruction execution during debugging and debugging of a program in an information processing device of a multiprocessor system to a trace area of a memory. This invention relates to a method for debugging programs in processor systems.

When debugging macro code as a system program or user program in a multiprocessor system, in a program that accesses shared memory using semaphore control, the area can only be accessed by a specified number of processors at a time. If this happens, waiting and access errors may occur, and sometimes deadlocks may occur. In this case, in order to analyze how deadlocks etc. occur, the trace information of the test and set instruction is written to a memory device, and after the trace is completed, it is output to a display device or printer, etc. I am trying to check the execution order.

[Conventional technology]

FIG. 7 is a block diagram of a conventional multiprocessor system. A plurality of instruction processors (IPUs), for example, three processors 10a, for a memory device 12 as a system storage (SS),
10b and 10c are connected, and external devices such as disks and magnetic tapes are further connected via a system processor (SPtl) 13 for interface.

When a conventional single-processor debugging method is applied to such a multiprocessor system, the result is as follows.

First, as shown in the memory map of FIG. 8, for example, the memory area of the memory device 12 is composed of a macro program to be traced (displayed in the upper row), a data area (lower row), and a trace data area specified by an address pointer. Ru. Here, symbols such as MOV indicate commands, and "rTS command" indicates a test and set command. The shaded area illustrates the opcode address. The three blocks at the bottom indicate areas to be acquired.

When the space number and address of the macro code of the macro instruction are obtained by executing the first test and set instruction in a specific processor, for example, the processor 10a, the space number 1, for example, is stored in the first trace data area indicated by the address pointer. , trace information is written as address 1, and then trace information obtained by execution of a test and set instruction by the same processor 10a, another processor 10b or 10c is indicated by updating the address pointer, and the next trace data area, For example, it is sequentially written to space number 2 and address 2.

[Problem to be solved by the invention]

However, in the conventional debugging method for multiprocessor systems described above, multiple processors write trace information to the same trace data area, so each processor writes a trace consisting of a space number and address to the memory area indicated by the address pointer. While writing information or updating the address pointer, another processor may write trace information or update the address pointer by interrupting the same address pointer. There is a problem in that trace information indicating the order in which macro instructions are executed by different processors cannot be obtained.

Of course, it is possible to allocate separate memory areas for multiple processors and write trace information, but
The mutual execution order of processors becomes unclear.

Furthermore, if the address of the area to be tested and set is an index modification that changes depending on the contents of the index register, it is unclear from the trace information which shared area is being accessed.

An object of the present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to effectively utilize a semaphore control function provided as hardware in a microprocessor, etc., to obtain accurate trace information indicating the order of instruction execution by a plurality of processors. The objective is to obtain a debugging method for multiprocessor systems that requires

[Means to solve the problem]

A flowchart illustrating the process of the present invention in FIG. 1 and FIG.
Description will be made with reference to a block diagram of a device to which the present invention is applied. A system in which the method of the invention is used includes a memory device 12 and a plurality of processors 10a, 10b, and 10c.
Each processor has semaphore control units 16a and 16 as hardware executed by microinstructions.
b, and 16C are provided. Each semaphore control unit is
Semaphore area 14 serving as a specific address of memory device 12
It has the ability to use microinstructions to execute a read/modify/write operation that flags and writes to specific bits after reading data stored in the processor. Reads, writes, and interrupts are disabled.

The present invention makes use of the above semaphore control function to detect the space number, address, operand address, and processor number of a test and set instruction among the execution instructions of a specific processor during system debugging (Sl
) The processor refers to the semaphore flag (S2).

When the flag is not detected, the processor acquires the exclusive right to the memory device 12 through its own semaphore control (S3), and when the flag is detected, since another processor has the exclusive right to the memory device 12, it waits for the exclusive right to be released by resetting the flag. After acquiring the exclusive right to the memory device 12 through its own semaphore control (S3), trace information is written to the memory area of the memory device 12 indicated by the address pointer (S4).
). I. When the writing of race information is completed, the address pointer is updated (S5: After I, the flag is reset (S
6) Release the memory exclusive right.

[For production]

When a processor writes trace information to the memory device 12, it sets a semaphore flag under its own semaphore control and acquires exclusive rights to the memory device. Memory access by other processors is prohibited while the pointer is being updated, and it is possible to reliably prevent trace information of other processors from being written to the memory area indicated by the same address pointer or from updating the address pointer. Accurate trace information indicating the order in which macro instructions are executed by multiple processors can be obtained.

On the other hand, if the flag is set when the semaphore flag is referenced, other processors can trace it.10) It is found that information is being written or the address pointer is being updated, and it waits for the semaphore flag to be reset and then controls its own semaphore. Also, since trace information is written, it is possible to obtain trace information that accurately indicates the order in which macro instructions are executed by a plurality of processors.

Note that there is a limit to the trace information storage area of the memory device, so when the storage area becomes full, if cyclic specification is specified, the address pointer is initialized and trace information is written from the beginning, and if cyclic specification is not specified, trace information is written from the beginning. Stop debugging.

〔Example〕

FIG. 3 is a block diagram of an embodiment showing the hardware of a semaphore control unit on the processor side used in the method of debugging a program in a multiprocessor system of the present invention.

In FIG. 3, a processor 10a is connected to a memory device 12 as a system storage (SS) shown in FIG. 4 through a memory data bus and a memory address bus. A plurality of other bromo nosas are similarly connected to the memory device 12. processor 10
Write (write) from a to the memory bus Has write register 20 and ECC (error correction)
An ECC code generation circuit 26 of circuit 24 is provided.

On the other hand, a memory data register 28, an error detection and correction circuit 30 of the ECC circuit 24, and a read data register 32 are provided in a read bus system from the memory data bus to the Bromo Nosa 10a.

The configuration of the read system and write system as described above is the same as that of normal Bromo Nosa node hardware equipped with the ECC circuit 24, but in addition to this, in order to realize the debugging method of the present invention, Bromo A data modify circuit 34, a data selector 36, and a flag register 38 for detecting and storing a semaphore flag from specific bits of read data stored in the read data register 32 are provided for the nose 10a.

That is, the data modification circuit 34 is the ECC circuit 2.
The circuit is provided as a circuit that bypasses the code data obtained through the error detection and correction circuit 30 of No. 4 to the write system equipped with the ECC code creation circuit 26, and when it receives the semaphore control signal from the processor 10a, the semaphore of the memory device 12 is A specific bit read from the area 14, for example, the most significant bit, is set as a semaphore pin and a flag "1" is set to modify the data.
Upon selection of the output of the data modifying circuit 34 of the data selector 36 by the semaphore control signal applied via the 'ECC circuit 24, modified data is written into the semaphore area of the memory. In addition, the data modification circuit 34 sets the semaphore flag “1j” to the most significant bit.
The correction data that has been set is written to the semaphore area of the memory device, and at the same time is stored in the read data register 32 via the memory data register 28 and the error detection correction circuit 30, and the semaphore flag of the most significant bit of the read data register 32 is set. It is configured so that it can be detected and stored in the flag register 38.

Semaphore control using a semaphore control unit configured with such hardware, that is, read modification that reads data stored in the semaphore area of a memory device, sets a flag "1" to the most significant bit, and writes it again. - Write operations can be performed by executing microinstructions that perform semaphore control when trace information is obtained by executing macroinstructions during debugging.

FIG. 4 is an explanatory diagram of a memory map of the memory device 12 into which trace information by the processor 10a of FIG. Consists of trace data area.

FIG. 5 is a timing explanatory diagram of semaphore control by the hardware shown in FIG. 3. Time t.

When the program 10a executes the test and set instruction in the steps up to and the trace information consisting of the space number, address, operand address, and processor number of the macro instruction is obtained, time 1. Memory installation at the timing of? Outputs bus requests for lf 12 and semaphore access for semaphore control. In response to this semaphore access at time t, the processor 10a specifies the address of the semaphore area 14 shown in FIG.
The read data of the semaphore area 14 is obtained from 4, and at the next time t5, if the flag of the upper bit of the semaphore data is "0", the flag is set to "1" and the memory device 12 is read at the timing of time t6. semaphore area 1
The write data for writing the modified data is transferred to the memory at time t, and the semaphore access is completed at time t. During the semaphore-controlled read/modify/write operations from time t2 to t7, the memory bus is occupied, and during this time, hardware or software interrupts from other processors are prohibited.

Next, the depacking method in the embodiment will be explained with reference to the operation flowchart of FIG. First, the macro instruction executed by processor loa shown in FIG. 3 is a test and set instruction, and when trace information consisting of the space number, address, and processor number of the macro instruction is detected,
The operating process of FIG. 6 is executed. That is, in step Sll in the operation process, it is first determined whether it is a test and set instruction, and if it is a test and set instruction, it is determined in step S1.
If the test and set command is successful, the process proceeds to step 319. In step S12, it is determined whether or not the memory bus is occupied by another processor. If the bus is in an open state, the process proceeds to step S13, where semaphore control for performing read/modify/write operations is executed.

The processor 10a specifies the address of the semaphore area 14 (see FIG. 4) of the memory device 12 using the memory address bus, and transfers the semaphore data to the memory data register 2.
8, error detection correction circuit 3 of ECC circuit 24
0 is stored in the read data register 32, and at the same time the data modifying circuit 34
Store in. At this time, if the error detection and correction circuit 30 detects a 1-bit error, correct read data with the 1-bit error corrected is provided.

Since the data modifying circuit 34 is given a semaphore control signal by the processor lOa through semaphore access, it is determined whether a semaphore flag is set in a specific bit of the read data, for example, the most significant bit.

If the flag "1" is set in the most significant bit at this time, it is determined that the trace data is being updated as shown in step S14 in FIG. 6, since the trace data is being updated by another processor. Step Sll again
Return to

The semaphore flag is "0" or the update of trace data by another processor has finished and the semaphore flag is "0".
”, the data modify circuit 34
The semaphore flag is set to "1" in the most significant bit and the modified data is sent to the semaphore area 14 of the memory device 12 via the data selector 36 selected by the semaphore control signal and the ECC code creation circuit 26 of the ECC circuit 24. Performs writing semaphore control.

To determine whether the trace data is being updated by another processor in step S14, the most significant bit of the read data of the semaphore area 14 stored in the read data register 32 is stored in the flag register 38, and the bits of this flag register 38 are By looking at "1" or "0", the processor 10a determines whether to perform its own semaphore control or wait for the completion of update of trace data of other processors to perform semaphore control.

In the process up to step S14, the semaphore flag is set to "1" in the semaphore area 14 of the memory device by its own semaphore control.
When data writing is completed, the next step S
15, the space number, address, target address, and processor number of the macro instruction detected as trace information are written into the memory area specified by the address pointer.

Next, as shown in step S16, the address blank is re-sent (updated) to specify the memory area for the next trace information, and the process proceeds to step S17, where it is determined whether the write area for trace information is full or not. . If there is space in the write area for trace information, the process advances to step 318 and the semaphore flag set by the semaphore control in step S13 is set.
1" to "0" and release the path exclusive right for updating trace information. When the bus exclusive right is released in step 318, the next instruction code is fetched in step S19, the instruction code fetched in step S20 is decoded, and the instruction code is executed in step S21, thereby obtaining the next trace information. Then, the process returns to step S12 again.

When the trace information writing area is full in step S17, the process advances to step S31 and it is determined whether the trace information writing is in the cyclic designation mode. In the cyclic specification mode, after initializing the address pointer in step S32, the memory exclusive right is released by resetting the semaphore control flag in step 31B, and in step S3
In steps 19 to S21, the next instruction is fetched, decoded, and executed.

That is, in the cyclic specification mode, when the trace information write area becomes full, the l/race information resulting from the execution of the next macro instruction is stored by rewriting the first area specified by address pointer initialization.

If it is not the cyclic designation mode in step S31, the memory exclusive right for updating trace information is released in step S33, and debugging is stopped by a stop command in step S34, and the operator is notified of this fact.

The above-mentioned embodiment describes a case in which hardware for performing semaphore control is provided on the side of a plurality of processors, but in another embodiment, hardware for realizing the semaphore control function is provided on the memory device side. You can. In this way, when hardware for semaphore control is provided in the memory device, only one semaphore control hardware is required, which simplifies the hardware configuration compared to when hardware is provided for each processor. be able to.

〔Effect of the invention〕

According to the present invention, memory access by other processors is prohibited while trace information is being updated by a specific processor using a semaphore control function, and trace information for accurate debugging that indicates the instruction execution order of multiple processors is used. can be obtained.

That is, it is possible to know the processor number that acquired the area that is the test and set instruction, the address where the instruction exists, the number of times the area was acquired, and the number of loops due to the test and set.

[Brief explanation of the drawing]

Fig. 1 is a flowchart of the processing process of the present invention, Fig. 2 is a block diagram of a system to which the present invention is applied, and Fig. 3 is a block diagram of the hardware of the semaphore control unit of the system that performs the method of one embodiment of the present invention. Figure 4 is a diagram explaining the memory map by debugging of the embodiment, Figure 5 is a diagram explaining the timing of semaphore control in the embodiment, Figure 6 is an operation flowchart of the method of the embodiment, and Figure 7 is the conventional method. FIG. 8 is a block diagram illustrating a multiprocessor system, and FIG. 8 is a diagram illustrating a memory area of a memory device. In the figure: 10a, 10b, 10cm--processor, 1
2...Memory device, 13...System processor, 14...Semaphore area, 16a, 16b, 16cm--semaphore control unit, 20...Write data register, 24...EC, C circuit, 26... ECC code creation circuit, 28... Memory data register, 30... Error detection correction circuit, 32... Read data register, 34... Data modify circuit, 36... Data selector, 38...Flag register.

Claims (1)

[Claims] A read method for each of a plurality of processors (10a, 10b, 10c) that reads data stored in a semaphore area (14) of a memory device (12) and then sets a flag and writes to a specific bit. - Semaphore control unit (16a,
16b, 16c), and in which interrupts from other processors are prohibited during read/modify/write operations by the semaphore control unit, the method includes: Among the instructions executed in S1, trace information including the space number and address where the instruction exists, the address targeted by the instruction, and the processor number is detected according to predetermined conditions for only the test and set instruction (S1 ), refers to the semaphore flag after detecting the trace information, and when the flag is not detected, sets the flag using the semaphore control to acquire memory exclusive rights, and when the flag is detected, waits for the flag to be reset and sets the flag using the semaphore control. After acquiring the memory exclusive right, the trace information is written in the memory area indicated by the address pointer (S2, S3, S4), and after the writing, the address pointer is updated (S5).
) and reset the semaphore flag (S6).
, a method for debugging a program on a multiprocessor, characterized in that memory ownership is released.