JPH0363853A - Sac instruction control system - Google Patents

Abstract

PURPOSE:To accelerate the processing speed of a SAC(Set Address space control) instruction by performing the space switching event program interruption processing of the SAC instruction without increasing the number of cycles of a CPU operation essentially. CONSTITUTION:The system is equipped with an operand address register(BOAR) 1 of B cycle, a register(ARCB) 2 which holds the content of an operand, an arithmetic unit 3, a latch(ARC 12) 4, and a program state word(PSW) 5, etc. And the fact that space switching occurs between a home space mode and another space mode during performing the processing of the SAC instruction is detected with hardware, and it is latched with the latch 4. A corresponding control register 13 is selected corresponding to the content of the latch 4, and the content is held with a universal register, and when program interruption due to a space switching event occurs, the content of the universal register is stored at the prescribed position of a main storage as an address conversion exceptional identifier. In such a way, the SAC instruction is processed at high speed.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a virtual memory type information processing device that enables access to multiple address spaces by rewriting specific bits of the PSW, with the aim of speeding up the processing of SAC instructions. 1. A circuit that detects the occurrence of switching between the home space mode and another space mode during processing of the S AC instruction and holds the result, and a circuit that stores all "0" data or a control register based on the above detection result. a circuit that selects one of the contents of A and stores it in general-purpose register The present invention is constructed by providing means for storing the contents of the general-purpose registers x and y in a predetermined area on the main memory as an identifier of an address translation exception when a program interrupt occurs due to a space switching event.

[Industrial Application Field] The present invention relates to an instruction control method in an information processing device having a virtual storage device consisting of a plurality of address spaces specified by specific bits in a program state word (PSW), and in particular, , C (Set Address 5pace) for rewriting specific bits in the above PSW.
(control) relates to a control method for commands.

[Prior Art] ``Recent demands on information processing devices include an increase in the amount of data to be processed. This is especially noticeable in data pace systems. In line with this demand, there is a desire to realize an architecture that allows a user program to directly access data in multiple address spaces, exceeding the address space limitations of conventional virtual storage devices. The product has appeared.

That is, in a conventional information processing device having virtual memory, only accessing data within a single address space specified by a control register is permitted. Therefore, in order to refer to data in multiple address spaces, it is necessary to change the contents of the control register, which is under the control of the operating system. Under such control, user programs were not allowed to directly process data across multiple address spaces.

However, as the demand for expansion of virtual memory space increases, it becomes necessary to provide control that allows user programs to access multiple address spaces with different pace register numbers beyond the range of the given address space. reached.

As a mechanism for this purpose, the following method can be considered.

In other words, for multiple address spaces used by users,
A segment table is prepared for each, and a segment table origin (S
It has a plurality of T○>, and which one to use is determined by the contents of the access register indexed by the pace register number used in the access. The method for determining this is that an access list in the real storage space is indexed based on the contents of the access register, and which ST○ is used to access the virtual storage space using the pace register number.

The pace register number designation part is located at a limited bit position of the instruction word, and the contents of the register selected according to the contents thereof are input to an adder circuit for generating an effective address.

In the method described above in which data in multiple address spaces is processed by access register conversion using access registers, there are two types: access register mode in which access register conversion is performed and home space mode in which the control program places control blocks. These modes can be switched using the program-like 11 words (PSW) using the SAC command.
) is controlled by rewriting specific bits.

When the CPU accesses the virtual storage space, its mode is set by the value of specific bits (16 bits and 17 bits here) of the program state 1t (PSW) (hereinafter 16 bits and 17 bits are 16:17). When 16:17 is "00.'", it is called the primary address space mode, and both instructions and operands are placed in this space.

The STO resides in a specific control register (here CRI).

When 16:17 is "10", it is called secondary address space mode, and only operands are placed in this space. ST
O is placed on a CRT. This space contains special commands (MV
CP,MVC3)l,: can only be accessed.

When i6:17 is "01", it is called access register mode, and only operands are placed in this space. The STO of each space is specified by a corresponding access register. This space can be accessed by general commands.

When 16:17 is "11", it is called a home address space, and both instructions and operands are placed in this space. STO is another specific control register (here CR1
3) Placed in the room.

Furthermore, within one task, the CRI is changed by executing pc and p'r, which are instructions for switching the primary address space. That is, even when the primary address space is switched, the program can perform common control in the home space.

Added to the SAC instruction is the ability to cause a space switch event program interrupt to record a space switch event to or from home space mode.

The above space switching event is a PIIOGRA with space switching.
M CALL, PR port GRAM TR with space switching
Upon completion of ANSFER, it is recognized if any of the following is true:

(1) Prior to the operation, the primary space switch event control bit in bit 0 of the control register (CRI) is "1".

(2) After the operation, the space switch event control bit is “1”.

(3) A PER event has been reported.

Space switching event is R1 to SB↑80! SS5PACB
Upon completion of C0NTR0L, it is recognized if any of the following is true when the CPU switches from home space mode to another mode or from another mode to home space mode.

(1) The primary space switching event control bit in bit 0 of the control register (CRI) is "1".

(2) The home space switching event control bit in bit 0 of the control register (CR13) is "1".

(3) A PER event has been reported.

SA switched to PC, PR and home space mode
When executing a C instruction, the old PASN (PRIMARY AD port R) in the control register (CR4 in this case) before execution is
BSS 5PACB N11M8[! R) is set to a specific address in the main memory (here, address 92 (HEX)), and the primary space switching event control bit is set to a specific address in the main memory (here, address 90).
address (HEX)).

This makes it possible to specify the address space before the space switching event.

When the SAC instruction is executed after switching from the home space mode, zero is stored at address 92 (HEX) and the home space switching control bit is stored at address 90 (HEX).

Using space switch events, a control program can receive and take control each time the program enters or exits a particular address space.

Spatial switch events are useful for providing permission checking functionality in programs, for recording additional tracking information, or for enabling or disabling CPtJs for PER and tracking.

[Invention tries to solve! 1111] When a space switching event program interrupt occurs due to a SAC instruction, C is used as a conversion exception identifier when switching to home space mode.
The contents of R4 and bit 0 of CRI are stored in a predetermined main storage area, and when switching from the home space mode, zero and bit 0 of CR13 are stored in a predetermined main storage area. In the conventional processing method, such processing was performed by identifying the mode after space switching in the microprogram routine that processes program interrupts, selecting the conversion exception identifier, and storing it, which resulted in an increase in unnecessary processing. This resulted in a decrease in performance.

That is, the condition that causes the SAC instruction to cause a new space switching event program interrupt is the PC.

Since it is almost the same as the PT instruction, existing microprogram code can be used.

Therefore, in the conventional technology, when implementing a new function in the SAC instruction, changes are mainly made in the program interrupt routine, which requires a considerable amount of processing.

FIG. 3 is a flowchart when the space switching event program interrupt of the SAC instruction is realized under microprogram control.

As shown in the figure, check whether the interrupt was a SAC instruction or not.
Overhead occurs due to the two-branch judgment of whether or not it is a home space. In the figure, the branch flow when the instruction is not an SAC instruction corresponds to the processing for the PC and PT instructions, and the contents to be stored at addresses 90 to 92 are already held in work register 0.1 during the execution of the PC and PT instructions. .

FIG. 4 is a time chart when the space switching event program interrupt of the SAC instruction is realized under microprogram control. As shown in the figure, four flows are required for branching.

The SAC instruction is originally a PSW for switching address spaces.
This is an instruction provided to rewrite specific bits (in this case, 16 bits and 17 bits).

In other words, a load PSW instruction is normally used to change the contents of a PSW, but since this requires a lot of processing time, in order to quickly switch the address space mode, it is necessary to load the corresponding bit without replacing the entire PSW. It is set to rewrite only the

However, as mentioned above, the process of storing the contents of a specific control register at a specific address in main memory is used as a means to record the history (logging) of address space switching events other than the intended operation. The problem was that it took a lot of time.

SUMMARY OF THE INVENTION In view of these conventional problems, it is an object of the present invention to provide a means for realizing SAC instruction space switching event program interrupt processing without increasing the number of CPU operation cycles.

[Means for Solving the Problems] According to the present invention, the above objects are distantly related to the means described in the claims.

That is, the present invention provides a programmable tIAF) (PSW
) The program state in a virtual memory information processing device configured to enable access to a plurality of address spaces including a home space by switching the address space mode based on specific 2-bit information in ) This is a control method for SAC commands to rewrite specific 2-bit information in a word. A circuit that detects whether switching from space mode to home space mode has occurred and holds the result, and the above detection result, all “0”
” or the contents of control register A and stores it in general-purpose register When a program interrupt occurs due to a space switching event, the contents of general-purpose register This is a SAC command control method comprising means for storing information in the SAC command.

[Function] In the present invention, the above means detects by hardware the occurrence of space switching between the home space mode and another space mode during processing of the SAC command, and holds it in a latch; Selecting a corresponding control register according to the contents of the latch and retaining the contents in a general-purpose register;
When a program interrupt occurs due to a space switching event, the contents of the general-purpose register are stored at a predetermined location in the main memory as an address translation exception identifier.

Since all of these are performed by hardware operations, high-speed processing can be expected.

[Embodiment] FIG. 1 is a diagram showing the configuration of an embodiment of the present invention, in which 1
is the operand address register (BOAR) of the B cycle.
), 2 is a register (AR
CB), 3 is the arithmetic unit, 4 is the latch (ARC12
), 5 is PSW.

6 to 10 are AND circuits, 11 is a NAND circuit, 12 is a latch, and 13 is a control register.

FIG. 2 is a time chart showing the operation of the above embodiment.

Hereinafter, the operation of the embodiment will be explained using the above two figures.

The SAC instruction in the present invention operates as shown in the time chart of FIG.

Bit 22゜bit 23 of operand address register 1 (BOAR) of B cycle in the first flow (a)
is like a program! ! ! ! ! It is inserted into the address space control bit of (PSW) 5. In addition, a register 2 (
ARCB) and the contents of latch 12 (SS-TO-HO
ME-LCH> is set.

Through the flows in (C) and (d) below, the content selected as the conversion exception identifier is set in the work register 0.1 (in the first flow, from the time the PSW is set in (a), the instruction is re-fetched. is performed, so the subsequent flow does not affect the processing speed of the SAC instruction.)

The setting of the latch 12 (SS-To-HOME-LCH) will be further explained with reference to FIG.
Cycle operand address register 1 (BOA
bit 22 of R). In the E cycle of setting bit 23 in PSW, when switching to the home space mode (both bits 16 and 17 of psw are "l") is detected, latch 12 (SS-To-HOME-LCH,
) Two cassettes are placed.

The output of latch 12 is the signal E-μ-T according to the microinstruction.
Retained by AG.

Then, the output of the latch 12 and the signal B based on the microinstruction
A signal for selecting a desired control register from among the control registers 13 by -μ-TAG is applied to the AND circuit 9. It is generated using the AND circuit 10, and the contents of the control register selected thereby are sent to the arithmetic unit.

As described above, according to the present invention, it is necessary to judge "whether or not the interrupt was an SAC instruction" and "whether or not it is the home space mode", which was previously necessary, and the corresponding processing by the microprogram. Since the operation is performed only by hardware, it becomes possible to execute SAC instructions at high speed.

[Effects of the Invention] As explained above, according to the present invention, the SAC instruction space switching event program interrupt processing can be performed without increasing the actual number of cycles of the CPU operation. This has the advantage of speeding up the process.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the configuration of an embodiment of the present invention, Fig. 2 is a time chart showing the operation of the embodiment, and Fig. 3 is a flowchart when the space switching event program interrupt of the SAC instruction is performed by microprogram control. , FIG. 4 is a time chart when the space switching event program interrupt of the SAC command is performed under microprogram control. 1...B cycle operand address register (BOAR), 2...Register for holding operand contents (ARCB), 3...Arithmetic unit, 4.12... ...Latch, 5...
・PSW, 6 to 10...AND circuit, 11...
... NAND circuit, 13 ... Control register

Claims (1)

[Claims] By switching the address space mode according to information of specific bits in the program state word (PSW),
Control of SAC commands for rewriting specific bit information in the program state word in a virtual memory type information processing device configured to allow access to multiple address spaces including a home space. The method detects whether a switch from a home space mode to another space mode or from another space mode to a home space mode occurs during processing of a SAC command, and detects the result. a circuit that holds , and selects either all “0” data or the contents of control register A according to the above detection result,
a circuit for storing in general-purpose register x, and selecting either the contents of control register A or the contents of control register B according to the detection result,
a circuit for storing in general-purpose register y; and means for storing the contents of general-purpose register x and general-purpose register y in a predetermined area on main memory as an identifier of an address translation exception when a program interrupt occurs due to a space switching event. SA characterized by comprising
C command control method.