JPH03113646A - Trace circuit - Google Patents

Abstract

PURPOSE:To effectively use a memory by detecting a loop which is previously registered on a real time basis when it exists in the middle of trace and preventing the execution part of the loop from being stored overlapping in the trace memory. CONSTITUTION:When a real execution address reaches a loop leading address which is previously registered in a loop address register 5, it is detected whether it reaches the address for the first time as the result of the sequential execution of the program or as the result of branching to the head of the loop by a branching command for executing the loop. When it branches to the head of the loop, the execution result is not written into the new address of the trace memory 1 but it is overwritten in the address where data obtained when the loop is sequentially executed for the first time is stored. Thus, the substantial decrease of effective trace data owing to the execution of the loop is prevented and the trace memory is used at a maximum.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a trace circuit, and particularly to a program execution trace circuit included in an in-circuit emulator for a microprocessor or the like.

(Conventional technology) The trace circuit of a conventional in-circuit emulator is
It constantly traces the microprocessor's bus accesses from the start of tracing, stores them cyclically in the trace memory (which can usually store a number of steps), and stops writing to the trace memory when the trace end condition is met. - It is designed to be done.

(Problem to be Solved by the Invention) Normally, many instructions are executed between the location to be investigated and the location where the trace end condition is met. If a loop is executed during that time, with the conventional method, only the loop execution results remain in the trace memory, making it sometimes impossible to trace the part you want to investigate.

For example, as shown in FIG. 5(a), it is assumed that the loop (between G and H) needs to be executed many times before the trace condition is satisfied. In this case, if you write all the program execution results to the trace memory, and if the capacity is exceeded, you go back to the first memory address and override it, eventually only the loop execution results will be recorded, and you will not be able to find the part you want to examine. The execution result of F disappears and cannot be traced.

Further, in order to avoid such problems, a large amount of trace memory is required, which causes problems such as an increase in circuit scale and an increase in exclusive area.

The present invention has been made in view of the above-mentioned problems, and
The purpose is to provide a trace circuit that prevents effective trace data from being substantially reduced due to loop execution and that makes full use of trace memory.

(Means for Solving the Problems) The trace circuit of the present invention includes a loop address register that stores the start address of a loop that is executed from the start to the end of the trace, and a loop that stores the loop address register. a comparator that detects a match between the start address and a current address on an address bus of the target system; and, when a match is detected by the comparator, holds an address for writing the current address into the trace memory. a memory circuit; a comparator for detecting whether the current address is a contiguous address or a discontinuous address from the immediately previous address when a match is detected by the comparator; The present invention is characterized by comprising a selector that selects an address held by the storage circuit as a write address to the trace memory when it is detected that the current address and the previous address are discontinuous.

(Operation) When the actual execution address reaches the loop start address registered in the loop address register in advance,
It detects whether the result is reached for the first time as a result of sequentially executing the program, or whether it is the result of branching to the beginning of the loop by a branch instruction to execute the loop, and if it branches to the beginning of the loop, ,
By not writing this execution result to a new address in the trace memory, but overriding it to the address where the data from the first sequential execution is stored, the executed part of the loop is recorded in the trace memory in duplicate. To achieve effective use of memory.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the trace circuit of the present invention.

This embodiment includes a trace memory 1 that records the states of the data bus and address bus of the target microprocessor, a decoder 2 that detects an instruction fetch cycle, and an adder that adds 1 to the address of the instruction currently being executed. 3a, a latch 4 that holds the address, a loop address register 5 that holds the loop start address, and compares the current instruction address with the previous instruction address plus 1 and the loop start address to find a match. Comparators 6b and 6a to detect, a latch 7 that holds the write address to the trace memory, a latch 8 that holds the trace memory address when the loop start address is written to the trace memory, and a latch 8 that holds the trace memory address when the loop start address is written to the trace memory, and a It consists of a selector 9 that switches between execution and when a branch to the top of the loop occurs, an adder 3b that generates the next trace memory address, and a loop counter 11 that counts the number of loops. There is.

With the above circuit, during normal instruction execution, tracing is performed while incrementing the ten-race memory address by +1, and when the loop top instruction is executed sequentially, the trace memory address at that time is memorized and latched 8). When branching to and executing a loop top instruction, the loop execution part is updated to the latest execution by setting the trace memory address to the trace memory address (contents of latch 8) that previously stored the loop top instruction. This realizes a function that traces only the results.

The functions of each circuit are as follows.

The trace memory 1 stores data, addresses, and a bit indicating that a branch has been made to the beginning of the loop.

Decoder 2 uses FETC in the instruction fetch cycle.
Set H to LOW.

Adders 3a and 3b add 1 to the address.

Latch 4 is the address of the previous instruction fetch cycle +
Hold 1.

The loop start address is set in the loop address register 5.

Comparators 6a and 6b are controlled by FETCH, which detects address coincidence, and operate only in instruction fetch cycles.

Latch 7 holds the write address of the trace memory.

Latch 8 holds the trace memory address when the beginning of the loop was executed.

Selector 9 normally provides the address of latch 7 as a trace memory address. When branching to the beginning of the loop, latch 8 is selected.

The loop counter 11 counts the number of times a loop is executed.

Next, the operation of this embodiment will be specifically explained using FIGS. 2 and 3.

(1) When the loop start address is executed sequentially When the loop start address N set in the loop address register 5 matches the current address, the signal HIT output from the comparator 6a temporarily becomes low level ( In other words, a negative pulse is output). Further, since the current address and the output of the latch 4 (previous address +1) are both N and match, C0NT also becomes low level and a negative pulse is output. As a result, Nantes Gate T
1 becomes low level, a sampling pulse is supplied to the latch 8, and the address T of the trace memory storing the loop head data is held in the latch 8.

That is, the output of the Nant gate T2 is at a high level (“l
”), the output Y of the selector is equal to the input of the AfliJ child (output T of latch 7), and the output T of this latch 7 is
becomes the write address to the trace memory, and on the other hand,
This address T is held in latch 8 in preparation for later loop execution.

(2) When branching to the beginning of the loop In this case, the loop beginning address (current address) N does not match the output address M+1 of latch 4, so C0
NT maintains a high level. As a result, the output of the Nant gate T2 becomes low level ("O"), and the selector 9 selects the output address of the latch 8. That is,
The content T of the latch 8 becomes the write address of the trace memory, T+l is loaded into the latch 7, and the data is overwritten to the same address as in the case of sequential execution.

FIGS. 4(a) and 4(b) are diagrams showing an example of the tracing operation of this embodiment.

When the processor operates as shown in (a) of the same figure,
In portions B and D where the loop is executed, only the latest loop execution result remains in the trace memory, and the previous results are overwritten (FIG. 2(b)).

In this case, the loop counter 11 holds the number of loop executions of loop D after the trace ends.

Furthermore, at the beginning of loops B and D, a bit indicating that there is a branch to the beginning of the loop is turned on.

Although the present invention has been described above using examples, the wooden invention is not limited thereto, and various modifications and applications are possible. For example, multiple detection circuits including loop address registers may be provided to support multiple loops and multiple sequential loops.

Further, the present invention can be used not only for trace circuits of in-circuit emulators but also for example, trace circuits for microprograms.

(Effects of the Invention) As explained above, the present invention detects in real time if there is a loop registered in advance during tracing, and prevents the loop execution portion from being duplicated and recorded in the trace memory. By doing so, it is possible to realize a trace function that makes effective use of memory.

This makes it possible to trace phenomena that could not be captured by conventional trace functions without increasing the capacity of the trace memory.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the trace circuit of the present invention, Fig. 2 is a timing chart for explaining the operation when the beginning of a loop is executed sequentially, and Fig. 3 is a case where a branch is made to the beginning of the loop. Timing charts for explaining the operation of FIGS. 4(a) and 4(b)
) is a diagram showing an example of the trace operation of the embodiment of FIG. 1, (a) is a diagram showing the operation of the target processor, (b) is a diagram showing the contents of the trace memory, and ( b) is a diagram showing an example of a conventional tracing operation. 1...Trace memory 2...Decoder 3a, 3
b...1 adder 4...latch 5...loop address register

Claims (1)

[Scope of Claim] A trace circuit that causes a target system to execute a program and records the states of a data bus and an address bus in a trace memory while monitoring bus accesses of the target system. The loop address register (5) that stores the start address of the loop to be processed matches the loop start address stored in the loop address register (5) and the current address of the address bus of the target system. a comparator (6a) that stores the current address in the trace memory when a match is detected by the comparator (6a); ), the comparator (6b) detects whether the current address is a contiguous address to the previous address or a discontinuous address when a match is detected by the comparator (6b); and a selector (9) that selects an address held by the storage circuit as a write address to the trace memory when it is detected that the current address and the previous address are discontinuous. trace circuit.