JPH0652044A - Microprocessor - Google Patents

Abstract

PURPOSE:To decelerate only a clock in the execution of an instruction and to perform the fetch and decoding of the instruction by an ordinary clock when a microprocessor makes access memory with slow speed connected to the outside and also when the instruction is an access instruction to the external memory as a result of the decoding of the instruction. CONSTITUTION:Plural signals with different frequencies are generated at frequency dividers 21-2n by the control signal 9 of an instruction decoder 7 based on a master clock 3 inputted from the outside, and a selection circuit 4 which selects the plural signals is controlled by a control signal 8 from the instruction decoder 7, and a signal 5 outputted from the selection circuit 4 is set as a system clock. Thereby, it is possible to change the clock based on a result of decoding and to suppress power consumption in a chip to a low level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly to a method of generating a plurality of system clock signals having different frequencies and selecting one of them as a result of instruction decoding.

[0002]

2. Description of the Related Art When an attempt is made to access an externally connected memory by a microprocessor, if the operating speed of the connected memory is such that the microprocessor can access it without waiting, then the memory between the microprocessor and the memory can be It is easy to set the timing of data transfer.
However, in a high-speed microprocessor, the memory that can be accessed without wait is limited.

When a memory slower than the operating speed of the microprocessor is used, the timing of data transfer between the microprocessor and the external memory will not match,
It becomes impossible to send accurate data between the microprocessor and the external memory.

Therefore, in order to send accurate data in synchronism with the external memory, as shown in FIG. 6 ((a) is no wait, (b) is 1 wait).
A method of inserting a weight (Tw), for example, μPD70208H (trade name) or μPD70216 manufactured by NEC Corporation
H (brand name) "User's Manual V40HL,
As described in "V50HL", there is a method of setting the timing by setting the system clock to be slow by writing data to a specific register using software.

Data transfer between a conventional microprocessor and an external memory will be described with reference to the drawings.

FIG. 4 is a graph of power consumption when weights are added and when the system clock is changed, FIG. 5 is a system diagram of an example of a conventional clock generator, and FIG. It is a time chart when it is used.

According to FIG. 5, a conventional clock generator uses an oscillator circuit 101 which oscillates a predetermined frequency by using a crystal oscillator (not shown) connected to the outside of the microcomputer, and the above-mentioned oscillation frequency of 1 Frequency divider 102 that divides the frequency by 2 and frequency divider 103 that further divides the frequency.
And the frequency divider 104 generate various internal clocks.

ΜPD70216H (16 manufactured by NEC Corporation)
(Bit microprocessor) or the like uses the clock generator of FIG. 5 having the above configuration. The 1 to 8 frequency divider 103 generates one of 1, 2, 4, and 8 frequency-divided signals based on the signal output from the 2 frequency divider according to the value of a certain specific register, and CPU, DMU ( It is output as a clock signal for each unit of DMA control unit), REFU (refresh control unit), and SCU (serial control unit). In addition, the TCU (timer / timer /
Output clock signal to counter unit). For example, as shown in FIG. 7, an external memory having a different speed is connected to each address range.

When accessing an external memory connected to addresses 8000H to 9fffH, which has an operation speed half that of the processor, it is necessary to match the timing. According to the time chart shown in FIG. 6, in the method of adding a wait, the system clock for one wait (Tw) is inserted to match the timing with the memory. Further, in the method of changing the system clock by writing a value in a specific register like the above-mentioned μPD70216 (16-bit microprocessor manufactured by NEC Corporation), the frequency divider outputs 2 before the address is accessed. The data of a specific register is rewritten and the system clock is slowed down so that the 1 to 8 frequency divider and the 2 to 8 frequency divider output a signal having a frequency 1/2 times that of the signal
It matches the timing with the memory.

[0010]

Generally, the power consumption P of a chip is represented by P = P _ACON + P _AMC + P _DC , and is shown in a graph of FIG. P _ACON represents power consumption depending on the frequency of the master clock, and P _DC represents power consumption depending on DC current. The two power consumptions P _ACON and P _DC do not change because they do not depend on the frequency of the system clock. P _{AM C} represents the power consumption that depends on the frequency of the system clock, and the power consumption P _AMC increases in proportion to the frequency of the system clock.

[0011] As described above, in the method of inserting wait to match the timing with the external, as shown in FIG. 6, if the no-wait (FIG. 6 (a)) is one bus cycle T ₁ through T _In the case of 1 wait (FIG. 5 (b)), the clock Tw is inserted between the clocks T ₃ and T ₄ to make 5 bus cycles for 1 bus cycle. Since the operation of the microprocessor is additionally performed, the power consumption of the microprocessor increases like _PAMC shown in FIG.

For example, when changing the system clock with software such as a 16-bit microprocessor μPD70216 (trade name) manufactured by NEC Corporation, setting the data in a certain register to change the clock means Since the system clock is always determined by the value of that register, unless a value that speeds up the system clock is written to that register, fetching, decoding, and execution of the next and subsequent instructions will also be performed in the slow system clock state. . Therefore, the effect of using a high-speed microprocessor is reduced.

In order to prevent this, when it is desired to execute an operation instruction or the like with a system clock with a high frequency, first write data in a specific register before performing the operation and change to a system clock with a high frequency. The calculation will be executed from. When accessing the external memory after that, the data is written again in the specific register to make the system clock of the slow frequency, and then the access instruction is executed. This method has a drawback that the value of a specific register is rewritten many times, so that the execution time increases, the effect of using a high-speed processor is reduced, and the power consumption also increases. .

[0014]

The features of the present invention are: an arithmetic circuit for performing an arithmetic operation; an instruction memory for storing an instruction for controlling a system; and an operation of a processor by decoding the contents of the instruction memory. An instruction decoder for outputting a signal to output, a program counter for specifying a read address of the instruction memory, an external clock input terminal for inputting a master signal, and an external memory connected to control input / output of data with the external memory. Reed that outputs a signal
A write terminal, and an address terminal connected to the external memory and outputting a signal designating an address of the external memory,
In a microprocessor having a data input / output terminal connected to the external memory and used for inputting / outputting data to / from the external memory, a plurality of signals having different frequencies are output from the master clock signal input via the external clock input terminal. A frequency divider circuit that is generated and whose output is reset by a clock generation signal that is input from the instruction decoder, and a clock selection circuit control signal that is input from the instruction decoder, and is controlled at the time of an instruction to access the external memory. By providing a clock selection circuit that selectively outputs, as a system clock signal, a signal having a frequency corresponding to the access time of the external memory from among a plurality of signals having different frequencies, the external memory connected to the outside and having a slow operation speed can be provided. When the instruction to access the master clock It is to be executed in one instruction without inserting the clock for weights No..

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. The instruction decoder 7 decodes the instruction given from the instruction memory 6, and outputs the clock selection circuit control signal 8 to the clock selection circuit 4 and the clock generation signal 9 to the frequency dividing circuit 2.

The external clock input terminal 1 receives the master clock signal 3 from the outside and outputs the signal as it is to the frequency dividing circuit 2 and the clock selecting circuit 4. The frequency dividers 21, 22, 23, ..., 2n in the frequency divider 2 are divided by the frequency dividers 21, 22, 22 when the clock generation signal 9 is "1" as can be seen from the time chart shown in FIG. , 2n outputs a signal having a frequency 1/2 times that of the signal output from the immediately previous frequency divider to the next frequency divider and the clock selection circuit 4.

When the clock generation signal 9 from the instruction decoder 7 is "0", the frequency dividers 21, 22, 23,
, 2n outputs a signal "0" to the next frequency divider and the clock selection circuit 4.

FIG. 2 shows an example of the circuit of the frequency divider 21. A JK type flip-flop consisting of AND gates 210 and 211, an OR gate 212 and a DFF with a clear preset is used. One input end of the AND gate 210 is "1" and one input end of the AND gate 211 is "0" level. The PR terminal is fixed at "1" level, the master clock signal 3 is input to the CLK terminal, and the clock generation signal 9 is input to the CLR terminal.

On the other hand, the clock selection circuit 4 selects one of the signals output from each of the frequency dividers 21, 22, ..., 2n by the clock selection circuit control signal 8 output from the instruction decoder 7, and the system clock signal 5 Output as. After generating the signal of one system clock, the master clock signal 3 is selected as the system clock signal 5.

In the method of the present invention, as shown in the column of the speed ratio of the external memory to be connected with the CPU in FIG. 7, external memories having different speeds are connected to respective address ranges,
When accessing the external memory at addresses 8000H to 9fffH, the instruction decoder 7 causes the frequency dividing circuit 2 to operate as shown in FIG.
The clock generation signal 9 and the clock selection circuit control signal 8 are output as described above, and the clock selection circuit 4 receives the clock selection circuit control signal 8 and outputs 1 of the master clock signal 3.
The signal output from the frequency divider 21 having a frequency of / 2 is selected and output as the system clock signal 5 (timing chart in FIG. 3).

The clock selection circuit 4 outputs one system clock signal 5, then selects the master clock signal 3 again and outputs it as the system clock signal 5. At this time, the clock generation signal 9 is "0", each frequency divider is cleared and outputs "0". Further, except when accessing an external memory, the instruction decoder 7 outputs the clock generation signal 9 and the clock selection circuit control signal 8 shown in FIG. 7A, and the clock selection circuit 4 outputs the master clock signal 3 to the system. Output as clock 5.

In the timing chart shown in FIG. 3, the clock selection circuit control signal 8 is 1000 (= 8), 0100 (=) of the clock selection circuit control signal 8 shown in FIG.
4) and 0010 (= 2), if of the output waveform of the clock selection circuit 4 indicates instruction fetch, id indicates instruction decoding, and ex indicates instruction execution cycle.

According to this method, the microprocessor fetches and decodes an instruction at a normal speed only when accessing the external memory, and does not insert a wait by changing the clock only when the access is executed. Can be executed by instruction. Further, the power consumption P _AMC can be reduced to about 1/2 as compared with the method of inserting the wait because the system clock requires only one cycle.

Further, when the access to the outside is completed, in order to select the master clock signal 3, the above-mentioned μPD is selected.
It is not necessary to execute an instruction to change the system clock as 70,216, it is possible to reduce the power consumption as P _'AMC shown in FIG.

[0026]

As described above, a frequency dividing circuit for generating a plurality of signals having different frequencies from a master clock signal input through an external clock input terminal and resetting the output by the clock generation signal, Clock selection circuit Clock selection that selects and outputs the signal of the frequency corresponding to the access time of the external memory as the system clock signal from the multiple signals with different frequencies when the instruction to access the external memory is controlled by the control signal. And a circuit.

Therefore, when accessing an external memory having a slow operation speed, one instruction can be executed without inserting a wait clock in the master clock signal.

That is, since the external memory can be accessed with one instruction and a small clock, the power consumption depending on the system clock can be suppressed to about 1/3,
This has the effect of suppressing the total power consumption in the chip.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a circuit of a frequency divider according to an embodiment of the present invention.

FIG. 3 is a timing chart of a master clock, a frequency divider output, and a clock selection circuit output.

FIG. 4 is a diagram showing power consumption when a wait is inserted and when a system clock signal is selected.

FIG. 5 is a diagram showing an example of a conventional clock generator.

FIG. 6 shows a conventional case of (a) no weight, (b) 1
It is a timing chart which shows the case of a wait.

FIG. 7 is a diagram showing a relationship between an address value, a speed ratio of a CPU to a memory, and a clock selection circuit control signal.

[Explanation of symbols]

 1 external clock input terminal 2 frequency divider 21 to 2n frequency divider 3 master clock signal 4 clock selection circuit 5 system clock signal 6 instruction memory 7 instruction decoder 8 clock selection circuit control signal 9 clock generation signal

Claims (1)

[Claims] 1. An arithmetic circuit for performing an operation, an instruction memory for storing an instruction for controlling a system, an instruction decoder for decoding a content of the instruction memory and outputting a signal for controlling an operation of a processor, A program counter for designating a read address of the instruction memory, an external clock input terminal for inputting a master signal, a read / write terminal for connecting to the external memory and outputting a signal for controlling input / output of data with the external memory, In a microprocessor comprising an address terminal connected to the external memory and outputting a signal designating an address of the external memory, and a data input / output terminal used for inputting / outputting data to / from the external memory , A frequency different from that of the master clock signal input via the external clock input terminal. Access to the external memory, which is controlled by a frequency dividing circuit that generates a plurality of signals that are generated and whose output is reset by a clock generation signal that is input from the instruction decoder, and a clock selection circuit control signal that is input from the instruction decoder. By providing a clock selection circuit that selectively outputs, as a system clock signal, a signal having a frequency corresponding to the access time of the external memory from among a plurality of signals having different frequencies when an instruction is issued, A microprocessor which can be executed by one instruction without inserting a wait clock in the master clock signal when an instruction for accessing the external memory is late.