JPS59100957A - Loop control system - Google Patents

Abstract

PURPOSE:To remove a useless cycle which is generated for each loop and to increase the speed of operation by discontinuing the control using a loop end sentence but using a loop declaring sentence. CONSTITUTION:An address N-1 of an instruction ROM2 is designated by a program counter PC1', and the contents of instruction of the address N-1 are sent to an instruction register 3. Then the loop frequency is set to a loop counter 5 via a decoder 4. Then the OC1' designates an address N of the ROM2, and both the loop declaring sentence of the contents of the address N and an address N+2 of a loop end are sent to the register 3. The value of the address N+1 of the PC1' of that time point is loaded to a stack 8 by said loop declaring sentence and an indication of a decoder 4'. Thus the address N+1 is used as the head address. At the same time, the last address N+1 of the loop is loaded to an end address setting register 9 by a command of the decoder 4'. The PC1' designates successively subsequent addresses N+1 and N+2 of the ROM2.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a microcontroller whose operation is controlled by microprogram instructions stored in an instruction read-only memory (hereinafter referred to as ROM), and particularly relates to a real-time A digital signal file that enables high-speed processing and processing.
This article relates to a 2-1 control system for processors.

(b) Prior Art and Problems The conventional Lu1 control system will be explained below with reference to the drawings. The first cause is a block diagram of a circuit mainly consisting of a conventional roof' control circuit, FIG. '
In the time chart of part 6, (4) is the 7" program counter, a3) is the instruction RαM, (Q is the instruction register, (2)
(G) indicates a loop counter, (G) indicates a loop end signal, (G) indicates a load signal to the decoder, and (G) indicates a load signal to the program counter.

N, N+11N+2. N+3. N+4. N+5 is command R
Address of OM, NtN+ltN+2. N+3s
N+4 indicates the content of the command of the current player, and K in (2) indicates the number of looses.

When the PCI specifies the N address of the instruction ROM 2, the content %K of the instruction at the N address of the instruction ROM is set in the loop counter circuit and sent to the instruction register 3, as shown in FIG.
A loop number K is set in the LC 5 via the decoder 4.

Next, by specifying the N+1sN"2 addresses of the PCI instruction R-OM2 one after another, N+L of the instruction ROM2 shown in FIG.
The content of the N+2 instruction, ``operation'', is sent to the instruction register 3, and the microcontrol processor performs the operation. Next, the PC
When instruction ROM2ON+3 address is specified from I, the second
The contents of the loop end statement at location N+3 of the instruction ROM 2 shown in the figure are sent to the instruction register 3, and the load signal shown in FIG. Each time t) is subtracted by 5Htt according to the number of loops set previously, the PCI load signal becomes the PCI load signal shown in FIG. 3G) through the AND circuit 6 until the value becomes %1s. The return destination address N+1 in the loop end statement is loaded into υPCI as the output of the instruction register 3 to form a loose loop. When the value of the loose number of LC5 reaches z1 as shown in FIG. 3 (2), LC5 outputs a signal of power 1/I level as shown in FIG. The PCI then specifies successive addresses of instruction R0M2 and the microcontroller executes the next instruction.However, such a conventional loop control circuit In this case, the following drawback arises: P
The processing that the CI executes with the instruction room loose-end statement in the N+3 location that specifies the instruction ROMZ does not actually perform arithmetic processing, resulting in dead time in loose arithmetic processing, making it difficult to speed up the arithmetic processing. There was a drawback that there was no

(c) Purpose of the Invention In view of the above-mentioned drawbacks, the purpose of the present invention is to eliminate control using loop end statements and use loop declaration statements to eliminate wasteful cycles that occur in each loop. 0(d) Structure of the Invention To achieve the above object, the present invention provides a loop end address using a loop declaration statement when forming loop money. Set it in the end address setting register and log 2
When the output from the program counter and the comparator that compares the contents of the register match, at the beginning of the next cycle, the loop start address that was saved in the p stack by the loop declaration statement is loaded into the program counter. let After that, the value of the loop counter is decremented by 1. By controlling the series of operations as described above to be repeated until the value of the loop counter reaches a predetermined value, unnecessary cycles can be removed and calculation speed can be increased.0 (e) Implementation of the Invention EXAMPLE Hereinafter, one embodiment of the present invention will be explained with reference to the drawings. Fourth
5 is a block diagram of a circuit mainly consisting of a loop control circuit according to an embodiment of the present invention, FIG. The figure is number 4
In the time chart of each part in the figure, (4) is a program counter, and a3) is an instruction ROM.

(Q is the instruction register, (2) is the loop counter, (g)
is the loose end number, (G) is the load signal to the program counter, (G) is the stack, wholesale is the end address setting register, (1) is the way the match signal is output from the comparator. Items with the same functions as Isamu 3 are shown with the same symbols.
1' is a program counter (PC), 4' is a decoder,
8 is the stack, 9 is the end address setting register, 10
is a comparator, N+1 in FIG. 609 is a loose start address, and N+2 in FIG. 6 ψ is a loop end address.

When specifying the N-1 area of instruction ROM2 from pci',
Contents of the instruction at address N-1 of the instruction ROM 2 shown in FIG.
"Set XK as loop counter" is sent to the instruction register 3, and via the decoder 4, Lc5 is set to the loose number -//. This may be defined simultaneously in a later loose declaration statement. Next, from the PCI, the N of the instruction ROIVi2 is
When the address is specified, the loop declaration statement at address N of the instruction ROM 2 and the loose end address N+2 shown in FIG. 5 are sent to the instruction register 3. According to this loop declaration statement,
The value of P-CI' at that time, N+1, is loaded into the stack 8 according to a command from the decoder 4'. This becomes the starting address of the loop. At the same time, the last address N+2 of the loop is loaded into the end address setting register 9 by a command from the decoder 4'. PCI' specifies successive addresses N+11N+2 of the instruction ROM 2 one after another. The output of PCI' and the output of end address setting register 9 are input to comparator 10, and when both values match (in this case, match at N+2)
As shown in (I) of FIG. 6, a coincidence No. 8 is output. This coincidence signal is passed through the AND circuit 6 to the PCI interface shown in FIG.
' becomes a load signal, and sends the first address stored in the stack 8 to the instruction register 3. Instruction register 3 is N
While receiving the contents of address N+1 from the instruction ROM 2, J411 receives the contents of address N+1 from the instruction ROM 2. N+2 address #
The microcontroller processor performs an operation based on the instruction contents of P.

As can be seen from the above explanation, the address specification of the instruction R-OM2 of PCl4 is the end address N+2 as shown in the prisoner of group 6.
'(After specifying i=, the first address N+i is added. Therefore, the microcontrol processor performs operations in the loop one after another without wasting cycles.LC5
When the value of the number of loops becomes <%1// as shown in FIG. 6 (2), the LC5 outputs a signal of λ\1〃 level as shown in FIG. It is input to the AND circuit 6, and all match signals from the comparator 1O are stopped. Therefore, the load signal to PCI' disappears as shown in Figure 6 (3). Therefore, pci' is the address N+ of successive instruction ROM2.
3jN+4, the microcontroller processor executes one instruction after another.

By doing the above! JPCB' eliminates the need to specify wasteful locations such as loose end statements, and specifies only the addresses of actually necessary arithmetic instructions, thereby increasing the speed of loose execution.

(f) Effects of the Invention As described in detail above, the present invention has the effect of speeding up calculations since unnecessary cycles are removed when executing a loop.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a circuit mainly consisting of a conventional loop 1 control circuit, the second figure is an example instruction statement diagram showing the address of the instruction ROIVi and the contents of the instruction in the case of figure 1, and Fig. 3 1 is a time chart of each part in FIG. 1, FIG. 4 is a block diagram of a circuit mainly consisting of a rune control circuit according to an embodiment of the present invention, and FIG. 5 is an address of the instruction ROM and contents of instructions in the case of FIG. 4. FIG. 6 is a time chart of each part of the fourth factor. In the figure, 1 and 1' are glogram counters, and 2 is an instruction R-OM.
13 is an instruction register; 4, 4'-i'1. decode,
5 is a loop counter, 6 is an acid circuit, 7 is a not circuit, 8 is a stack, 9 is an end address setting register, l
O indicates a comparator.

Claims (1)

[Claims] In a microcontroller whose operation is controlled by microprogram instructions stored in instruction read-only memory, a roof instruction is placed at the beginning of a loop 1 statement to form a loop with instructions, and the roof instruction is used to close the loop at the beginning of the loop. A stack that can save the contents of the program counter, a register that sets the loop end address set in the loop instruction, and a comparator that compares the contents of the register and the contents of the 10-gram counter are provided. This loose control system is characterized in that when the comparison contents in the devices match, the first address is loaded from the stack to the log counter a number of times set in a loop counter storing the number of loop instructions.