JPS5949644A - Arithmetic processing circuit of sequence controller - Google Patents

Abstract

PURPOSE:To inhibit the processing in an unnecessary stage, by altering or converting the output of a stage counter according to the kind of an instruction and the contents of an arithmetic result register. CONSTITUTION:An arithmetic control part 2 reads an instruction code (k) in an FF4 by the input of a latch signal l. Then, values of instruction codes (c) and (d) are identified and a clear command is supplied to the stage counter 1 at the time of an instruction NOP (allowing no process in the step except the advance of only the address counter of a program memory). Then, an advance to the next instruction fetch is made. The output (a) of the counter 1 is raised to ''1'' at the time of an instruction accompanying the input or output of external control data. The control part 2 sends out an operation mode code which means the input or output as an output (a) according to the condition between outputs (a) and (c) to perform specific operation. At the time of a conditional jump instruction, processing is performed according to the values of the output (a) of the counter 1 and the output (c) of the FF4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an arithmetic processing device
This paper relates to a processing circuit of a sequence controller that is optimal for performing t3j processing 3!41.

[Prior art]

The conventional processing method for sequence controllers is to set a certain cycle time r to process all the commands of a snag, and divide it into stages for each processing process to perform the processing. / Jin.

Figure 1 is a seventh diagram showing the entire arithmetic processing method, and is ν0 when the execution of a one-step command is divided into four stages and the performance processing is performed.

Stage ITf'J, f='ti instruction Wt output instruction fetch] and the increment of the address counter for the next instruction, and stage ■ creates all the addresses to specify the control data of the next stage. fc performs calculations between internal registers that do not require external control data.゛Also in Stage III IV, evening 11
Read control data from 1- and perform arithmetic processing,
The calculation result is output as open side 1 data.

According to such an arithmetic processing method, the execution cycle of one instruction is fixed, and processing cannot proceed to the next instruction unless all stages t-- Ill have been passed.

Therefore, there is an instruction that requires only the stage -t<ll and does not need to do anything else. For example, in a NOP instruction (the step does nothing and increments only the address counter in program memory), only stage ■ is required, and the others are not required, but in that case, the stage counter is actually is not executed, only advancing the stage is performed. Such an instruction wastes the time required to process the extra stages, thereby reducing the overall calculation processing speed.

In general, the sequence controller has a program capacity of 11 (steps to 16) (step 81.1).The cyclic processing time (scan time) is Here, if there is wasted processing time as described above, this scan time will not be greatly affected.

For example, if one instruction is 4μS and 2μs of that is wasted in useless processing, the scan time in IKw memory is about 4mS, but 2mS of that is wasted in every scan. It turns out.

[Purpose of the invention]

The present invention overcomes the drawbacks of the prior art described above.

An object of the present invention is to provide an arithmetic processing circuit for a sequence controller in which no useless processing stages are generated among the processing stages for one instruction.

[41 inventions! ] The present invention transforms or converts the output of a stage counter (or shift register) that controls the processing process of one-step instructions depending on the type of instruction, the existence of a performance result register, etc. , is characterized in that each instruction is processed without processing any unnecessary stages.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be explained with reference to the accompanying drawings. FIG. 2 shows the Ill configuration of the sequence controller control unit a, where 1 is the operation processing stage counter, 2 is the arithmetic control unit including the division 11 part of the stage counter, and 3 is the actual operation control unit. Act) A river performing I action
At the capital, input line h of control data of outside 115, output mA g
s Output All d indicating the contents of the dance result register is M. 4e Mar step instruction code k ”f hold -C
C is its output (instruction code)
and is input to the calculation side (tLl ill 2).

5 is the basic clock oscillator, reset at power-on 15
Generate number j. The arithmetic control section 2 increments the stage color/return 1 through the control line of the stage counter 1 or returns it to the initial state based on the output a of the stage counter 10 and the result d of the instruction code C1. -f
In addition, for ts: +t++ 3, the operation mode is given by the signal line f, and the operation mode is given by the signal line e.
This is an operation command when inputting the input data and calculating the logical result or outputting the data. Next, the common operation of one device line on the side system side shown in FIG. 2 will be explained together with the time chart of FIG. 3 showing the input/output shape of each 1111.

First, when the reset/1 straight number j is input from the oscillator 5, the arithmetic control fll2 unconditionally gives a clear command to the stage counter 1 via the fourth flag AjMb4:.

As a result, the output a of the stage counter 1 will indicate the month, but the instruction code c1 or r, which is the output of the flip-flop 4, is "0" in advance, regardless of the 1 shift of the operation result d. , instruction fetch, instruction code 1 (v) can be output by inputting latch signal t to all flip-flops 4.

Here, the value of the instruction code C or d is established. For example, if it is a NOP nW command, the clear command can be immediately given to the stage counter 1 and the next instruction can be fetched. If the input ° or output is all 1 and half, issue an increment command to stage counter 1, and output a't r of stage counter 1.
tJ, and depending on the conditions of its output a and C, express 'kl 1l
ill all 141i Outputs the operating mode code 1' which means 'input' or output to the output e of 2 and sets the predetermined A.
Execute the 1111th work.゛Also, at the end of this operation,
A clear command is given to stage counter 1, and the next instruction fetch is started. This is clear from the Y/F whipyard in Figure 3.

Furthermore, when the multiplier 1'l: jump instruction depends on the result of the previous instruction, the output d output from the operator 3 in the instance j traction fetch hypothetical Decide whether to issue a clear command or a step command to the stage counter 1, and if it is a step, the output a of the stage counter 1 after the step and the flip 70 knob 40 output C
Process according to the value of . In this case, it goes without saying that a jump process must be performed.

As is clear from the time chart in Figure 3, in the conventional arithmetic processing method, all instructions required four stages, but according to this implementation 1j, the NoP instruction requires I'□11 stages.
The stage requires only 1 stage, which is the same as the 7-bit command (not 2 stages in maki!ilb珀41'l2otoI), eliminating unnecessary stages and clearly improving processing speed. It can be seen that the weight has improved by 7t.

In the above-mentioned Example 11, a stage counter was used as a means for controlling the entire processing process of a one-step instruction.
Although the case -CHII has been explained above, in addition to this 7t, a shift register having a similar one-table function may be used.

In this way, on the A flow side, the stage counter (or shift register) and its stage counter Kanayama 11
f114 + stage counter city 11flL (1 bar 11 minus i, command word's :I!li class, operation j, r result register) By increasing or decreasing the processing process of the command word according to the content etc. Reduces treatment time and reduces treatment time.

According to the same example, the scan time of the sequence controller could be reduced to about 60% of the conventional one.

[Early fruit of the invention] As is clear from the two actual htU examples, according to the present invention, there is no need to execute the "wasteful stage."
Compared to conventional arithmetic processing methods, the instruction processing time can be significantly shortened, contributing to an improvement in the 1/to performance of the sequence controller.

[Brief explanation of the drawing]

Figure 1 is a time chart for simplifying the processing method. 1118 configuration diagram, ^S3 diagram is the second
6 is a time chart for testing the circuit shown in the figure. 1... Stage counter, 2... Reconnaissance 1 interval f111
part, 3... performance j'4 t'rB, 4... free lag flop, 5... starting device. Agent Patent attorney Tadashi Akimoto Hi younger brother 1 Zukyu Chi Jl n ■L--
-----" Stay, d'M
(mouth Σ-also'; M [phase] L-111111

Claims (1)

[Claims] The control program sequentially reads out the program kFdt from the program memory loaded 1!
7L Performance according to the program contents: In the arithmetic processing unit of the seedance controller that performs processing and executes the desired sequence fli control, the stage counter (- In addition to inputting the output of the stage counter (or shift register) and the stage counter (or shift register), the operation timing and dJb operation code are given to the arithmetic unit that performs the actual arithmetic operation, and the instruction code is executed: J' Stage counter control for incrementing the stage counter or returning it to the initial state by inputting the result of performance 11 in part L'.
C Miyamu performance! (+iii) The processing time of the instruction code is increased or decreased by 1 depending on the output of the stage counter (or shift register) and the contents of the operation result register. A performance KM s'M circuit for a sequence controller, characterized in that the KM s'M circuit is shortened.