KR930005707B1 - Command processing method of plc - Google Patents

Abstract

The method for improving the processing velocity of programable logic controller (PLC) comprises the following steps of: discriminating whether the instruction code is inputted or not through the data buffer; interpreting the instruction code; discriminating whether the intervention demand instruction of CPU is included or not; increasing the program counter by one if the intervention demand instruction is not included, followed by returning to the previous stage; discriminating whether the instruction code of the third stage is processed; outputting the processed result of program; generating the interrupt to the CPU if the instruction code of the third stage is not processed.

Description

PLC command processing method

1 is a hardware block diagram according to the present invention.

2 is a control flow diagram according to the present invention.

* Explanation of symbols for main parts of the drawings

10: address buffer 11: data buffer

12,13: 1-2 memory 14,15: 3-4 memory

16: buffer latch 20: HSU

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable logic controller (PLC), and more particularly, to a command processing method of a PLC capable of fast control by increasing a processing speed of a PLC command.

Generally, a PLC is a controller for controlling an operation object by processing by a user's command.

Conventionally, when a user gives a command to the PLC as a command code, the central processing unit of the PLC processes the command with an internal operating program and outputs a result thereof to control the operation target.

In other words, the central processing unit in the PLC inputs the user's command into the RAM area and processes the command code by software using the built-in operation program to control the operation target.

Therefore, the conventional method has caused a delay in the scan time according to the command processing of the central processing unit. Accordingly, there is a problem in that it cannot be used for an operation target that requires fast control.

In addition, since the central processing unit dedicates a time of 10 μsec or more per instruction to increase the total scan time, it often causes a malfunction of an operation target.

Accordingly, an object of the present invention is to provide a command processing method of a PLC capable of fast control by processing the command processing of the PLC in consideration of the above problems.

Another object of the present invention is to provide a command processing method of a PLC that can reduce the scanning time of the PLC.

The present invention for achieving the above object is characterized by having a command processing means inside the PLC to process the command.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a hardware block diagram according to an embodiment of the present invention, wherein an address buffer 10 and a data buffer 11 connected to an address bus and a data bus, respectively, and a first code connected to the address buffer 10 for storing command codes are shown in FIG. -2 memory (12, 13), 3-4 memory (14, 15) connected to the second memory (13) for storing the command code results, the address buffer (10) and data buffer ( 11) is connected to the HSO (Hardware Solving Unit) 20 for processing and outputting the command code of the PLC to the central processing unit, the HSU (20) is connected between the data bus and the HSU (20) command processing It consists of a buffer lattice 16 for latching the result.

2 is a flow chart of the present invention, a first step of determining whether a request for interpretation of a command is input through a data buffer, a second step of interpreting a command code if a command code is input from the first step, and A third step of judging whether the central processing unit requires an intervention request command from the second step, a fourth step of increasing the program counter by one and returning to the second step if the request command is not a request from the third step, and the third step; A fifth step for determining whether the processing of the command code is completed from the step; and a sixth step for outputting the processing result of the user program if it is completed from the fifth step and generating an interrupt to the central processing unit if not. .

Hereinafter, the present invention will be described in detail with reference to FIGS. 1 and 2 according to the above-described configuration. First, the central processing unit in the PLC uses 68000 CPUs, and the HSU 20 of FIG. 1 uses XC3030-PC84. In FIG. 1, the HSC 20 is coupled between the central processing unit and the input / output device in the PLC to process the command code from the central processing unit.

Therefore, in the central processing unit, command code processing causes the HSU 20 to process and system operation other than command code processing. Therefore, when a command code that is a user's command code program is input, the CPU processes the address code of the command code through the address bus and outputs the address code to the address buffer 10.

In addition, command data is output to the data buffer 11.

The HSU 20 then stores and stores the command data output to the data buffer 11 in the 1-2 memory 12,13.

Where the HSU 20 The command code is processed by the command enable signal of the terminal.

The third and fourth memories 14 and 15 store and store the processing result of the processed command code. In addition, the buffer latch 16 The command processing result is latched by the terminal clock and outputs the analysis result to the CPU through the data bus.

Referring to FIG. 2, the command code input is determined in (2a), and if it is an input (2b), HSU solving is performed (2c). It increments 1 and returns to (2b). If it is an interrupt in (2c), it is determined whether the input of the command code is completed in (2f), and if it is finished, it ends in (2h).

If it is not the end (2g) in (2f), an interrupt is generated, which returns to (2a).

On the other hand, the HSU 20 is designed to solve in one step per four clocks by the input clock. Here, a correct scanning time of about 20 times as compared with the conventional scanning time is obtained. Therefore, as described above, since the present invention can process the user's command code by hardware, there is an advantage in that the instruction processing speed of the PLC is increased, so that an operation object requiring fast control can be controlled without malfunction.

Claims (1)

In a command processing method of a PLC having an HSU 20 therein, a first process of determining whether a command code interpretation request is input through a data buffer, and a command code is interpreted if a command code is input from the first process. And a third step of determining whether or not an intervention request command of the central processing unit is caught from the second step, and if not an intervention request command from the third step, increases the program counter by one and returns to the second step. And a fifth section for determining whether the processing of the command code is completed from the third step, and outputting the processing result of the user program if the processing is completed from the fifth step. The instruction processing method of the PLC, characterized in that the sixth step of generating an interrupt.