KR910002318B1 - Logic interpreter with pipe-line architecture - Google Patents

Abstract

The circuit uses the pipe line structure to analise the ladder logic with the minimum scan time and the analysed ladder logic is used to control the control objectives with high speed. The circuit fetches and processes the address information, the data information, the former data information and the processed information at every four cycle to realise the logic analyzing circuit. In a first cycle, the instruction, the operand address and operation of each nodesof Kth column are fetched. In a second cycle, the operation of each nodes are decoded and a function code is stored on a FCLu (48) and FCL1 (50). In a third cycle, the designated address data is stored on a PDLu (40) and PDL1 (42) through data buses (37,39). In a fourth cycle, the data stored in the PDLu (40), PDL1 (42) FCLu (48), FCL1 (50) are input to a PSu (52), PS1 (54) to analyse the ladder logic.

Description

Hardware logic analysis circuit with pipeline structure

1 is a ladder logic diagram.

2 is a circuit diagram according to the present invention.

3 is an operation timing diagram of FIG.

* Explanation of symbols for main parts of the drawings

10: program counter 12: clock controller

14: instruction memory 16: upper address memory

18: row address memory 20: upper function memory

22: low function memory 24: instruction latch

26: upper address latch 28: row address latch

30: upper function latch 32: low function latch

34: Store Logic 36: Upper Data Memory

38: low data memory 40: upper predata latch

42: low predata latch 44: first decoder

46: 2nd decoder 48: upper function code latch

50: Low function code latch 52: Upper free shoulder

54: low presever 56: data latch

트래치58: shoulder 60: Lee

Trach

The present invention relates to a ladder logic analysis circuit of a program logic controller, and more particularly, to a ladder logic analysis circuit having a pipeline structure. In general, PLC (Program Logic Controller) is a technology that is widely applied in the industrial field of Confucius Automation (FA). In the sequence control system, only the expert of the maker side can make simple changes or modifications to the contents of the sequence control system. On the user side, there has been a great deal of interest due to the need for simple changes in the field without changing the hardware. In 1969, GM (Gereral Motors) was born the first programmable controller. The general PLC and general technology of the GM company are described in detail from page 12 of the "Introduction to the Programmable Controller" issued by "Ganam Corporation".

Conventionally, the ladder diagram logic as shown in FIG. 1 is mainly interpreted in software as shown in FIG. 1 by ROW scanning, as shown in page 139 of the "Introduction to Programmable". I've been doing it. However, the method of interpreting the ladder diagram logic by software as described above has the following problems. In case of large PLC, it takes a lot of time to analyze ladder logic, which causes a problem that the output device cannot be controlled smoothly. In other words, in PLCs having many inputs and outputs, the user's use programs become more complicated, and the ladder logic becomes complicated. In the software, the control of the complex programmed ladder logic becomes a problem. For example, when the motor connected to any output terminal of PLC is controlled every 0.1 seconds, the ladder logic (program) necessary to control the motor is analyzed by software. If this is taken, the motor will not actually be controlled by the program. Therefore, the conventional PLC that interprets the ladder logic in software has a problem in that the "SCAN Time" for receiving the given input and interpreting the ladder logic and then outputting it to the control object is long.

Accordingly, an object of the present invention is to provide a hardware ladder logic analysis circuit capable of controlling a control object at high speed by analyzing information of ladder logic with hardware.

It is a further object of the present invention to provide a circuit having a pipeline structure and analyzing ladder logic with a minimum scan time.

Hereinafter, with reference to the accompanying drawings the purpose of the present invention will be described in detail.

2 is a circuit diagram according to the present invention, a program counter 10 providing an access address of a memory by a predetermined control clock, a clock controller 12 generating a predetermined control clock, and a ladder logic program. It has 7-bit information of each column's common instruction such as End of Program (EOP) and End of Network (EON), which is the last information of Logic Program, and each node OR in the column. An even address of an instruction memory (hereinafter referred to as IM) 15 for accessing and outputting it under control, and an information designation address of an address (for example, an input address and an output relay address control relay address) of each node of a column; An upper address memory (hereinafter referred to as "Upper Address Memory") which stores only the address of a node of the node and accesses it by the output address of the program counter 10. A low address memory (AM1) 18 for storing only the addresses of 16 nodes and odd nodes and accessing them by the output address of the program counter 10, and Operation type For example, the node performs some operation such as AND AND AND NOT, STORE, STOP, JUMP and Block type instructions. Among the information specifying whether or not to be specified, only an upper function memory (hereinafter referred to as FMu) 20 which outputs only information of even-numbered nodes of each column and outputs by a predetermined address, and predetermined information only of odd-numbered nodes of each column Low function memory (hereinafter referred to as FM1) 22 outputted by an address, and each of the IM 15, AMu (16), AM1 (18), FMu (20), and FM1 (22). Synchronous output by each predetermined clock Instruction Latch (IL) (24), Address Latch (ALu) (26), Address Latch Low (AL1) (28), Function Latch Upper Function Latch: (hereinafter referred to as FLu) (30), Function Latch (hereinafter referred to as FLu) (32), and input the output information of the FMu (20) and FM1 (22) and ring the result Store Logic 34 provided as a control signal and operand of each node of each column, for example, input relay output relay, control memory, etc. are stored in the data received from the input / output processor and the ladder logic Upper data memory (hereinafter referred to as DMu) 36 and low data memory (hereinafter referred to as DM1) for outputting the analysis result to the input / output processor by the addresses of the AMu 16 and AM1 18. (38) and the outputs of the DMu (36) and DM1 (38) Upper Pre-Data Latch (hereinafter referred to as PDLu) 40 and Low Pre-Data Latch (hereinafter referred to as PDL1) 42 for storing the data in synchronization with the clock, and FMu. And the output terminal of the FMu 20 or FM1 22 to decode the output of the function code, for example, block time (timer shift register, etc.). Upper function code latch (Lupper Function Code Latch) for latching and outputting the first and second decoders 44 and 46 and the outputs of the first and second decoders 44 and 46 by a predetermined clock. FCLu) (48) and Low Function Code Latch (FCL1) (50), and the output of the PDLu (40) FCLu (48) to input the output of the upper pre-several ( Upper Pre So1ver (hereinafter referred to as PSu) (52) and a low pre-sleeve that inputs the outputs of the PDL1 (42) and FCL1 (50) to find the current leader logic result. (Low Pre So1ver: PS1) 54, and a data latch for storing and outputting the temporary result of the performed column of the operations of the PSu 52 and the PS1 52 (Data Latch: DL hereinafter). A shoulder 58 for obtaining ORI calculation information of one column from the output of the DL 56 and the output of the IL 24, and a residual latch for temporarily storing the output of the shoulder 58 by a clock; Result Latch).

3 is an operation timing diagram of FIG. 1, where k is the kth column of the ladder.

i denotes the i-th row of the k-th column and F (k, j) denotes the function of the i-th row of the k-th column.

Hereinafter, the present invention will be described with reference to FIGS. 1, 2, and 3 with operation examples. When the clock CLK of the clock controller 12 is input to the program counter 10 of FIG. 2, the program counter 10 is incremented by 1 to designate a column of ladder logic every 4 cycles of the clock. Value is output, and each time the clock is inputted, a sub-program counter value is incremented by 1 as an address signal. Therefore, during the first cycle at the position as shown in FIG. 3, the address values of the program counter 10 are transferred via the address bus 11 to the IM 14, AMu 16, AM1 18, and FMu. (20) to provide the address of FM1 (22) to fetch instructions, operand addresses, and operations. At this time, the IM 14 outputs data (column k) of the column node of the ladder logic shown in FIG. 1 to the IL 24 based on the PC value of the program counter 10. In addition, AMu (16) having data X00, Y00, Y01, Y00 of even nodes i0, i2, i4, i6 of k-column of Fig. 1 and nodes il, i3, i5, i7 of data X01, X00 of odd address AM1 (18) having L01, X02 information, FMu (20) storing the operation contents of nodes i0, i2, i3, i6 of even addresses of k columns, and nodes i1, i3, of odd addresses of k columns FM1 (22), which stores the contents of the operations of i5 and i7, performs the instruction (In-Struction), operand address (operation address) and operation of each node of column k during the first cycle clock based on the point T of FIG. Fetch operations The data fetched at this stage are input to the respective ALu 26, AL1 28, FLu 30, and FLu 32. Since the remaining data except for the output of the IM 14 are fetched one for each clock, one column of low rows is fetched every four clocks. The IMs 14 are fetched one by one before the analysis result is generated by a suitable phase clock, so that one in four clocks c1ock is generated.

트래치(RL)(60)에 저장되며, 이는 1칼럼의 로직솔빙 정보로써 도시하지 않은 주제어부에 입력된다.When the clock of the second cycle of FIG. 3 is reached, data outputted from the respective memories are stored in the latches of the ALu 16, the AL1 18, the FLu 20, and the FL1 22 as shown in FIG. 3. In addition, the first decoder 44 and the second decoder 46 decode the operation of each node output from the FMu 20 and the FM1 22 to store the function codes in the FCLu 48 and the FCL1 50. . When the clock of the third cycle in FIG. 3 is reached, the DMu 36 and the DM1 38 receive data of the address designated through the address buses 27 and 29 of the ALu 29 and AL1 28. 37 and 39 are stored in the PDLu 40 and the PDL1 42 as shown in FIG. When the clock of the fourth cycle is reached, data stored in the PDLu (40), the PDL1 (42), the FCLu (48), and the FCL1 (50) in the third cycle clock step are respectively inputted from the PSu (52) and the PS1 (54) ladder. Interpret the logic and store the result in the DL 56. In addition, the logic result data stored in the DL 56 and the “OR” information of the column stored in the IL 24 are input from the shoulder 58 to return the final result for one column.

It is stored in the track (RL) 60, which is input to the main control part (not shown) as the logic solving information of one column.

As described above, the present invention has an advantage that a logic analysis circuit that operates at high speed can be easily implemented by fetching and processing address information, data information, previous data information, ora and result processing information every four cycles. .

Claims (1)

In a hardware logic analysis circuit having a pipeline structure, a program counter 10 for providing an access address of a memory by a predetermined control clock, a clock controller 12 for generating a predetermined control clock, and final information of a ladder logic program are provided. Instruction memory 15 which has common commands such as EOP and EON and 7-bit information of each node OR information in the column, and accesses and outputs them by predetermined control, and address of each node of the column, for example, input address, Output Relay Address Control Stores only the addresses of even-numbered nodes among the information designating addresses of the relay address and stores only the addresses of the up-address memory 16 and odd-nodes which are accessed and output by the output address of the program counter 10. Accessed by the output address of the program counter 10 The lower function memory 18 to output, the upper function memory 20 to output only the information of the even-numbered node of each column among the information which specifies the operation type of each column, and to output by a predetermined address, and the odd-numbered node of each column. Corresponding connection is provided to the row function memory 22 outputting only the information of a predetermined address with a predetermined address, and output terminals of the IM 15, AMu 16, AM1 18, EMu 20, and FM1 22, respectively. And an instruction latch 24, an address latch upper 26, an address latch row 28, a function latch upper 30, a function latch row 32, and the FMu 20, which are synchronously outputted by respective predetermined clocks. And store logic 34 for inputting and outputting the output information of the FM1 22 and providing the result as a control signal, and data such as an operand of each node of each column, for example, an input relay, an output relay, and a control relay. Received from the I / O processor as memory An upper data memory 36 and a low data memory 38 for storing data and outputting an analysis result of ladder logic to the input / output processor by the addresses of the AMu (16) and the AM1 (18); and the DMu (36). And an upper predata latch 40 for storing the output data of the DM1 38 in synchronization with a clock, and the output terminal of the FMu 20 and the FM1 22, respectively. 20) or the first and second decoders 44 and 46 for decoding the output of the FM1 22 and outputting function code information, and the outputs of the first and second decoders 44 and 46 are predetermined. The upper function code latch 48 and the low function code latch 50, which are latched and outputted in synchronization with a clock, and the output of the current ladder logic by inputting the outputs of the PDLu 40 and the FCLu 48. (52) and a low pre-shoulder (54) for inputting the outputs of the PDL1 (42) and the FCL1 (50) to obtain the current leader logic result; The data latch 56 stores and latches the temporary result of the performed column of the PSu 52 and the operations of the PS1 52, and outputs one column to the output of the DL 56 and the output of the IL 24. And a shoulder latch (58) for obtaining the OR operation information, and a limit latch for temporarily storing the output of the shoulder (58) by a clock.

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