JP2792778B2 - Programmable controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller (hereinafter referred to as "PC"), and more particularly to a PC optimally used for applications requiring high speed / high functionality.

[0002]

2. Description of the Related Art FIG. 14 is a block diagram showing a conventional PC. Reference numeral 1 denotes a sequence program memory (hereinafter referred to as S) for storing a sequence program created by a user.
2 is a device RAM for storing device information such as input information (device X), output information (device Y), and data information (device D) calculated by the PC according to the contents of SPM1, and 3 is stored in SPM1. A CPU 4 for processing the executed instructions, a system ROM 4 for describing the processing contents of the CPU 3, and a RAM 101 for storing the operation result (signal flow) of the SPM1.

FIG. 15 is a diagram of a conventional ladder circuit, which operates as follows. Input condition X ₀ ( _{0 of} device X
If the bit information at the address is ON, the MOV command (transfer command) is executed, and the contents of the data device D ₀ (word information) on the source side are transferred to the data device D ₁ on the destination side. MO if input condition X ₀ is OFF
Run the V command to transfer the contents of D ₁ to D ₁ (MOV
If the instruction is not executed, the operation is the same, and the destination retains the data.)

If the input condition X ₁ is ON, the MOV instruction is executed, and the value of 100 of the hexadecimal constant (H) on the source side is transferred to the data device D ₂ on the destination side. If the input condition X ₁ is OFF, the same as above.

[0005] Type Condition X ₁₁ is as by if ON PLS instruction (rising differential output command) of the timing chart shown in FIG. 16, after the output device Y ₃ is X ₁₁ is rising, the ON only for one scan, also, PLF the instruction (falling differentiated output instruction), as shown in the timing chart of FIG. 16, the output Y ₄ after a falling is X _11, are processed by software instructions to the oN only for one scan.

Next, the operation will be described. In FIG. 14, the CPU 3 sequentially reads and executes programs stored in the SPM 1 in ascending order of address. At this time, if there is a MOV instruction in the program,
The transfer instruction code is decoded by the software instruction, and the contents of the device RAM 2 indicated by the source address are stored in the CP.
It is stored in an internal register (not shown) of U3. Next, the content stored in the internal register is stored in the device RAM 2 indicated by the destination address.

When a PLS instruction is present in a program, C
PU3 by software instructions, decodes the differential output instruction code, with reference to the operation result of the last scan of X ₁₁ signal flow storage RAM 101, before scanning OFF
In, and, ON only Y ₃ when scanning current is ON
And, in the last scan is ON, and the scan current is turned OFF Y ₃ when is ON. If there is a PLF instruction, X
Refers to the calculation result of ₁₁ previous scans, and the previous scan is ON
In, and, ON only Y ₄ when scanning current is OFF
And otherwise it turns OFF the Y _4.

[0008] In addition, as reference technical documents related to the present invention, "Processing system for differential instruction of sequencer" disclosed in JP-A-2-8909 and JP-A-3-11.
"Pipeline control mechanism" disclosed in Japanese Unexamined Patent Publication No. 3-46028, "Instruction processing system" disclosed in Japanese Patent Application Laid-Open No. 3-46028, and "Pipeline control mechanism" disclosed in Japanese Patent Application Laid-Open No. 64-76226. Method ", JP 6
There is a "vector data processing device control method" disclosed in Japanese Patent Application Laid-Open No. 0-69746.

[0009]

Since the conventional PC is configured as described above, the processing is executed by software instructions, and as a result, transfer instructions and differential instructions cannot be processed at high speed. was there.

Also, Japanese Patent Laid-Open Publication No. Hei 2-8909 discloses hardware processing of a differential instruction. However, in this prior art, an extra RAM is required for a work area of the differential instruction, and There was a problem that the number of points increased and the apparatus became expensive.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and a PC capable of reducing the cost of a device without using an extra memory and increasing the speed of a transfer instruction and a differential instruction is provided. The purpose is to gain.

[0012]

According to the present invention, a PC is provided.
Sequence program storage means for storing sequence programs, device storage means for storing device results, pipeline registers for sequentially reading sequence programs stored in the sequence program storage means, and temporary storage of the contents of the device storage means And a shift register for temporarily storing the result of the hardware operation means.

A data register for temporarily storing the source device stored in the device storage means;
In the transfer command between the devices, when the shift register is ON, the contents of the data register temporarily storing the source device are written into the device storage means.

Further, constant latch means for temporarily storing the contents of the pipeline register is provided, and the value of the constant stored in the constant latch means is temporarily stored in the data register. When the shift register is ON, the contents of the data register temporarily storing a constant value are written to the device storage means.

Further, when the shift register is OFF, a specific value is written to the device storage means.

Also, bit designation latch means for latching a signal outputted from the pipeline register, a decoder for bit-converting a signal outputted from the bit designation latch means, and a specific signal outputted from the device storage means. A selector for selecting a bit; and a bit processing unit for processing a signal to be written to a device storage unit based on an output from the decoder.
When N, the decoder and the bit processing means set a predetermined bit of the device storage means to 1, and the hardware calculation means calculates the contents of the shift register and the contents of the selector. This is to write to the shift register.

Further , the hardware operation means may include
The contents of the inverted output of the shift register and the contents of the selector
Falling one scan O with AND
It outputs N instructions.

Further, the hardware operation means includes
Of the contents of the shift register and the inverted output of the selector.
1 scan O which takes the logical AND (AND) of the volume
It outputs N instructions.

Further, the hardware operation means includes
The logical sum of the contents of the shift register and the contents of the selector
Outputs 1-scan delay OFF command with (OR) taken
Things.

Further, the hardware operation means may include
Logical product of the contents of the shift register and the contents of the selector
Outputs a one-scan delay ON command that takes (AND)
Things.

[0021]

In the PC according to the present invention, the source device stored in the device storage means is temporarily stored in the data register. When the shift register is turned on in the transfer instruction between the devices, the contents of the data register temporarily storing the source device are stored. Is written to the device storage means.

Further, the contents of the pipeline register are temporarily stored in the constant latch means, the value of the constant stored in the constant latch means is temporarily stored in the data register, and the shift register is turned on by a constant / device transfer instruction. At this time, the contents of the data register in which the value of the constant is temporarily stored are written to the device storage means.

When the shift register is off, a specific value is written to the device storage means.

When the shift register is ON, the decoder and the bit processing means set a predetermined bit of the device storage means to 1, and the hardware calculation means calculates the contents of the shift register and the contents of the selector. Write the result to the shift register.

Also, the hardware operation means may be provided with a shift register.
Logical product of the contents of the inverted output of the register and the contents of the selector
(ON) is issued and the falling 1 scan ON command is issued.
Power.

Also, the hardware operation means may include a shift register.
Logical product of the contents of the register and the contents of the inverted output of the selector
(ON) and issued a rising 1 scan ON command
Power.

Also, the hardware operation means may be provided with a shift register.
The logical sum (OR) of the contents of the register and the contents of the selector is calculated.
A single scan delay OFF command is output.

Also, the hardware operation means is provided with a shift register.
The logical product (AND) of the contents of the register and the contents of the selector
The one-scan-delay ON command is output.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a main configuration of a PC according to the present invention. Reference numeral 1 denotes an SPM storing a sequence program created by a user, 2 denotes input information (device X) calculated by the PC according to the contents of SPM1, and output. A device RAM for storing device results such as information (device Y), data information (device D), and 3 is software (hereinafter, referred to as S / W) for adding and subtracting instructions written in the SPM1.
A CPU that executes this instruction in the case of processing;
5 is a system ROM that describes the processing contents of
3 and a sequence control circuit for controlling a hardware (hereinafter referred to as H / W) processing circuit to be described later.
, A pipeline instruction register (hereinafter referred to as a B2R register) for reading the contents described in order from address 0, a pipeline instruction register (hereinafter referred to as a B3R register) 7 for reading the contents of the B2R register 6, and 8 a CPU 3
Is a B4R register for storing the result of processing the S / W instruction.

9 is the content (instruction) of the B2R register
Decoding circuit (hereinafter referred to as DEC),
Reference numeral 10 denotes a pipeline register DECL (1) for reading the contents of the DEC 9, and reference numeral 11 denotes a pipeline register DECL (2), 12 for reading the contents of the DECL (1) 10.
For example, an oscillation circuit for generating a reference clock MCK of 40MH _Z, clock generating circuit 13 for generating various clocks with the MCK of the oscillation circuit 12, 14 the device R
In addition to controlling the address, data, read, and write signals of AM2, INCK, DECL (2) 11
H / W control circuit for generating the CK clock.

Reference numeral 15 denotes 00-1 of the B3R register 7.
A constant latch for storing the contents of 5 bits, 16 is a device RAM bit designation latch for storing 16 to 19 bits of the B3R register 7, and 17 is a device RAM.
Device RAM latch for storing the second contents, 18 device RAM from the 16-bit data D ₀₀ to D ₁₅ of the latch 17, 16TO1 selector for extracting only the bits of information specified in the device RAM bit designation latch 16, 1
Reference numeral 9 designates 4-bit data B3R16 to 19 of the device RAM bit designation latch 16 as 16-bit data BIT00 to
This is a 4TO16 decoder for decoding to 15.

Reference numeral 20 denotes an H / W operation circuit for calculating input conditions of a ladder circuit described later, and 21 denotes an H / W operation circuit 20
, A shift register (hereinafter referred to as a B register) 22 for storing the result of the device RAM 2 (device RA).
M latches D ₀₀ to ₁₅ ) and information of SPM1 (constant latch I
D ₀₀ ~ ₁₅₎ data register (hereinafter to store, called D registers), word processing circuit writing the word operation results when MOUT and MZOUT instructions later in the device RAM2 23, described later 24 OUT instruction or EGP, EG
At the time of an edge instruction of F, EGS, and EGC, only a designated bit of the 4TO16 decoder 19 is replaced with the operation result, and other bits are a bit processing circuit that returns the data of the device RAM latch 17 to the device RAM 2 as it is.

FIGS. 2A to 2E are ladder circuit diagrams of the present invention. FIG. 2A operates as follows. That is, the input condition X ₀ (1 bit information of the input information device X) is O
If N (1), the MLD (the load device RAM2) instruction, reads the data of the data device D ₀ from the device RAM2, MOUT (device RAM2
Writing the contents of the D ₀ data device D ₁ by a write) instruction to (even the same function during MZOUT instructions). If the input condition X ₀ is OFF (0),
The MOUT instruction after executing the LD instruction, D to D ₁
Writes the _first content, the content of D ₀ is (the same functions unless executed) is not written and, if MZOUT instruction, input conditions X ₀ OFF times, rewrites all 0 to D _1. Next, input condition X ₁₁ is as long as ON (1),
The EGP instruction output device Y ₃ rising one scan only to ON (1).

In the case (b), E is used instead of the EGP instruction.
X ₁₁ is ON after the GF instruction, falling only one scan Y ₃ to ON (1). For (c), Y ₃ is ON X ₁₁ is 1 scan delay after ON by EGS instruction
(1). For (d), X ₁₁ is the Y ₃ in one scan delay after ON to OFF (0) by EGS instructions.
(E) shows that MLD D ₀ is larger than that of (a) in ILD H _100.
And the input condition X ₀ is ON (1)
At the time, by the ILD (immediate load) instruction,
₁₀₀ (H stands for hexadecimal 100)
MOUT (MZOUT) instruction by transferring the H ₁₀₀ to D _1.

FIG. 3 shows the details of the contents of the ladder circuit shown in FIG. 2A. The data and addresses of the SPM 1 and the device RAM 2, the B register 21 and the D register 22 are shown in FIG.
Represents the contents of FIG. 4 shows the contents of FIG. 3 in more detail. FIG. 5 is an internal timing chart when the ladder circuit of FIG. 2A is operated. FIG. 6 shows the internal operation at the time of the MOUT instruction for the part A in FIG. 2A. FIG. 7 shows an internal operation at the time of the MOUT instruction in FIG. FIG. 8 shows the internal operation at the time of the MZOUT instruction for the part A in FIG. FIG.
5 shows the internal operation at the time of the MZOUT instruction in FIG.
FIG. 10 shows the EG for the portion A in FIG.
This is an internal operation at the time of the P instruction. FIG. 11 shows the internal operation at the time of the EGF instruction for the part A in FIG. 2A. FIG. 12 shows the internal operation at the time of the EGS instruction for the part A in FIG. 2A. FIG. 13 shows the state shown in FIG.
Of these, the internal operation at the time of the EGC instruction for the portion (a).

First, the pipeline read operation of the sequence program written in the SPM 1 will be described with reference to FIG. When the PC is run (RUN), CP is executed according to the contents (not shown) written in the system ROM 4.
After making initial settings such as setting of various registers, U3 activates the sequence control circuit 5 and sequentially reads the contents of SPM1 shown in FIG.

The basic operation of the CPU 3 is as follows. C
The PU3 normally executes an instruction to sequentially read the contents of the SPM1 and monitors the contents of the B2R register 6. If the 25th bit shown in FIG.
The contents of register 6 are stored in B3R register 7, and DEC
9 is transferred to the DECL (1) 10, and the H / W instruction is processed by a circuit described later. On the other hand, the 25th bit is 1 (S /
W instruction), the pipeline transfer is not performed (B3
R register 7, not transferred to DECL (1) 10),
The address in the S / W instruction is set in the program counter in the CPU 3, and the address is skipped to the corresponding address in the system ROM 4. If B ₀ described later is ON, the CPU 3 performs a predetermined S / W process. Also, if necessary, the CPU 3
The result of the S / W operation is transferred to the R register 8 and written to the SPM1. Next, the detailed operation of the H / W instruction in this embodiment will be described with reference to FIGS.

[0038] (1) Operation T1 period T1 is representative of the after LDX ₀ instruction is written to the address of the SPM 1 0000 ^H (see FIG. 4) is transferred to B2R register 6, at this time CPU3 Is H / W
The instruction is determined, and a control signal is output to the sequence control circuit 5. Further, in this period, in DEC9, it decodes the instruction, the LD output to 1.

(2) Operation in Period T2 At T2, (H /
W instruction = 1) LDX _{0 of} B2R register 6 is transferred to B3R register 7 and LD output of DEC 9 is
CL (1) after the transfer. Also, SP
MLD D ₀ of the address 0001 ^H of M1 is also transferred to the B2R register 6. In this period, the lower 00-15 bits device RAM2 address B3R register 7 (0000 ^H address SPM1 shown in FIG. 4)
Is output. After the access time of the device RAM2,
The device RAM data (0001 ^H = X ₀₎ shown in FIG.
X ₀ only ON of ～XF) is input into the device RAM latch 17.

(3) Operation in Period T3 T3 is the operation of the LD instruction and the device RA of the MLD instruction.
This is a period for reading M2 and transferring the MOUT instruction to the B2R register 6. DECL (2) at the beginning of this period
Eleven CKs occur. Address 0 of device RAM2
000 ^H of X ₀ ~XF data (0000 ^H) is then transferred to the device RAM latch 17, is input to 16TO1 selector 18. On the other hand, when the CK of the DECL (2) 11 occurs, the LD output of the DECL (1) 10
(2) While being transferred to 11, the B3R register 7
6- to 4-bit information 0000 ^H = 0 ^H (X
₀ represents the X ₀ of ~XF; 1 of SPM1 shown in FIG. 4
(Corresponding to 9 to 16 bits) is transferred to the device RAM bit designation latch 16, and then the 16TO1 selector 1
8 is input. The 16TO1 selector 18 stores the address 000 of the device RAM shown in FIG.
X ₀ (= 1) among X ₀ to _F of 0 ^H is extracted.

The LD output of the DECL (2) 11 is 1 during this period, and the gate of the tristate IC in the H / W arithmetic circuit 20 becomes active when LD = 1, so that the bit extraction M (= 1) is B _{0 of the} B register 21
Entered in the input. The B register 21 receives the clock input CK
, V2CK is input and LD = 1, so that two clock pulses are input during this period. On the other hand, since the mode input S ₀ receives the period 1 during this period and the S ₁ receives V3CK, the initial value (= 0000 ^H ) of the B register 21 is shifted rightward (Q ₀ → Q ₁ , Q ₁ →) in the first half clock pulse. Q ₂
... Q ₁₄ → Q ₁₅ , Q ₁₅ → overflow). In the latter half of the clock pulse, the parallel latch (B ₀ → A ₀ , Q
By performing _n → A _n (n = 1 to 15), the input condition calculation result BR ₀ becomes 1. The same operation as above is performed for the MLD and MOUT instructions.

(4) Operation in Period T4 T4 is a period during which the operation of the MLD command is performed, the device RAM read of the MOUT command and the transfer of the LD command to the B2R6 are performed. During this period, INCK and DECL (2)
A CK of 11 is generated, and similarly, D _{0 at} the address 4000 ^H of the device RAM (for example, as shown in FIG.
55 ^H ) is transferred to the device RAM latch 17. Also <br/>, MLD output of D ECL (2) 11 becomes the period 1. The H / W operation circuit 20 and the B register 21 do not operate.

Since the output of the device RAM latch 17 is input to the input terminal of the D register 22 and the SCK clock is input to the clock CK, D is input at the beginning of the next T5.
_{00 to} D ₁₅ (= 5555 ^H ) are latched. The same operation as described above is performed for the MOUT instruction and the LD instruction. still,
When the ILD instruction is used instead of the MLD instruction, the following operation is performed.

Unlike the MLD instruction, the ILD instruction cannot designate a device as D _0, and a constant value is previously stored in bits ₀ to 15 of the SPM 1 (H0100 in FIG. 2E).
Even during this period, the INCK and DECL (2) 11 C
K will occur, but the device RAM of INCK
H0100H is transferred to the output terminal of the constant latch 15, the output of the constant latch 15 is input to the input terminal of the D register 22, and the clock CK is not transferred to the latch 17.
, The SCK clock is input, so that ID ₀₀ to ₁₅ (= 0100 ^H ) are latched at the beginning of the next T5.

(5) Operation in Period T5 T5 is an operation period in which only the operation of the MOUT instruction is performed. Even during this period, the INCK and DECL (2) 11 CK
Occurs, and the address 4001 of the device RAM 2
^H ₁ (for example, the initial value AAAAA ^H as shown in FIG. 3) is transferred to the device RAM latch 17. Also, DEC
The MOUT output of L (2) 11 becomes 1 during this period.

In the word processing circuit 23, BR ₀ is 1 (X ₀ = ON) in the operation of T3.
Output to the D register 22 (= 5555 ^H is latched by the operation of the T4) is turned V8D ₀₀ ~ _15, the device R
Output to AM2. Here, BR ₀ = 0 (X ₀ = OF
F) If D ₀₀ -D _{00 of the} device RAM latch 17
₁₅ (AAAAA ^H ) is returned to the device RAM 2 as it is (the same operation as non-execution).

When the MZOUT instruction is used instead of the MOUT instruction, the following operation is performed. When BR ₀ = 1, the same operation is performed, but when BR ₀ = 0, the operation is forcibly 0000.
^H is output to the device RAM2. That is, if the input condition is O
When N, the data of the transfer source device is transferred to the transfer destination device, but when OFF, 0000 ^H is forcibly output to the transfer destination device. Since the device RAM read at the time of the MZOUT instruction has the configuration of DEC9, the V8RD output is 0 and the device R
AM2 data is not output.

(6) Operation in Period T6 T6 is a period in which no operation is performed.
G2 B2R transfer is performed.

(7) Operation in Period T7 T7 is the same as that described above, and a description thereof will be omitted.

(8) Operation in Period T8 The calculation of EG □ (assumed to be a generic command of EGP, EGF, EGS, and EGC) will be described using EGP as an example. Even during this period, CK of INCK and DECL (2) 11
Occurs, E ₀ to _F (for example, the initial value 0000 ^H as shown in FIG. 3) of the address 6000 ^H of the device RAM are transferred to the device RAM latch 17, and then L 3 of T 3
As in the case of the D instruction operation, it is input to D (data) of the 16TO1 selector 18. On the other hand, the CK of DECL (2) 11
Due to the occurrence, the EGP output of the DECL (2) 11 becomes 1 during this period, and 4bi of B3R16 to B3R16 to 19 of B3R7.
t bit information 0010 = 2 ^H (SPM1 shown in FIG. 4)
After representing the E ₂₎ of the E ₀ ~ _F of is transferred to the device RAM bits specified latch 16, and S (selector) of 16TO1 selector 18 is input to 4TO16 decoder 19.

Bit extraction M from 16TO1 selector 18
Contains the address 6000 ^{H of the} device RAM shown in FIG.
E ₂ (= 0) in E ₀ to _F of the above are extracted. The gate of the tristate IC in the H / W arithmetic circuit 20 is EGP
= 1, the bit extraction M (= 0)
(Because LDX ₁₁ is a ON, T7 in BR ₀ is that a 1) of the inverter output and the BR ₀ output by AND operation becomes one, which is input to the B ₀ is input to register B 21. During this period, the B register 21 receives the clock input CK.
, And EGP = 1, so that two clock pulses are input during this period. On the other hand, since V3CK is input to both S ₀ and S ₁ , the first half clock pulse is unprocessed because S ₀ = S ₁ = 0, and the second half clock pulse is a parallel latch (B ₀ → A ₀ , Q _n
→ A _n ), and BR ₀ changes from 1 → 1, that is, does not change.

In the above-mentioned 4TO16 recorder 19, only the bit-designated one becomes 1. Here next only BIT ₀₂ is 1 since the ID ₁₆ ~ ₁₉ is 0010 = 2 ^H, the other is zero. BIT ₀₀ to BIT ₁₅ are used in the bit processing circuit 24, and 0 of BIT ₀₂ to BIT ₁₅ is a device R
D ₀₀ to ₁₅ of the AM latch 17 and BR _{0 are}
(Here, 1) is output to the device RAM2. Here, BIT ₀₂ is 0000 ^{H of} D ₀₀ to ₁₅ from 1
But the 0004 ^H in V8D ₀₀ ~ _15.

(9) Operation in Period T9 During this period, as shown in FIG. 5, no processing is performed on the device RAM2, and the same operation as that of T8 is performed on the B register 21. I haven't.

(10) Operation in Period T10 The operation of the OUT instruction will be described. Even during this period,
CK and CK of DECL (2) 11 are generated, and Y _{0 to} YF at address 2000 ^H of the device RAM 2 are generated in the same manner as described above.
There is transferred to the device RAM latch 17D ₀₀ ~ _15. On the other hand, when CK of DECL (2) 11 occurs,
(1) The OUT output of 10 is transferred to the DECL (2) 11, and OUT = 1, and B3R16 to B3R1 of B3R7
9 4-bit information 0011 = 3 ^H (Y out of Y _{0 to} YF)
After representing the ₃₎ is transferred to the device RAM bits specified latch 16, is input to 4TO16 decoder 19, the same operation as EGP the T7, it becomes 1 only BIT3, others are zero. BIT00～15 is used in the bit processing circuit 24, those of 0 among BIT00~15, D ₀₀ ~ ₁₅ of the device RAM latch 17, also,
In the case of device 1, the contents of BR ₀ (1 in this case) are device R
Output to AM2. Here, BIT03 = 1 and D
₀₀ 0000 ^H to ₁₅ becomes the V8D ₀₀ ~ ₁₅ in 0008 ^H. That is why X ₁₁ is the ON at Y ₃ has turns ON.

(11) Operation in Period T11 T11 is a period in which no operation is performed.
B2R transfer of UT instruction is performed. The transfer command is as described above, and only the transfer command has been outlined in FIGS. 6 to 9 (the edge command is omitted).

[0056] FIG. 6-9 is an operation when the X ₀ is turned ON before 1 scan END, the second scan MOUT
, And a predetermined output is transferred after execution of the MZOUT instruction.
The operation of the edge instruction cannot be described with reference to FIG. 5 alone, and will be described with reference to FIGS.

(12) EGP Command Operation The EGP command operation will be described with reference to FIG. First
Since the scanning operation is a X ₁₁ = OFF, the LDX ₁₁ BR ₀ = _0, EGP in BR ₀ = 0 from the device RAM
2 To output the 0000 ^H the AND processing of an inverter output of the M (= 0) in the BR with (input D ₀₀ ~ ₁₅ The same as the same result a is untreated and) ₀ (= 0) D ₀₀ ~ ₁₅ were the ones written to the B register 21 (= 0) OUTY ₃ in BR ₀ (= 0) to be 0000 ^H output device RAM (input D ₀₀ ~ ₁₅ identical to the same result in and untreated with). The second scanning operation is as shown in FIG. 5 described above.

In the third scan operation, the LDX ₁₁ is the same as the second scan (however, the B register 21 is shifted to the right). In EGP, since the bit 2 of the inputs D ₀₀ to ₁₅ is 1 in the second scan, the AND processing result BR ₀ is 0
Rewritten. From OUTY ₃ in BR ₀ = 0, the device RAM outputs 0000 ^H becomes, Y ₃ is turned OFF. Hereinafter, Y ₃ remains OFF in the fourth step as well. Therefore, the EGP instruction rises 1 after X ₁₁ is turned on.
Scanning only Y ₃ is turned ON.

(13) EGF Instruction Operation The EGF instruction operation will be described with reference to FIG. The difference from the above-mentioned EGP is the input information of the AND processing and BR ₀
It has become a M in the inverter output of the D ₀₀ ~ _15. A
The ND process output = 1 (thus, Y ₃ is ON) is given, only 4 scanning eyes after post as X ₁₁ OFF shown in FIG. 11, once again turned OFF at 5 scans eyes. Thus, EGF instruction X ₁₁ OFF after the falling only one scan Y ₃ is turned ON.

(14) EGS Command Operation The EGS command operation will be described with reference to FIG. EG
The difference from P is that it is input information for AND processing and there is no inverter. AND processing output = 1 and becomes (a result, Y ₃ is ON) as from FIG. 12, a third scan th X ₁₁ ON after one scan delay, the Y ₃ in X ₁₁ OFF after the next scan It turns off. Therefore, EGS instruction Y ₃ is turned ON at 1 scan delay after X ₁₁ ON.

(15) EGC Command Operation The EGC command operation will be described with reference to FIG. EG
The difference from S is that AND is ORed. O
R processing output = 1 and becomes (a result, Y ₃ is ON)
It is as shown in FIG. 13, ON Suruga in X ₁₁ ON after the next scan, after X ₁₁ OFF, Y ₁₃ is turned OFF at successive scan to. Therefore, EGC instruction Y ₃ is turned OFF in a single scan delay after X ₁₁ OFF.

[0062]

As described above, according to the present invention, it is possible to process an input command and a transfer command (LD + MLD + MOUT command) at a very high speed of four cycles. For example, although it depends on the performance of an IC, Reference clock MCK = 40
Operation at MH _z enables treated with 75 _ns (1 cycle) × 4 cycles = 300 _ns.

The input condition OFF and 000 are added to the transfer command.
0 because ^H have added the forwarding instructions (MZOUT), creation of the sequence program is simplified, thereby reducing the number of steps.

Further, since four types of edge instructions are constituted by the H / W circuit, it becomes possible to process the LD + EG □ + OUT instruction at extremely high speed of five cycles.

[Brief description of the drawings]

1 is a block diagram showing the configuration of a P C according to the present invention.

FIG. 2 is a ladder circuit diagram showing an operation of the PC shown in FIG. 1;

FIG. 3 is an explanatory diagram showing detailed contents of a ladder circuit shown in FIG.

FIG. 4 is an explanatory diagram showing the contents shown in FIG. 3 in more detail;

FIG. 5 is a timing chart showing an operation of the ladder circuit shown in FIG.

FIG. 6 is an explanatory diagram showing an internal operation at the time of a MOUT instruction for A in FIG.

FIG. 7 is an explanatory diagram showing an internal operation at the time of a MOUT instruction in FIG. 2B;

FIG. 8 is an explanatory diagram showing an internal operation at the time of an MZOUT instruction for A in FIG.

FIG. 9 is an explanatory diagram showing an internal operation at the time of an MZOUT instruction in FIG. 2 (b).

FIG. 10 is an explanatory diagram showing an internal operation at the time of an EGP instruction with respect to a in FIG. 2A.

FIG. 11 is an explanatory diagram showing an internal operation at the time of an EGF instruction for A in FIG. 2A.

FIG. 12 is an explanatory diagram showing an internal operation at the time of an EGS command for A in FIG. 2A.

FIG. 13 is an explanatory diagram showing an internal operation at the time of an EGC instruction for A in FIG. 2A.

FIG. 14 is a block diagram showing a schematic configuration of a conventional PC.

FIG. 15 is a ladder circuit showing an operation of the PC shown in FIG. 14;

FIG. 16 is a timing chart showing a conventional PC differential output command.

[Explanation of symbols]

 1 SPM 2 Device RAM 3 CPU 4 System ROM 5 Sequence control circuit 6 B2R register 7 B3R register 8 B4R register 9 DEC 10 DECL (1) 11 DECL (2) 12 Oscillator 13 Clock generator 14 H / W control circuit 15 Constant Latch 16 Device RAM bit designation latch 17 Device RAM latch 18 16 TO1 selector 194 4TO16 decoder 20 H / W operation circuit 21 B register 22 D register 23 Word processing circuit 24 bit processing circuit

Claims (9)

(57) [Claims] 1. A sequence program storage means for storing a sequence program, a device storage means for storing a device result, a pipeline register for sequentially reading sequence programs stored in the sequence program storage means, and the device storage means Means for temporarily storing the contents of the hardware operation, hardware operation means for operating hardware instructions at high speed, and a hardware operation result register for temporarily storing the result of the hardware operation means.
Programmable controller comprising the register. 2. A data register for temporarily storing a source device stored in said device storage means, wherein a hardware operation result is provided in a transfer instruction between devices.
2. The programmable controller according to claim 1, wherein when the register is ON, the contents of the data register temporarily storing a source device are written to the device storage means. 3. A constant latch means for temporarily storing the contents of the pipeline register, a constant value stored in the constant latch means being temporarily stored in the data register, and a constant / device transfer instruction for transferring the constant value. Hardware performance
2. The programmable controller according to claim 1, wherein when the calculation result register is ON, the content of the data register temporarily storing a constant value is written to the device storage means. 4. The hardware operation result register according to claim 1, wherein
4. The programmable controller according to claim 2, wherein a specific value is written to the device storage unit when the FF is set. 5. A bit designation latch means for latching a signal output from the pipeline register, a decoder for bit-converting a signal output from the bit designation latch means, and a specific signal output from the device storage means. a selector for selecting the bit, provided the bit processing means for processing a signal to be written to the device memory means based on the output from the decoder, the hardware operation results Les
When register is ON, with putting a 1 to a predetermined bit of said device memory means by said decoder and the bit processing means, wherein the said hardware computing means hardware
The programmable controller according to claim 1, wherein the contents of the operation result register and the contents of the selector are operated, and the operation result is written in the hardware operation result register . 6. The hardware operation means according to claim 1 , wherein
The contents of the inverted output of the hardware operation result register and the
Falling 1 obtained by taking the logical product (AND) of the contents of the vector
6. A scan ON command is output.
The programmable controller as described. 7. The hardware operation means according to claim 7 , wherein
Hardware operation result register and the contents of the selector
Rise 1 obtained by taking the logical product (AND) of the contents of the inverted output
6. A scan ON command is output.
The programmable controller as described. 8. The hardware operation means according to claim 1 , wherein
Hardware operation result register and the contents of the selector.
1 scan delay OFF instruction with logical sum (OR)
6. The programmer according to claim 5, wherein
Bull controller. 9. The hardware computing means according to claim 1 , wherein
Hardware operation result register and the contents of the selector.
1 scan delay ON command that takes the logical product of AND (AND)
6. The programmer according to claim 5, wherein
Bull controller.