JP3118824B2 - Microprocessor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applied to a microprocessor.

The invention particularly relates to high-speed microprocessors operating at high frequencies.

〔Overview〕

The present invention simplifies the processing procedure in a microprocessor by delaying the input of a ready signal for a bus cycle as needed by an extended ready signal that is input after the end of a bus cycle separately from the ready signal, and This is for speeding up.

[Conventional technology]

Conventional microprocessors, as shown in FIG.
An execution unit 1 for actually executing an instruction, a bus control unit 2 for controlling an external bus cycle, a prefetch pointer 3 for prefetching an instruction, and a prefetch queue 4 for temporarily storing the prefetched instruction When,
A predecoder 5 for analyzing prefetched instructions;
And a ready (READY) signal 6 input to the bus control unit 2.

Next, an operation of the conventional example will be described with reference to a timing chart shown in FIG.

When the microprocessor reads a program from outside, the prefetch pointer 3 outputs a fetch address to the bus control unit 2. The bus control unit 2 activates a bus cycle according to the information from the prefetch pointer 3, and waits until the ready signal 6 becomes active (here, the “L” level is active).
As shown in state T _W in FIG, extend the bus cycle. When the active state of the ready signal 6 is sampled, the bus control unit 2 ends the bus cycle and sends the instruction read from the external data bus 10 to the prefetch queue 4. The prefetch queue 4 sends the instruction word to the predecoder 5, and the predecoder 5 analyzes the sent instruction word and outputs it to the execution unit 1.

That is, according to the conventional example, the instruction is transferred to the prefetch queue 4 after the ready signal 6 becomes active, and then the analysis and execution are performed. It was getting longer. This means that the execution time becomes longer because a wait is inserted in consideration of the longest access to the memory.

[Problems to be solved by the invention]

In the above-described conventional microprocessor, an instruction is transferred to a prefetch queue after the active state of a ready signal is sampled, and then the instruction is analyzed and executed. Had the disadvantage of being slow.

The object of the present invention is to eliminate the disadvantages mentioned above,
It is an object of the present invention to provide a microprocessor whose execution speed is increased.

[Means for solving the problem]

The present invention relates to an execution unit that actually executes an instruction, a bus control unit that controls an external bus cycle by an input ready signal, and a data transmission / reception unit that transmits and receives data between the execution unit and the bus control unit. In the microprocessor having the above, the ready signal and an extended ready signal that is input after the end of the bus cycle are input, and the extended ready signal is used to control the ready signal so that the internal ready signal is sent to the bus control unit again. A ready control circuit for inputting and outputting an internal extended ready signal for controlling the operation of the data transmitting / receiving means.

Further, according to the present invention, the ready control circuit samples the level of the extended ready signal at the rising edge of the first state of a bus cycle and sets the output as the internal extended ready signal. Means for sampling at the rising edge of the first state of the next bus cycle and outputting a signal obtained by delaying the ready signal by one clock as the internal ready signal when the state is inactive.

Also, in the present invention, the data transmission / reception means includes a prefetch pointer for prefetching the instruction, a prefetch queue for temporarily storing the prefetched instruction, and a predecoder for analyzing the prefetched instruction and inputting it to the execution unit. The prefetch pointer, the prefetch queue, and the predecoder include means for clearing an instruction fetched in the immediately preceding bus cycle by the internal extension ready signal and accessing the same address again in the next bus cycle. be able to.

[Action]

The extension ready signal is input after the end of the bus cycle.
The ready control circuit samples the level of the extended ready signal in the first state of the bus cycle, uses the output as an internal extended ready signal for data transmission / reception means, and samples the internal extended ready signal again in the first state of the next bus cycle. In the inactive state, a signal obtained by delaying the ready signal by one clock as an internal ready signal is output to the bus control unit. When the internal extension ready signal is in the inactive state, the data transmitting / receiving means clears the instruction fetched in the immediately preceding bus cycle and accesses the same address again in the next bus cycle.

Therefore, it is not necessary to always extend the bus cycle until the ready signal becomes active as in the conventional case. If necessary, the bus cycle is extended by the extended ready signal and its activation is performed, thereby increasing the processing speed. Can be achieved.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a main part of an embodiment of the present invention.

In this embodiment, an execution unit 1 that actually executes an instruction
A prefetch for prefetching an instruction as a bus control unit 2 for controlling an external bus cycle by an input ready signal 6 and a data transmission / reception unit for transmitting / receiving data between the execution unit 1 and the bus control unit 2 In a microprocessor including a pointer 3, a prefetch queue 4 for temporarily storing prefetched instructions, and a predecoder 5 for analyzing prefetched instructions and inputting them to the execution unit 1, a ready signal, which is a feature of the present invention, is provided. 6 and an extended ready signal 14, which is inputted after the end of the bus cycle, separately from the ready signal 6,
The ready control circuit 13 which controls the ready signal 6 by the extended ready signal 14 and inputs it again as the internal ready signal 16 to the bus control unit 2 and outputs the internal extended ready signal 15 for controlling the operation of the data transmission / reception means. Have.

Then, the prefetch pointer 3, the prefetch queue 4, and the predecoder 5 clear the instruction fetched in the immediately preceding bus cycle by the internal extended ready signal 15, which is a feature of the present invention, and again in the next bus cycle. Means for accessing the same address are included within each.

FIG. 2 is a block diagram showing an example of the ready control circuit 13.

The ready control circuit 13 is connected to the clock signal 17
Clock signal 19 takes a logical product of the T ₁ signal 18 for instructing the T ₁
An AND circuit 31 for outputting, an OR circuit 32 for ORing the ready signal 6 and T ₁ signal 18, the flip of outputting the internal expansion ready signal 15 thereof is inverted captures the extended ready signal 14 by the clock signal 19 And a flip-flop 34 that captures and outputs the output of the OR circuit 32 by the clock signal 17 and a flip-flop that captures the internal extended ready signal 15 output from the flip-flop 33 by the clock signal 19 and outputs the control signals 20 and 21, respectively. Step
35, a control buffer 36 that outputs the output of the flip-flop 34 as the internal ready signal 16 according to the control signal 20, and a control buffer 37 that outputs the ready signal 6 as the internal ready signal 16 according to the control signal 21.

Next, the operation of the ready control circuit 13 will be described with reference to the timing chart shown in FIG.

Flip-flop 33 is extended ready signal 14 takes the rising edge of the clock signal 19 is a logical product of the clock signal 17 and the T ₁ signal 18, and outputs the internal expansion ready signal 15 from the output of the _1.

Flip-flop 35 takes in the internal expansion ready signal 15 at the next rise of the clock signal 19, control signal 20 as the Q ₂ output, outputs a control signal 21 as a _second output, respectively.

On the other hand, the flip-flop 34 is a ready signal 6 captures the ready signal 6 and T ₁ signal 18 is delayed one clock output from the Q ₀ output by the clock signal 17.

When the control signal 20 is inactive and the control signal 21 is active, the ready signal 6 is output as it is as the internal ready signal 16. On the contrary, the ready signal 6 delayed by one clock is used as the internal ready signal 16. Is output as

That is, in the ready control circuit 13 samples the level of the extended ready signal 14 at the clock rising edge of the state T _1, its output internal expansion ready signal 15. Further, the internal expansion ready signal 15 is sampled again clock the next rise of T ₁ state, and if that state is inactive, the ready signal propagating therein is delayed by one clock, and the internal ready signal 16.

Next, the overall operation of this embodiment will be described with reference to the timing chart shown in FIG.

As described above, the internal ready signal 16 output from the ready control circuit 13 is input to the bus control unit 2 as in the case of the conventional example shown in FIG. The internal extension ready signal 15 is input to the prefetch pointer 3, prefetch queue 4, and predecoder 5. When the internal extension ready signal 15 becomes inactive, each block clears the fetched instruction in the bus cycle immediately before the block becomes inactive and accesses the same address again in the next bus cycle. That is, it returns to the address of the immediately preceding instruction.

According to the present embodiment, when the extended ready signal 14 becomes inactive following a certain bus cycle (1), the bus cycle (1) is re-executed after the bus cycle (2) being executed at that time, And the bus cycle is 1
It can be extended by the clock (T _{EW in} FIG. 4).

〔The invention's effect〕

As described above, according to the present invention, in addition to the conventional ready signal, an extended ready signal that can be input after the end of the bus cycle is added, so that the ready input for the bus cycle can be delayed if necessary. In a system that generates a ready signal by using a complicated procedure, such as a system that uses, a delay ready input is allowed, and the bus cycle can be sped up.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a circuit diagram showing an example of the ready control circuit. FIG. 3 is a timing chart of the ready control circuit of FIG. FIG. 4 is a timing chart of the embodiment of FIG. FIG. 5 is a block diagram showing a conventional example. FIG. 6 is the timing chart. 1 ... Execution unit, 2 ... Bus control unit, 3 ...
Prefetch pointer, 4 ... Prefetch queue, 5
... Predecoder, 6 Ready signal, 7 Internal address bus, 8 External address bus, 9 Internal data bus, 10 External data bus, 11 Internal data bus for instructions, 12 ... Predecoder output, 13 ... Ready control circuit, 14 ... Extended ready signal, 15 ... Internal extended ready signal, 16 ... Internal ready signal, 17, 19 ... Clock signal,
18 ...... T ₁ signal, 20, 21 ...... control signal, 31 ...... AND circuit, 32 ...... OR circuit, 33, 34, 35 ...... flip-flop, 36, 37 ...... control buffer.

Claims (3)

(57) [Claims] An execution unit for actually executing an instruction; a bus control unit for controlling an external bus cycle by an input ready signal; and a data transmission / reception for transmitting / receiving data between the execution unit and the bus control unit. Means for receiving the ready signal and an extended ready signal input after the end of a bus cycle, and controlling the ready signal by the extended ready signal to renew the internal control signal as an internal ready signal. And a ready control circuit for outputting an internal extended ready signal for controlling the operation of the data transmission / reception means. A means for sampling the level of the extension ready signal at the rising edge of the first state of a bus cycle and for setting the output as the internal extension ready signal; And a means for outputting a signal obtained by delaying the ready signal by one clock as the internal ready signal when the state is inactive when the first state of the bus cycle is sampled and the state is inactive. Processor. 3. The data transmission / reception means includes: a prefetch pointer for prefetching an instruction, a prefetch queue for temporarily storing a prefetched instruction, and a predecoder for analyzing a prefetched instruction and inputting it to the execution unit. The prefetch pointer, the prefetch queue,
3. The predecoder according to claim 1, further comprising means for clearing an instruction fetched in a previous bus cycle by the internal extension ready signal and accessing the same address again in a next bus cycle. Microprocessor.