JPH0322049A - Memory controller - Google Patents

Abstract

PURPOSE:To obtain a memory controller of high flexibility where the number of degrees of feedom of the operation mode is large by switching the operation mode to directly access a memory with the logical address outputted from a CPU or to access the memory with the address from an address converting means. CONSTITUTION:When the direct access mode is selected by an operation mode switching means 5, a memory 2 is directly accessed by the address outputted from a CPU 1. When the address conversion access mode is selected by the operation mode switching means 5, the address outputted from the CPU 1 is converted to the address of another system by a converting means 3 and the memory 2 is accessed by this converted address. Conversion contents are rewritten to freely set the system which the address from the CPU 1 is converted to the address of. Thus, a memory system is realized which has a large number of degrees of freedom and a high flexibility to accord with the operation mode of the CPU 1 and applications.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a memory control device that controls access to a main storage device, etc. in a compinator system.

As is well known in the art, large main memories are structured so that they can be operated simultaneously by dividing the entire memory into several modules, each with its own address and data buffer registers. The one who is the one who is the one who is the one who is the one who is the one who is the one. This is called multi-module memory, and each module that can operate simultaneously is called a bank. For example, if the number of banks is 2k and the size of the main memory is 2 addresses, then of the j pin addresses, k bits specify the module number, and l bits specify the position within the access unit. Therefore, j (k+i) Minuma Binotto is used to specify the position within the module. There are two ways of arranging the i, k, -g focus within the address information.

In the first method, the module number part is taken as the upper address, and the addresses are arranged in order from the lowest module number. In the second method, module number sections are taken in descending order and addresses are crossed across modules. This second method is called an interleaving method. When using the incubation method, information at consecutive addresses can be accessed in parallel, so it is very effective when accessing a large amount of information at the same time using advance control or when performing proactive transfer in cache memory. Therefore, large main memories often adopt this configuration. However, if the number of modules is changed, the address allocation must be changed, so the configuration flexibility and fault tolerance are inferior to the first method.

Problems to be Solved by the Invention In the conventional device described above, since the memory configuration and the bank switching control section are closely related in terms of hardware, the CP
The correspondence between the logical address output from U and the real address of the memory area is fixed, there is no degree of freedom, and there is little flexibility, which can be a constraint on the application program.

Modern CPUs are rapidly becoming more sophisticated, and the conventional mainstream 16-bit CPU is being replaced with a 32-pit CPU. What is important here is to make it possible to utilize conventional software resources even with a 32-bit CPU. Many 32-bit CPUs are faster than 16-bit CPUs
It has an operating mode as U, but 16 Bino}CP
32 pit CP with existing software used for U
Address space expansion is required to operate U.

However, when operating with software for a 32-bit CPU, the logical address space output by the CPU itself is sufficiently wide, so there is no need to use an indirect address space expansion method, and it is possible to access memory directly. can. Conventional devices have not been able to perform access control appropriate to the circumstances of such applications.

This invention was made in view of the above-mentioned conventional problems, and its purpose is to prevent the correspondence between the logical address output from the CPU and the real address of the memory area to be fixed, and to provide a high degree of freedom and flexibility in operating modes. An object of the present invention is to provide a memory control device.

Means for Solving the Problems Therefore, in the present invention, the memory control device includes address conversion means for associating a logical address output by the CPU with a predetermined real address in the physical address space of the memory, and a conversion content of the address conversion means. A conversion content setting means for arbitrarily rewriting, and an operation mode switching means for switching whether the memory is accessed directly using the logical address of the CPU or the Aill memory is accessed using the address from the address conversion means are provided.

Effect: When the direct access mode is selected by the operation mode switching means, the memory is directly accessed using the address output from the CPU. Further, when the address conversion access mode is selected by the operation mode switching means, the address output by the CPU is converted into an address of a different system by the conversion means, and the memory is accessed using the converted address. The type of address to be converted into by the conversion means can be freely set by rewriting the conversion contents.

Embodiment FIG. 1 shows a schematic configuration of a memory control device according to an embodiment of the present invention. This device has two modes: a mode in which the memory 2 is accessed directly using the address output from the cPU 1 (direct access mode), and a mode in which the address output from the cPU 1 is converted by the address converter 3 and the memory 2 is accessed (address conversion access mode). be.

When the CPUI turns off the mode switching flag 5, the direct access mode is entered. In this mode, the 32
The BINOTO address bus 6 is directly connected to the 32-bit address bus 7 on the memory 2 side via the bus gate section 4, and the CP
A 32-bit address output from Ul is directly input to and accessed from memory 2, and 32-bit data is read/written via data bus 9.

When the CPU 1 turns on the mode switching flag 5, the address translation access mode is entered. In this mode, the CPU
lower bits of the side address bus 6}AI9 to AO
is connected from the bus gate section 4 to the address bus 8 on the address conversion section 3 side (the upper 12 bits of the address bus 6)
31 to A20 are invalid).

When the CPUI outputs the binary addresses AI9 to AO, the lower 14 bits A13 to AO of them are inputted to the memory 2 via the Atres bus 8 on the A13 to AO of the Atres bus 7. In addition, the upper 6 bits 7 A19 to A14 of the additive bits output by the CPU 1 are input to the address manono ζ-11 via the multiplexer IO, and from this address manopar 11, the address of the l4 pinto of a different system is input. A2'7 to A14 are output, and these converted addresses A27 to A14 are output to A2'7 to A14 on the address bus 7.
14 and input into the memory 2.

Then, when CPU1 outputs the addresses AI9 to AO of Kabinoto, A13 to AO among them are those! 1 memory 2
address input, and the remaining AI9 to A14 are used as address master bar 11 to input 14 separate addresses A27 to Al.
4 and becomes the address input for memory 2. Therefore, memory 2 has the expanded address A27.
~AO is input, and 16 bits of data is read/written via the data bus 9.

The address manager 11 consists of SRAM, and any conversion contents can be written into it and rewritten as desired.
This makes it possible to freely set the address conversion system during address expansion.

When writing arbitrary contents to the address manoper 11, turn on flag 5 to set the address conversion access mode.
A chip select signal CS and a write signal R/W are applied to a multiplexer 10 button and an address manover 11. At this time, the address A5 of the lower 6 bits from CPU 1
~ When outputting AO, A5 ~ AO multiplexer 10
The data on the data bus 9 is then written to the address manoper 11 and then becomes an address input to the address manoper 11.

Effects of the Invention As explained in detail above, according to the memory control device of the present invention, the memory can be accessed directly using the address output by the CPU, or the memory can be accessed by converting the address output by the CPU into an extended address of a different system. In addition to being able to access the memory, the content of address conversion can be freely rewritten, and a memory system with a high degree of freedom and flexibility depending on the operating mode and specification of the CPU can be realized.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of a memory control device according to an embodiment of the present invention. 6, 7, 8...address bus.

Claims (1)

[Claims] an address conversion means for associating a logical address output by a CPU with a predetermined real address in a physical address space of a memory; a conversion content setting means for arbitrarily rewriting the conversion contents of the address conversion means; and a logical address output by the CPU. and operation mode switching means for switching between directly accessing the memory and accessing the memory using an address from the address conversion means.