CN1512373A - Method for multiple CPU communication - Google Patents
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- CN1512373A CN1512373A CNA021589100A CN02158910A CN1512373A CN 1512373 A CN1512373 A CN 1512373A CN A021589100 A CNA021589100 A CN A021589100A CN 02158910 A CN02158910 A CN 02158910A CN 1512373 A CN1512373 A CN 1512373A
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Abstract
The multiple-CPU communication method includes the following steps: to set hung memory spaces connected to CPU for mutual access, for the CPU in the sending party to write data message to be sent into the memory space connected to the CPU in the receiving party, to set register for generating interruption signal to receiving party CPU, and for the receiving party CPU to receive the data message after accepting the interruption signal; for the CPU in the sending party to write control message to be sent into the buffering area of the intelligent I/O unit, to create interruption signal of intelligent I/O unit transmitted to receiving party CPU, and for the receiving party CPU to receive the control message from the buffering area of the intelligent I/O unit after accepting the interruption signal. The present invention transmits data via different interruptions and passages, solves the safety problem of transmitting important data and raises data transmitting speed.
Description
Technical field
The present invention relates to communication technical field, be meant a kind of many CPU method for communicating especially.
Background technology
Along with computing machine and development of Communication Technique, single cpu can't satisfy people's demand, and many CPU technology is also just arisen at the historic moment thereupon.
Figure 1 shows that the master-slave mode multi-CPU structure.The general processor that will have powerful arithmetic capability is as host CPU, the CPU that communication controler or network processing unit etc. is had powerful communication control function and data forwarding ability finishes with extraneous and communicates by letter or the data forwarding function as the common PCI equipment on interface element interconnection (PCI:Peripheral ComponentInterconnection) bus.Like this, just have powerful operation capacity and fast data transfer capability simultaneously on a veneer, this structure is referred to as the master-slave mode multi-CPU structure.
At the master-slave mode multi-CPU structure, the scheme of " shared drive+mailbox agreement " is adopted in the communication between its CPU usually.Figure 2 shows that shared drive formula communication queue.In the space that each CPU can both have access to, set up two formations, adopt reception pointer (Precv) and send two pointers of pointer (Psend) to come formation is managed, Precv points to the current buffer zone address that is reading, and Psend points to the buffer zone address of depositing next data to be sent.The buffer zone that each formation is 2KB by 32 or 64 sizes is formed, and each buffer zone is deposited a needs data packets for transmission.Deposit host CPU in the formation 0 and issue data, regularly read, deposit the data of issuing host CPU from CPU in the formation 1, and host CPU also is regularly to read from CPU from CPU.
The mode that data send between master-slave cpu is identical, is that example illustrates data transmission procedure with host CPU to sending packet from CPU below.
Host CPU writes data randomly in formation 0, for prevent in each buffer zone packet do not have removed before, by new data rewriting, first long word that each buffer zone is set is a control bit.When data need write buffer zone, at first judge the content of first long word of buffer zone, if first long word of buffer zone is 0x5555aaaa, represent that then the packet in the current buffer zone is effective, also do not have removedly, can not write new data; If first long word of buffer zone is 0xaaaa5555, represent that then the packet in the current buffer zone is removed, can write new data.If the packet in each buffer zone of whole formation is all effective, new data will be dropped.
Periodically read data the formation 0 from CPU.Precv traverses rear of queue from the head of formation, in case find that first long word content of certain buffer zone is 0x5555aaaa, just the data read of this buffer zone is come out, and simultaneously first long word of this buffer zone is revised as 0xaaaa5555.From the setting principle of CPU reading of data required time be: if from CPU all packets the formation 0 are read the time that needs that finishes is T, for preventing when CPU once reads, have packet to be omitted, then be provided with from the time that CPU reads all packets be 1.5T～2T.
In order to solve the access conflict problem and to prevent that new data are dropped in Data Receiving, behind the packet that takes out formation 0 first buffer zone of head, revise the sensing of pointer Psend at once, make it point to the head of formation 0, new data just leave the head of formation 0 in.And after all packets all take out, revise the sensing of pointer Precv, make its point to the head of formation 0, all be that head from buffering sector row begins reading of data to guarantee from CPU at every turn.
As can be seen, there is following shortcoming in the method from above-mentioned implementation:
Because transmission bandwidth is conflicting with the time delay of each packet of transmission, the time delay of promptly transmitting each packet is long more, transmission bandwidth is also just relatively more little, so, in case queue length and read the required time of all packets and determine, also just determine the time delay of transmission bandwidth and each packet of transmission thereupon, avoid omitting for guarantee all to take packet away at every turn, read the required time of all data should long enough at every turn, just meaned increase time delay of transmitting each packet and should increase the time, this is unallowable for the very strong business of real-time.
The data of transmitting between CPU are a lot, and the priority of various data is all different with significance level, and the packet that has allows to be dropped, and in a single day the packet that has is dropped, and will cause system works unusual.In above-mentioned prior art scheme, no matter be common data message or important control message, all packets all are to transmit by the same mode of same passage, can't guarantee the reliability of significant data.
For each formation, writing of data is at random, and reading of data is regularly, and the problem of access conflict is difficult to thoroughly avoid and solve.
Owing to rely on reception pointer and send pointer to come formation is managed, and master-slave cpu all has a cover to safeguard the software code of pointer, increased the complexity of software design.
Summary of the invention
In view of this, the invention provides a kind of many CPU method for communicating, when increasing transmission bandwidth, significantly reduce the time delay of each packet of transmission, reduce the packet loss of system; Simultaneously, thoroughly solve the integrity problem of significant data; And can avoid access conflict fully, prevent the data exception that causes owing to access conflict.
For achieving the above object, technical scheme of the present invention is achieved in that
A kind of many CPU method for communicating, this method may further comprise the steps:
The plug-in memory headroom that can visit mutually that links to each other with CPU is set respectively, data message to be sent is write the memory headroom that links to each other with take over party CPU by transmit leg CPU, register is set gives take over party CPU to produce look-at-me, after take over party CPU receives look-at-me, carry out data message and receive;
Control message to be sent is write the buffer zone of intelligent input-output unit by transmit leg CPU, the look-at-me that produces intelligent input-output unit is given take over party CPU, after take over party CPU receives look-at-me, from the buffer zone of intelligent input-output unit, obtain the control message.
Preferably, describedly plug-in memory headroom step be set further comprise: with plug-in memory headroom that CPU links to each other separately in, respectively set up the buffer zone of a fixed size, as the destination address that receives the other side's data message, and set up the control bit whether this buffer zone of control can write message at each buffer zone;
Preferably, the transmission course of data message further comprises:
Transmit leg CPU judges whether our control bit is to write message status, if just apply for the dynamic space of our buffer zone and deposit data message to be sent, otherwise behind the wait certain hour, this control bit of pressure is set to write message status, applies for the dynamic space of our buffer zone again and deposits data message to be sent;
After transmit leg CPU write the destination address of take over party's buffer zone with the data message in the our buffer zone dynamic space, our control bit was set to forbid writing message status;
After take over party CPU handles the data message of receiving, the control bit of transmit leg is revised as to write message status.
Preferably, a control message is divided into several control frames, its transmission course further comprises:
A, transmit leg CPU obtain the address of idle message frame head pointer according to the buffer zone tail pointer in the intelligent input-output unit, write control frame to be transmitted then in the buffer zone of this pointer indication, and tail pointer points to the next idle message frame of this buffer zone;
B, the value of this buffer count device is added one, transmit leg CPU produces intelligent input-output unit and interrupts, and reports take over party CPU;
C, take over party CPU have no progeny in receiving, and in the register of intelligent input-output unit, obtain the pointer of the control newspaper frame address that transmit leg CPU sends, then from obtaining control message to be transmitted between the buffer empty of this pointed;
D, buffer zone head pointer point to the address at the next message frame place in this buffer zone, got all control frames after, the value of buffer count device subtracts one.
Preferably, transmit leg is from CPU, and the take over party is a host CPU, wherein comprises kernel and micro engine two parts from CPU, and the transmission course of data message further comprises:
After CPU write the destination address of the buffer zone that links to each other with host CPU with the data message to be sent its buffer zone with the direct access control mode, host CPU returned the micro engine of hardware signal notice from CPU;
After being set to forbid writing message status from the micro engine we's of CPU control bit, produce the kernel of interrupt notification from CPU;
Send out interruption from the kernel control doorbell register of CPU and give host CPU;
Host CPU is had no progeny in receiving, reads the data in the our buffer zone, with its encapsulation and send to upper layer software (applications), and is set to write message status from the control bit of CPU.
Preferably, transmit leg is a host CPU, and the take over party is from CPU, and wherein host CPU comprises kernel and micro engine two parts, and the transmission course of data message further comprises:
Host CPU with the data message to be sent in its buffer zone with byte copy mode or direct access control mode write with the buffer zone that links to each other from CPU after, we's control bit is set to forbid writing message status, and the kernel that interrupts giving from CPU is sent out in setting from the doorbell register of CPU;
From the kernel of CPU our internal thread interrupt register is set, makes from the micro engine of CPU and produce interruption, transmit the data message in the our buffer zone;
Be set to write message status from the control bit of the micro engine host CPU of CPU.
Preferably, in the buffer zone of described fixed size, only deposit a data message that comprises header and message.
Preferably, transmit leg is from CPU, and the take over party is a host CPU, wherein comprises kernel and micro engine two parts from CPU, and the transmission course of control message further comprises:
Described step a further comprises: obtain pointing to the address of the idle message frame head pointer that sends buffer zone according to the transmission buffer zone tail pointer the intelligent input-output unit of we from CPU, write control frame to be transmitted to the buffer zone place of this pointer indication then, send the buffer zone tail pointer and point to the next idle message frame that sends buffer zone;
Described step c further comprises: have no progeny during host CPU is received, in the first-in first-out register from the transmission buffer zone of CPU, obtain the address at the data pointer place of the control message sent from CPU, then from obtaining control message to be transmitted between the buffer empty of this pointed.
Preferably, transmit leg is a host CPU, and the take over party is from CPU, and wherein host CPU comprises kernel and micro engine two parts, and the transmission course of control message further comprises:
Described step a further comprises: host CPU reads the first-in first-out register in the send buffer from the intelligent input-output unit of CPU, from this register, obtain the send buffer tail pointer, and obtain from the head pointer address of the idle message frame of CPU send buffer according to this tail pointer, buffer zone place to this pointer indication writes control frame to be transmitted, and the send buffer tail pointer points to the next idle message frame of send buffer;
Described step c further comprises: have no progeny from CPU receives, obtain the address at the data pointer place of the control message that host CPU sends according to our send buffer head pointer place, and obtain control message to be transmitted from the buffer zone of this pointed.
Use the present invention, utilize and interrupt carrying out data transmission, when increasing transmission bandwidth, significantly reduced the time delay of each packet, reduced the packet loss of system; And rely on interruption to solve access conflict, thereby prevented because the data exception that access conflict causes.When common data message of transmission and important control message, adopt different interruptions and transmission channel respectively, data message and control message problem of mutual interference mutually in same passage have been avoided, thoroughly solved the safety issue of significant data, in the efficient of data transmission, aspects such as reliability and transmission bandwidth improve a lot, simultaneously, make full use of the function of chip itself, avoided complicated software design, significantly reduced the workload of software design, maintenance.
Description of drawings
Fig. 1 is the master-slave mode multi-CPU structure figure of prior art;
Fig. 2 is the shared drive formula communication queue of prior art;
Fig. 3 is the system construction drawing of master-slave mode CPU;
Fig. 4 is the data message mode;
Fig. 5 is IXP1200 sends diagram from the control message to MPC750;
Fig. 6 is MPC750 sends diagram from the control message to IXP1200.
Embodiment
For making purpose of the present invention, technical scheme and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, the present invention is described in further details.
In the present embodiment, be example with MPC750 (general processor of the PPC of motorola inc series) and IXP1200 (network processing unit of the Strong ARM series of Intel Company), describe technical scheme of the present invention in detail at the master-slave mode multi-CPU structure.
Figure 3 shows that the system construction drawing of master-slave mode CPU.MPC750 has powerful operation capacity, uses as host CPU at this; IXP1200 has powerful data forwarding ability, it comprises kernel (CORE) and micro engine (uE) two parts, CORE is the general processor of a Reduced Instruction Set Computer (RISC:Reduced Instruction System Computer) structure, the effect of uE is to carry out the processing of data and forwarding, these two parts are integrated in the chip jointly, use from CPU in this conduct.Two plug-in internal memories (SDRAM) are set link to each other with IXP1200 with MPC750 respectively, and MPC750 and IXP1200 can visit the other side's SDRAM space mutually.
The flow of data message is generally bigger, its uE that mainly is meant IXP1200 reports MPC750 with the data message that self can't handle and handles the uE that data message after will handling with MPC750 is handed down to IXP1200, when carrying out the transmission of data message, be to finish, and notify the other side to receive by interrupt mode by the plug-in separately SDRAM space of master-slave cpu; And the control message is meant that MPC750 is handed down to the various control commands of IXP1200 and the status information that IXP1200 reports MPC750, when the transmission of controlling message, be to finish by I2O (the Intelligent Inputand Output) unit that IXP1200 carries, and the data transmission of control message also adopts interrupt mode to notify the other side to receive, but the employed interruption of this interruption and data message is not same interruption.This just makes data message adopt different transmission channels respectively with the control message, thereby has avoided data message to adopt the same passage problem of mutual interference mutually with the control message.Also there is the I2O unit MPC750 inside, can be used as the transmission channel of control message, and in the present embodiment, the I2O unit of IXP1200 is only used in the transmission of control message.
Figure 4 shows that the data message mode.The implementation procedure of data message transmission mechanism is as follows:
1, respectively set up the fixedly buffer zone of a 2KB in the SDRAM of IXP1200 and MPC750, transmit the destination address of data as twocouese the other side, the source address of so each data transmission is dynamically application, and destination address is fixed;
2, for simplified design, only deposit a data message in the buffer zone of 2KB, the header that it had both comprised data message also comprises the concrete data content of data message, only transmits a data message at every turn, wait the other side to receive this message after, transmission is next again;
3, the data message length of transmission is between 40～1500 bytes, and based on 60 byte lengths, because the direct access controller (DMA:Direct Memory Access) of MPC750 is when handling bigger data message or DMA chained list, its performance is apparent in view, and when handling less data message, its performance can not well embody, so for simplified design, the scheme that present embodiment adopts is: MPC750 issues the data message of IXP1200 and handles with byte copy (bcopy) mode, and IXP1200 issues the data message of MPC750 and handles with dma mode;
4, refreshed by next data message in order to prevent that data message in the buffer zone from just having little time to take away, increase control bit in addition and represent the current data message of which CPU control, buffer zone side at 2KB is provided with 8 byte control bits, during initialization the control bit in the buffer zone all is set to 1.The control bit of finding we before sending is could send in 1 o'clock, otherwise wait if wait for that control bit still is 0 for a long time, just is made as 1 to this control bit pressure.For example: will send a data message to MPC750 as IXP1200, find before sending that the control bit among the our SDRAM is 1, write with regard to the data message that will send in the SDRAM of MPC750 with dma mode, uE is we's control position 0 subsequently, when MPC750 after in the interrupt service routine this data message being read out from the sdram buffer of MPC750, again the control bit of IXP1200 is revised as 1, when IXP1200 finds that we's control bit is 1, just can send next data message like this.MPC750 is identical to the principle that IXP1200 sends datagram.
5, utilize interior doorbell (DoorBell) register of pci configuration space of each equipment, realize the communication of interrupt mode between the master-slave cpu on the pci bus.If IXP1200 is provided with this register as target (Target) equipment of pci bus, just produce an interruption and give MPC750, if MPC750 is provided with this register as main frame (HOST) processor of pci bus, just produces an interruption and give IXP1200.
Specify the transmission course of data message between the master-slave cpu below.
IXP1200 sends datagram to MPC750:
1, IXP1200 and MPC750 are written as 1 to we's control bit separately during initialization, when IXP1200 has data message to send, read the control bit of our buffer zone earlier, if control bit is 1 just can continue to carry out the operation that sends datagram, otherwise just wait for, until the time of waiting for greater than 20 times that send a data message required time, just force this control bit to be set to 1;
If 2 control bits are 1, uE applies for that the dynamic space among the our SDRAM deposits data message to be sent;
3, by the PCI_DMA instruction of uE, uE writes this data message to be sent in the SDRAM of MPC750 with dma mode;
4, after MPC750 receives these data, return a hardware signal notice uE, uE is written as 0 to we's control bit earlier this moment, produce a look-at-me notice CORE then, CORE carries out the respective interrupt service routine again, the Doorbell register that we only need be set in the disconnected hereinto service routine is sent out external interrupt to MPC750, and CORE withdraws from this interrupt service routine after executing this operation;
5, MPC750 receives in this and has no progeny, and reads the data message that IXP1200 sends from buffer zone, and gives upper layer software (applications) after it encapsulation finished and handle, and the control bit of IXP1200 is written as 1.
MPC750 sends datagram to IXP1200:
1, IXP1200 and MPC750 are written as 1 to we's control bit separately during initialization, when MPC750 has data message to send, read the control bit of our buffer zone earlier, if control bit is 1 just can continue to carry out the operation that sends datagram, otherwise just wait for, until the time of waiting for greater than 20 times that send a data message required time, just force this control bit to be set to 1;
If 2 control bits are 1, the dynamic space among the MPC750 first to file we SDRAM is deposited data message to be sent, and the mode with bcopy is written to data message in the SDRAM of IXP1200 again, writes after finishing we's control bit is written as 0;
3, MPC750 is provided with the Doorbell register of IXP1200 to produce the CORE of respective interrupt signals to IXP1200, CORE carries out the respective interrupt service routine again, in the disconnected hereinto service routine, internal thread on CORE interruption (INTER_THD_SIG) register among the IXP1200 only need be set, make the data message that the uE generation is interrupted and forwarding MPC750 sends, CORE withdraws from this service routine after executing this operation;
The control bit of having no progeny during 4, uE receives MPC750 changes 1 into.
The implementation procedure of control message transmissions mechanism:
With respect to data message, the flow of control message is less, but the transmission reliability that it requires is very high, and data message allows packet loss when flow is excessive, but controlling message will avoid this situation as far as possible.In order to satisfy the demand of this high reliability, a control message is divided into several control frames, and adopt the I2O unit to realize controlling the transmission of message, I2O provides a standard, reliable message passing mechanism for hanging over to communicate between the equipment on the pci bus, and it has comprised four FIFO buffers (FIFOs) that are arranged in local SDRAM: promptly
Inbound free list FIFO: the idle queues in the send buffer;
Inbound post list FIFO: occupied formation in the send buffer;
Outbound free list FIFO: send the idle queues in the buffer zone;
Outbound post list FIFO: send occupied formation in the buffer zone.
MPC750 and IXP1200 respectively have an I2O unit, can use I2O unit realization communication between the two separately, in order better to support the structure of many CPU, only use the send buffer of IXP1200 in the present embodiment and send buffer zone, the I2O unit that promptly only uses IXP1200 to provide does not use this unit of MPC750.
IXP1200 sends the control message to MPC750:
Convenience for program design, use OUT_MFA_HEAD_PTR and out_mfa_tail_ptr to represent to send the head pointer and the tail pointer of occupied formation in the buffer zone respectively, because the space of this formation and the shared one section continuous internal memory of idle queues, can know also that so send the head pointer and the tail pointer of the idle queues of buffer zone the head pointer and the tail pointer that promptly send occupied formation in the buffer zone are exactly tail pointer and the head pointer that sends the idle queues of buffer zone.Simultaneously, with sending buffer count device (OUT_BOUND_CNT) record sends needs the data message that sends in the buffer zone number.
Figure 5 shows that IXP1200 sends the diagram of control message to MPC750.At first IXP1200 obtains pointing to the address of the head pointer of the idle message frame that sends buffer zone according to out_mfa_tail_ptr, write control frame to be sent successively to the internal memory place of this pointer indication then, whenever write a frame, out_mfa_tail_ptr just moves down a frame, after all control frames have been write, out_mfa_tail_ptr points to the next idle message frame that sends buffer zone, uses so that send the control message next time, and the value of OUT BOUND CNT adds one.As long as the value of OUT BOUND CNT is not equal to 0, IXP1200 will produce PCI and interrupt, and reports MPC750.
MPC750 has no progeny in receiving, from the transmission buffer zone first-in first-out register (OUTBOUND_FIFO) of IXP1200, obtain the pointer of the control frame address that IXP1200 sends, obtain control frame to be transmitted from the memory headroom of this pointer indication address then, whenever get a frame, OUT_MFA_HEAD_PTR just points to the address at the next control frame place that sends buffer zone, after treating that all control frames have been got, the value of OUT_BOUND_CNT subtracts one.
MPC750 sends the control message to IXP1200:
Convenience for program design, use IN_MFA_TAIL_PTR and in_mfa_head_ptr to represent the tail pointer and the head pointer of occupied formation in the send buffer respectively, because the space of this formation and the shared one section continuous internal memory of idle queues, so the head pointer of the idle queues of send buffer and tail pointer can know that also promptly the tail pointer of occupied formation and head pointer are exactly the head pointer and the tail pointer of the idle queues of send buffer in the send buffer.Simultaneously, with the number of the data message that has received in send buffer counter (IN_BOUND_CNT) the recorder buffer zone.
Figure 6 shows that MPC750 sends the diagram of control message to IXP1200.When MPC750 sends the control message to IXP1200, MPC750 reads the send buffer first-in first-out register (INBOUND_FIFO) of IXP1200 earlier, obtain the address of head pointer of the idle message frame of IXP1200 send buffer according to IN_MFA_TAIL_PTR, write control frame to be sent successively to the internal memory place of this pointer indication then, whenever write a frame, IN_MFA_TAIL_PTR just moves down a frame, after all control frames have been write, the next idle message frame of IN_MFA_TAIL_PTR pointed send buffer, use so that send the control message next time, the value of IN_BOUND_CNT adds one.As long as the value of IN_BOUND_CNT is not equal to 0, MPC750 will produce I2O and interrupt reporting IXP1200.
IXP1200 receives among the I2O and has no progeny, obtain the pointer of the control frame address that MPC750 sends at the in_mfa_head_ptr place, obtain control frame to be transmitted from the internal memory of this pointer indication address again, whenever get a frame, in_mfa_head_ptr just points to the next control frame address of send buffer, after treating that all control frames have been got, the value of IN_BOUND_CNT subtracts one.
In the present embodiment, when MPC750 and IXP1200 carry out data transmission, MPC750 adopts the bcopy mode that data are sent to IXP1200's, if data volume is very big, MPC750 also can adopt the mode of DMA that data are sent to IXP1200, data rate can be faster, and the occupancy of CPU also can reduce.
Above embodiment has only introduced host CPU and the signal intelligence from CPU, and this communication means is equally applicable to host CPU and two or more situations of communicating by letter simultaneously from CPU.Simultaneously, for other series the CPU of similar structures is arranged, this communication means is suitable equally.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1, a kind of many CPU method for communicating is characterized in that, this method may further comprise the steps:
The plug-in memory headroom that can visit mutually that links to each other with CPU is set respectively, data message to be sent is write the memory headroom that links to each other with take over party CPU by transmit leg CPU, register is set gives take over party CPU to produce look-at-me, after take over party CPU receives look-at-me, carry out data message and receive;
Control message to be sent is write the buffer zone of intelligent input-output unit by transmit leg CPU, the look-at-me that produces intelligent input-output unit is given take over party CPU, after take over party CPU receives look-at-me, from the buffer zone of intelligent input-output unit, obtain the control message.
2, many CPU method for communicating according to claim 1 is characterized in that, describedly plug-in memory headroom step is set further comprises:
With plug-in memory headroom that CPU links to each other separately in, respectively set up the buffer zone of a fixed size, as the destination address that receives the other side's data message, and set up the control bit whether this buffer zone of control can write message at each buffer zone;
3, many CPU method for communicating according to claim 2 is characterized in that, the transmission course of data message further comprises:
Transmit leg CPU judges whether our control bit is to write message status, if just apply for the dynamic space of our buffer zone and deposit data message to be sent, otherwise behind the wait certain hour, this control bit of pressure is set to write message status, applies for the dynamic space of our buffer zone again and deposits data message to be sent;
After transmit leg CPU write the destination address of take over party's buffer zone with the data message in the our buffer zone dynamic space, our control bit was set to forbid writing message status;
After take over party CPU handles the data message of receiving, the control bit of transmit leg is revised as to write message status.
4, many CPU method for communicating according to claim 1 is characterized in that, a control message is divided into several control frames, and its transmission course further comprises:
A, transmit leg CPU obtain the address of idle message frame head pointer according to the buffer zone tail pointer in the intelligent input-output unit, write control frame to be transmitted then in the buffer zone of this pointer indication, and tail pointer points to the next idle message frame of this buffer zone;
B, the value of this buffer count device is added one, transmit leg CPU produces intelligent input-output unit and interrupts, and reports take over party CPU;
C, take over party CPU have no progeny in receiving, and in the register of intelligent input-output unit, obtain the pointer of the control newspaper frame address that transmit leg CPU sends, then from obtaining control message to be transmitted between the buffer empty of this pointed;
D, buffer zone head pointer point to the address at the next message frame place in this buffer zone, got all control frames after, the value of buffer count device subtracts one.
5, many CPU method for communicating according to claim 3 is characterized in that, transmit leg is from CPU, and the take over party is a host CPU, wherein comprises kernel and micro engine two parts from CPU, and the transmission course of data message further comprises:
After CPU write the destination address of the buffer zone that links to each other with host CPU with the data message to be sent its buffer zone with the direct access control mode, host CPU returned the micro engine of hardware signal notice from CPU;
After being set to forbid writing message status from the micro engine we's of CPU control bit, produce the kernel of interrupt notification from CPU;
Send out interruption from the kernel control doorbell register of CPU and give host CPU;
Host CPU is had no progeny in receiving, reads the data in the our buffer zone, with its encapsulation and send to upper layer software (applications), and is set to write message status from the control bit of CPU.
6, many CPU method for communicating according to claim 3 is characterized in that transmit leg is a host CPU, and the take over party is from CPU, and wherein host CPU comprises kernel and micro engine two parts, and the transmission course of data message further comprises:
Host CPU with the data message to be sent in its buffer zone with byte copy mode or direct access control mode write with the buffer zone that links to each other from CPU after, we's control bit is set to forbid writing message status, and the kernel that interrupts giving from CPU is sent out in setting from the doorbell register of CPU;
From the kernel of CPU our internal thread interrupt register is set, makes from the micro engine of CPU and produce interruption, transmit the data message in the our buffer zone;
Be set to write message status from the control bit of the micro engine host CPU of CPU.
7, according to claim 2 or 5 or 6 described many CPU method for communicating, it is characterized in that: in the buffer zone of described fixed size, only deposit a data message that comprises header and message.
8, many CPU method for communicating according to claim 4 is characterized in that transmit leg is from CPU, and the take over party is a host CPU, wherein comprises kernel and micro engine two parts from CPU, and the transmission course of control message further comprises:
Described step a further comprises: obtain pointing to the address of the idle message frame head pointer that sends buffer zone according to the transmission buffer zone tail pointer the intelligent input-output unit of we from CPU, write control frame to be transmitted to the buffer zone place of this pointer indication then, send the buffer zone tail pointer and point to the next idle message frame that sends buffer zone;
Described step c further comprises: have no progeny during host CPU is received, in the first-in first-out register from the transmission buffer zone of CPU, obtain the address at the data pointer place of the control message sent from CPU, then from obtaining control message to be transmitted between the buffer empty of this pointed.
9, many CPU method for communicating according to claim 4 is characterized in that transmit leg is a host CPU, and the take over party is from CPU, and wherein host CPU comprises kernel and micro engine two parts, and the transmission course of control message further comprises:
Described step a further comprises: host CPU reads the first-in first-out register in the send buffer from the intelligent input-output unit of CPU, from this register, obtain the send buffer tail pointer, and obtain from the head pointer address of the idle message frame of CPU send buffer according to this tail pointer, buffer zone place to this pointer indication writes control frame to be transmitted, and the send buffer tail pointer points to the next idle message frame of send buffer;
Described step c further comprises: have no progeny from CPU receives, obtain the address at the data pointer place of the control message that host CPU sends according to our send buffer head pointer place, and obtain control message to be transmitted from the buffer zone of this pointed.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021589100A CN1295633C (en) | 2002-12-26 | 2002-12-26 | Method for multiple CPU communication |
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| CN100458696C (en) * | 2006-05-08 | 2009-02-04 | 华为技术有限公司 | System and method for realizing multiple CPU loading |
| CN100538690C (en) * | 2006-04-10 | 2009-09-09 | 中国科学院研究生院 | The method that message is transmitted between a kind of multi-CPU system and the CPU |
| CN1964286B (en) * | 2006-12-13 | 2012-02-29 | 杭州华三通信技术有限公司 | A master control device with double CPU |
| CN102624734A (en) * | 2012-03-15 | 2012-08-01 | 汉柏科技有限公司 | NAT (Network Address Translation) equipment discovery processing method in IKE (Internet Key Exchange) message negotiation process |
| CN102866971A (en) * | 2012-08-28 | 2013-01-09 | 华为技术有限公司 | Data transmission device, system and method |
| CN101620551B (en) * | 2009-05-07 | 2013-03-06 | 曙光信息产业(北京)有限公司 | Network card interrupt control method for a plurality of virtual machines |
| CN103597416A (en) * | 2011-06-09 | 2014-02-19 | 三菱电机株式会社 | Programmable controller system |
| CN103853692A (en) * | 2014-03-12 | 2014-06-11 | 四川九洲空管科技有限责任公司 | Multiprocessor data communication method based on interrupt judgment mechanism |
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| CN107634916A (en) * | 2016-07-19 | 2018-01-26 | 大唐移动通信设备有限公司 | A kind of data communications method and device |
| CN109299033A (en) * | 2017-07-25 | 2019-02-01 | 中车株洲电力机车研究所有限公司 | A kind of processor interface device and processor data processing method |
| CN110046115A (en) * | 2019-04-03 | 2019-07-23 | 山东超越数控电子股份有限公司 | A kind of transmission terminal based on big data quantity high-speed asynchronous transfer receives terminal, method and system |
| CN111008164A (en) * | 2019-12-04 | 2020-04-14 | 天津七一二通信广播股份有限公司 | Inter-node multi-cache type communication method based on storage mapping type bus |
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| SE515265C2 (en) * | 1994-10-17 | 2001-07-09 | Ericsson Telefon Ab L M | Systems and methods for processing signal data and communication systems comprising a signal data processing system |
| JP3365705B2 (en) * | 1995-05-24 | 2003-01-14 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Distributed data processing system |
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| CN100538690C (en) * | 2006-04-10 | 2009-09-09 | 中国科学院研究生院 | The method that message is transmitted between a kind of multi-CPU system and the CPU |
| CN100458696C (en) * | 2006-05-08 | 2009-02-04 | 华为技术有限公司 | System and method for realizing multiple CPU loading |
| CN1964286B (en) * | 2006-12-13 | 2012-02-29 | 杭州华三通信技术有限公司 | A master control device with double CPU |
| CN101620551B (en) * | 2009-05-07 | 2013-03-06 | 曙光信息产业(北京)有限公司 | Network card interrupt control method for a plurality of virtual machines |
| CN103597416A (en) * | 2011-06-09 | 2014-02-19 | 三菱电机株式会社 | Programmable controller system |
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| CN109299033A (en) * | 2017-07-25 | 2019-02-01 | 中车株洲电力机车研究所有限公司 | A kind of processor interface device and processor data processing method |
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| CN110046115B (en) * | 2019-04-03 | 2023-09-01 | 超越科技股份有限公司 | Transmitting terminal, receiving terminal, method and system based on high-data-rate high-speed asynchronous transmission |
| CN111008164A (en) * | 2019-12-04 | 2020-04-14 | 天津七一二通信广播股份有限公司 | Inter-node multi-cache type communication method based on storage mapping type bus |
| CN113590520A (en) * | 2021-06-15 | 2021-11-02 | 珠海一微半导体股份有限公司 | Control method for automatically writing data into SPI system and SPI system |
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| CN116455849A (en) * | 2023-06-15 | 2023-07-18 | 中国人民解放军国防科技大学 | Concurrent communication method, device, equipment and medium for many-core processor |
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