JP2006338194A - Data processing system, data processing program, and data processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain speed-up of data processing by reducing the time necessary for cache flush processing. <P>SOLUTION: A check part determines whether garbage collection by a memory management part is performed or not (S9), the check part makes a cache flush part perform cache flush processing when the garbage collection is performed (YES in S10, S4), and the check part controls the cache flush part not to perform the cache flush processing when the garbage collection is not performed (NO in S10, S5). According to this, the frequency of cache flush processing is reduced. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a data processing technique that causes an ASIC to execute processing of data written in a storage area in a memory. As an example of the application field, there is control of a circuit for forming an image by interpreting a drawing command in a printer or a multi-function peripheral, performing image processing on an image, and the like.

  In a printer, a multifunction peripheral (an image forming apparatus having a complex function such as a printer function, a copy function, and a scanner function), print data is received from a host computer, and an image is formed and printed. In this process, the size of the print data received from the host computer is variable, and the image data to be generated varies depending on the print mode. Therefore, when the memory is used for generating the image data, Memory management control is required to allocate memory areas, release areas that are no longer needed, and rearrange memory areas (garbage collection described later).

  When relocating the above memory, when using a low-function CPU that does not have a segmented or paging memory management function (MMU), it is necessary to secure the requested memory area in a continuous state. When free memory areas of sizes are scattered, a process called garbage collection is performed in which allocated memory areas are moved to secure continuous memory areas. The following patent document 1 is a prior art document regarding garbage collection, and the following patent document 2 is a prior art document regarding a memory management method in a printer.

  In addition, when the cache is used in the write back mode, the CPU always generates data in a memory such as a DRAM through the cache. When an ASIC (Application Specific Integrated Circuit) executes processing of data generated in the memory, the data is read from the memory area indicated by the previously acquired address information, and the ASIC Is processed. However, if the garbage collection has already been executed when the ASIC reads data from the memory, the data to be processed cannot be read from the memory. Therefore, by executing a cache flush, the processing target data is accurately read out.

For example, in printer image processing, various printer description languages (PDL) received from a host computer are refined into drawing commands with a low level of abstraction and then processed by the ASIC. This drawing command is generated for each page. The drawing process cannot be started in the middle of the page even if the system adopts the band method. After the drawing command for one page is generated, the cycle of drawing in band units, compressing, and decompressing during printing processing is repeated. In this process, an area to hold compressed data is secured after drawing. After compression, the original drawing area is no longer needed and is released and reused. In other words, memory is frequently secured and released in band units, and when the memory area for holding the compressed data is insufficient, rearrangement by garbage collection is performed to secure the necessary area. When garbage collection is executed, the position of the original data such as drawing commands and images that have been generated in the memory may move, so the cache flush process is always performed in band units. .
JP 2001-184254 A JP 2002-351739 A

  However, if the cache flush process is always executed as described above, the data process takes a long time, and the data process cannot be performed at a high speed. In recent years, since a large-scale secondary cache is mounted on a CPU and the time required for cache flush processing has increased, an improvement for high-speed data processing is desired.

  The present invention has been made to solve the above-described problems, and has an object to reduce the time required for cache flush processing and realize high-speed data processing.

The invention according to claim 1 of the present invention is a data processing system for causing an ASIC to execute processing of data written in a storage area in a memory,
Cache flush means for performing cache flush processing for writing data stored in a cache to a storage area in the memory;
Address information notifying means for notifying the ASIC of address information of the storage area in which data is written by the cache flush process;
When the data written in the storage area indicated by the address information obtained from the address information notification means is processed by the ASIC, and the processed data is written to the memory, the memory is stored as necessary. Relocation processing means for performing relocation processing of the area and securing a writable area of the data to be written;
Relocation presence / absence determining means for determining whether or not relocation processing has been performed by the relocation processing means;
When the rearrangement determination unit determines that the rearrangement process has been performed, the cache flush unit performs the cache flush process, and when the rearrangement process has not been performed, the rearrangement presence determination is performed. And a prohibiting unit that prohibits the cache flush process by the cache flush unit.

  In the present invention, the relocation presence / absence determination unit determines whether or not the relocation processing by the relocation processing unit has been performed, and according to the determination result, whether the prohibition unit causes the cache flush unit to execute the cache flush process. By controlling whether or not, the number of cache flush processes is reduced.

  The cache flush process is performed so that the ASIC can accurately read the data to be processed even when the data storage area rearrangement process is performed. Whether or not the data storage area is rearranged is determined by the memory area required for data retention and the continuous maximum free capacity in the memory at that time. In other words, relocation processing is only performed when there is insufficient continuous free memory capacity when attempting to secure a memory area for data writing, and memory relocation is always performed when data is written to memory. It is not done. Since cache flush processing only needs to be performed when relocation processing is performed, the performance of data processing is reduced by prohibiting cache flush processing when relocation processing is not performed and reducing the number of cache flush processing. To improve.

The invention according to claim 2 is the data processing system according to claim 1, wherein the storage area in the memory in which data to be processed by the ASIC is written is the relocation processing means. Determining means for determining whether or not the target of the relocation processing by
Even if the prohibition unit determines that the rearrangement process has been performed by the rearrangement presence determination unit, the storage area in which the data to be processed by the ASIC is written When it is determined by the determination means that it is not a target for the rearrangement process, the cache flush process by the cache flush means is prohibited.

  In this configuration, the determination unit determines whether or not the data storage area in which the data to be processed by the ASIC is written is the target of the rearrangement process by the rearrangement processing unit. Thus, the prohibiting means controls whether or not the cache flushing means executes the cache flush process, thereby further reducing the number of cache flush processes.

  Even if the memory is rearranged due to insufficient continuous free space when writing data to the memory, if the memory area that is the target of the rearrangement process is not the area that the ASIC refers to, cache flush is performed. Since there is no need, unnecessary cache flush processing is further reduced to further improve data processing performance.

  Further, the invention according to claim 3 is the data processing system according to claim 1 or 2, wherein the cache flush unit is provided for each task based on each identifier indicating each of a plurality of tasks. This is to control whether or not the cache flush process is prohibited.

  In this configuration, by using respective identifiers for a plurality of tasks, it is controlled whether or not the cache flush processing is prohibited for each data processing for each task. As a result, it is possible to control whether or not the cache flush processing is prohibited for a plurality of tasks.

The invention according to claim 4 is a data processing program for causing an ASIC to execute processing of data written in a storage area in a memory.
Cache flush means for performing cache flush processing for writing data stored in a cache to a storage area in the memory;
Address information notifying means for notifying the ASIC of address information of the storage area in which data is written by the cache flush process;
When the data written in the storage area indicated by the address information obtained from the address information notification means is processed by the ASIC, and the processed data is written to the memory, the memory is stored as necessary. Relocation processing means for performing relocation processing of the area and securing a writable area of the data to be written;
Relocation presence / absence determining means for determining whether or not relocation processing has been performed by the relocation processing means;
When the rearrangement determination unit determines that the rearrangement process has been performed, the cache flush unit performs the cache flush process, and when the rearrangement process has not been performed, the rearrangement presence determination is performed. If determined by the means, the computer is operated so as to include prohibiting means for prohibiting the cache flush processing by the cache flush means.

The invention according to claim 5 is a data processing method for causing an ASIC to execute processing of data written in a storage area in a memory,
A step of performing a cache flush process for writing data stored in a cache to a storage area in the memory;
A process of notifying the ASIC of address information of the storage area in which data is written by the cache flush process;
When the data written in the storage area indicated by the notified address information is processed by the ASIC and the processed data is written into the memory, the storage area of the memory is rearranged as necessary. Performing a process and securing a writable area for the data to be written;
A step of determining whether or not the rearrangement process has been performed;
When it is determined that the relocation processing has been performed, the cache flush unit is caused to perform the cache flush processing, and when it is determined that the relocation processing has not been performed, the cache flush processing is prohibited. It consists of a process.

  According to the first, fourth, and fifth aspects of the present invention, the cache flush process is prohibited when the relocation process is not performed and the number of cache flush processes is reduced. Time required can be reduced, and high-speed data processing can be realized.

  According to the second aspect of the present invention, even if the memory is rearranged due to insufficient continuous free space when data is written to the memory, the moved memory area subject to the rearrangement process becomes the ASIC. Since the cache flush process is prohibited when the area is not referred to, unnecessary cache flush process is further reduced, and the data processing performance can be further improved.

  According to the third aspect of the present invention, it is possible to control whether or not the cache flush processing is prohibited for a plurality of tasks.

  An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a schematic configuration of a main part of a data processing system according to the present invention. Hereinafter, a case where the data processing system according to the present invention is applied to an image forming apparatus will be described (the present invention is not limited to application only to an image forming apparatus). The image forming apparatus 1 is a printer or a multi-function device having at least a printer function. The image forming apparatus 1 includes a control unit 10, an I / F (interface) unit 11, an ASIC 12, an image forming unit 13, and a memory in order to perform image data processing (printing processing and other processing) necessary for the printer function. 15.

  The control unit 10 includes a CPU and the like, and controls operation of each unit for image data processing. The control unit 10 also functions as a PDL analysis unit 100, a cache flash unit 101, a memory management unit 102, and a check unit 103 based on a data processing program stored in a storage device (not shown). Further, the control unit 10 includes a cache 104. PDL (Page Description Language) data (drawing command) sent from the host computer 2 is written into the memory 15 via the I / F unit 11. The PDL analysis unit 100 reads the PDL data written in the memory 15 and converts it into a display list (DL), which is an intermediate language for each band. This display list is held in the cache 104. The cache flush unit (cache flush unit) 101 writes the display list written in the cache 104 back to a predetermined area in the memory 15 as necessary (cache flush process).

  The memory management unit (address information notification means, relocation processing means) 102 is a storage area in the memory 15 that is assigned to various data (DL buffer area, compressed data buffer area, band buffer area, etc.) ). The compression / decompression unit 122 of the ASIC 12 to be described later, in accordance with memory map information (address information) given from the memory management unit 102, the memory space on the memory 15 made of DRAM (Dynamic Random Access Memory) or the like is divided into the DL buffer area, Used as a compressed data buffer area and a band buffer area. Further, the memory management unit 102 does not have enough free space for writing the compressed data when the compressed data compressed by the compression / decompression unit 122 cannot be written to a predetermined area in the memory 15 that is set in advance. If not, garbage collection (relocation processing) is performed to secure an area capable of holding the compressed data in the storage area in the memory 15. When garbage collection is performed, the memory management unit 102 sets a flag indicating that garbage collection has been performed.

  The check unit (relocation presence / absence determination unit, prohibition unit) 103 determines whether or not the memory management unit 102 has set the flag (a flag indicating that garbage collection has been performed), and the flag is set Is determined to require cache flush processing, and if the flag is not set, it is determined that cache flush processing is unnecessary.

  The cache flush unit 101 executes a cache flush process for writing data stored in the cache 104 to the memory 15. The cache flush unit 101 controls whether to perform the cache flush process based on the information received from the check unit 103 indicating that the cache flush process is necessary.

  An ASIC (Application Specific Integrated Circuit) 12 includes a bitmap expansion unit 121 and a compression / decompression unit 122. The bitmap development unit 121 develops a display list as a bitmap. The compression / decompression unit 122 (1) compresses the bitmap data expanded for each band by, for example, JBIG (Joint Bi-level Image experts Group), and (2) decompresses the compressed image data. Process. The image data compressed by the compression / decompression unit 122 is written in a compressed data buffer area in the memory 15, and the image data expanded by the compression / decompression unit 122 is written in a band buffer area in the memory 15.

  The image forming unit 13 performs image formation by sequentially receiving the image data expanded by the compression / decompression unit 122 for each band.

  The flow of image data processing by the image forming apparatus 1 will be briefly described. When the PDL data received from the host computer 2 via the I / F unit 11 is written in the memory 15, the PDL analysis unit 100 reads the PDL data from the memory 15, converts it into a display list (DL), and caches it. 104. The cache flash unit 101 appropriately writes the display list held in the cache 104 into a predetermined area (reference area of the ASIC 12) of the memory 15 (cache flush process). The bitmap expansion unit 121 of the ASIC 12 expands the display list into a bitmap in units of bands, and the compression / decompression unit 122 compresses the bitmap data for each band with JBIG, and compresses the compressed data into a compressed data buffer. To store. The compressed data stored in the compressed data buffer is decompressed by the compression / expansion unit 122 at an appropriate timing and written to the band buffer, and the decompressed data is output to the image forming unit 13.

  The cache flush control during the print data processing will be described. FIG. 2 is a flowchart showing the cache flush control. When PDL data is received from the host computer 2 via the I / F unit 11, the PDL data is held in the memory 15 (S1). The memory management unit 102 uses, as an argument, the ID of the task that performs the print data processing as an argument (a memory to be used to determine whether or not garbage collection to be described later has been performed). 15), memory control information such as memory map information indicating the area) is acquired (S2). In this way, by using the task ID as an argument and performing the following control on the area in the memory 15 corresponding to each task, the cache flush control is individually performed for each print data processing based on a plurality of tasks. Making it possible to do.

  Subsequently, the PDL analysis unit 10 reads and analyzes the PDL data from the memory 15, and generates a display list in the cache 104 (S3). The cache flush unit 101 executes a cache flush process (writing the display list generated in the cache 104 to a predetermined area of the memory 15) (S4). The control unit 10 activates the ASIC 12 (S5), and the memory management unit 102 sends memory map information indicating the reference area of the ASIC 12 in the memory 15 to the ASIC 12. Thereby, after the cache flush process, the bitmap developing unit 121 of the ASIC 12 reads the display list written in the predetermined area of the memory 15 and develops the bitmap. The compression / decompression unit 122 compresses the decompressed bitmap data using, for example, JBIG (S6).

  Here, if the continuous free capacity of the compressed data buffer in the memory 15 is not sufficient for the amount of compressed data generated by the compression / decompression unit 122, the memory management unit 102 performs garbage collection. When garbage collection is performed, the memory management unit 102 sets a flag indicating that garbage collection has been performed. That is, it is determined whether or not garbage collection has occurred in a specific area used for print data processing based on this task in the memory 15. If garbage collection has occurred in the specific area, garbage collection has occurred. A flag indicating that the operation has been performed is set. In addition, the garbage collection, determination as to whether or not to set a flag, and processing are performed each time compressed data is generated by the compression / decompression unit 122. This completes image data processing for one band.

  Here, when the processing for all the bands constituting the display list written in the memory 15 by the cache flash unit 101 is completed (YES in S7), the memory management unit 102 determines whether garbage collection has occurred. The memory control information indicating the specific area or the like for each task ID to be determined is reset (S8), and the process ends.

  In addition, in the display list written in the memory 15, when a band to be processed remains (NO in S7), the check unit 103 indicates that the memory management unit 102 has been garbage collected. It is detected whether the flag is set (S9), and it is determined whether or not the cache flush unit 101 is to execute the cache flush again. When the flag is set (when garbage collection is performed), the check unit 103 causes the cache flush unit 101 to perform a cache flush (YES in S10, S4). That is, the data to be read by the compression / decompression unit 122 of the ASIC 12 is written again in a predetermined area of the memory 15. Thereby, even if the data arrangement is changed in the specific area in the memory 15 due to the garbage collection, the data read out from the memory 15 by the compression / decompression unit 122 becomes accurate processing target data.

  If the flag is not raised (NO in S10), the check unit 103 prohibits the cache flush process by the cache flush unit 101 and does not perform the cache flush process (NO in S10, S5). Processing by the decompression unit 122 is performed (S5). In this case, since garbage collection is not performed, the storage area of the memory 15 in which the data to be processed by the compression / decompression unit 122 has not been changed, so that the processing target can be processed without performing cache flush processing. The compression / decompression unit 122 can accurately read the data.

  The present invention is not limited to the configuration of the above embodiment, and various modifications can be made. For example, in the above embodiment, control is performed so that cache flush processing is performed if garbage collection is performed, and cache flush processing is not performed if garbage collection is not performed. However, garbage collection is performed. Even in the case where the area where the display list to be processed by the compression / decompression unit 122 is not moved by garbage collection, the cache flush process may not be performed. Good. That is, although the garbage collection is performed in the specific area in the memory 15 used for the print data processing based on the task being executed, the data written in the area affected by the garbage collection is compressed / decompressed. If 122 does not refer to it, the cache flush process is not performed.

  A schematic configuration of the main part of the data processing system in this case is shown in FIG. The control unit 10 changes the area actually referred to by the compression / decompression unit 122 in the memory 15 in the print data processing based on the task being executed by the garbage collection. A determination unit (determination means) 106 is provided for determining whether or not it has been performed. In the determination unit 106, the control unit 10 functions according to a program. The determination unit 106 receives, from the memory management unit 102, memory map information indicating the area after the change by the rearrangement when the storage area in the memory 15 is rearranged by the garbage collection, and the compression / decompression unit 122 from before the garbage collection is executed. Is acquired from the memory management unit 102, and it is determined whether the storage area referenced by the compression / decompression unit 122 has been moved by garbage collection.

  A control flow in this case is shown in FIG. In FIG. 4, the same processes as those in the control shown in FIG. That is, when the check unit 103 checks whether or not the flag indicating that garbage collection has been performed is set in the memory management unit 102 (S9), if the flag is set (YES in S10), The determination unit 106 determines whether the reference area of the compression / decompression unit 122 has been moved by garbage collection (S11). If the reference area of the compression / decompression unit 122 has not been moved by garbage collection (NO in S11) The check unit 103 prohibits the cache flush process by the cache flush unit 101 (NO in S11, S5), and the compression / decompression unit 122 reads the display list from the reference area as before and performs the process. (S5). When the reference area of the compression / decompression unit 122 is moved by garbage collection (YES in S11), the check unit 103 causes the cache flush unit 101 to execute cache flush processing (YES in S11, S4). Even if garbage collection is executed, as long as the reference area of the compression / decompression unit 122 is not moved, accurate processing target data can be read without performing cache flush processing. By performing such control, the number of cache flush processes can be further reduced.

  Note that the configurations and processes shown in FIGS. 1 to 4 described as the above embodiments are merely examples, and can be appropriately changed.

  For example, in each of the above embodiments, the control unit 10 performs the PDL analysis unit 100, the cache flash unit 101, the memory management unit 102, the check unit 103 (in the above other embodiments) according to a program stored in a storage device (not shown). The determination unit 106 is also included), but each of these units may be provided as a circuit (hardware) inside or outside the control unit 10.

  Further, in each of the above embodiments, the conversion process from PDL data to the display list is described as being performed by the control unit 10 (CPU). However, the PDL analysis unit 100 is provided in the ASIC, and the PASIC data is converted by the ASIC. You may comprise so that the conversion process to a display list may be performed.

  In each of the above embodiments, the PDL data received from the host computer 2 is once written in the memory 15, and this is described as being read by the PDL analysis unit 100 in the control unit 10 and converted into a display list. The control unit 10 (CPU) may directly receive PDL data from the host computer 2.

  In each of the above embodiments, the present invention has been described as a data processing system. However, the present invention is a data processing program for causing a computer to perform the above-described cache flush control, or a data processing method for performing the above-described cache flush control by a computer. Also holds.

It is a figure which shows schematic structure of the principal part of the data processing system which concerns on this invention. 6 is a flowchart illustrating cache flush control during print data processing. It is a figure which shows schematic structure of the principal part of the data processing system which concerns on other embodiment of this invention. It is a flowchart which shows the cache flush control at the time of the print data processing by the data processing system which concerns on other embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Image forming apparatus 2 Host computer 10 Control part 100 PDL analysis part 101 Cache flash part 102 Memory management part 103 Check part 104 Cache 106 Judgment part 13 Image formation part 15 Memory 12 ASIC
121 Bitmap development unit 122 Compression / decompression unit

Claims (5)

A data processing system for causing an ASIC to execute processing of data written in a storage area in a memory,
Cache flush means for performing cache flush processing for writing data stored in a cache to a storage area in the memory;
Address information notifying means for notifying the ASIC of address information of the storage area in which data is written by the cache flush process;
When the data written in the storage area indicated by the address information obtained from the address information notification means is processed by the ASIC, and the processed data is written to the memory, the memory is stored as necessary. Relocation processing means for performing relocation processing of the area and securing a writable area of the data to be written;
Relocation presence / absence determining means for determining whether or not relocation processing has been performed by the relocation processing means;
When the rearrangement determination unit determines that the rearrangement process has been performed, the cache flush unit performs the cache flush process, and when the rearrangement process has not been performed, the rearrangement presence determination is performed. A data processing system comprising: prohibiting means for prohibiting cache flush processing by the cache flush means when judged by the means. A determination means for determining whether a storage area in the memory in which data to be processed by the ASIC is written is a target of a rearrangement process by the rearrangement processing means;
Even if the prohibition unit determines that the rearrangement process has been performed by the rearrangement presence determination unit, the storage area in which the data to be processed by the ASIC is written The data processing system according to claim 1, wherein when the determination unit determines that it is not a target for relocation processing, cache flush processing by the cache flush unit is prohibited.   The data processing system according to claim 1 or 2, wherein, based on each identifier indicating each of a plurality of tasks, control whether to prohibit the cache flush process by the cache flush unit is performed for each task. A data processing program for causing an ASIC to execute processing of data written in a storage area in a memory,
Cache flush means for performing cache flush processing for writing data stored in a cache to a storage area in the memory;
Address information notifying means for notifying the ASIC of address information of the storage area in which data is written by the cache flush process;
When the data written in the storage area indicated by the address information obtained from the address information notification means is processed by the ASIC, and the processed data is written to the memory, the memory is stored as necessary. Relocation processing means for performing relocation processing of the area and securing a writable area of the data to be written;
Relocation presence / absence determining means for determining whether or not relocation processing has been performed by the relocation processing means;
When the rearrangement determination unit determines that the rearrangement process has been performed, the cache flush unit performs the cache flush process, and when the rearrangement process has not been performed, the rearrangement presence determination is performed. A data processing program that causes a computer to operate so as to include a prohibiting unit that prohibits a cache flush process by the cache flush unit when determined by the unit. A data processing method for causing an ASIC to execute processing of data written in a storage area in a memory,
A step of performing a cache flush process for writing data stored in a cache to a storage area in the memory;
A process of notifying the ASIC of address information of the storage area in which data is written by the cache flush process;
When the data written in the storage area indicated by the notified address information is processed by the ASIC and the processed data is written into the memory, the storage area of the memory is rearranged as necessary. Performing a process and securing a writable area for the data to be written;
A step of determining whether or not the rearrangement process has been performed;
When it is determined that the relocation processing has been performed, the cache flush unit is caused to perform the cache flush processing, and when it is determined that the relocation processing has not been performed, the cache flush processing is prohibited. A data processing method consisting of a process.

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