CN112131156B - Data transmission method, system, electronic equipment and storage medium - Google Patents
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Abstract
The application discloses a data transmission method, a system, an electronic device and a computer readable storage medium, wherein the method comprises the following steps: when any CPU writes data, judging whether the annular output buffer area is locked; if not, locking the annular output buffer area; and writing the character string data to be written into the annular output buffer area after the locking is successful, updating the write pointer in the control register group corresponding to the annular output buffer area after the writing, and synchronously updating the write pointer in the TAP register so that the JTAG equipment reads the updated character string data in the annular output buffer area through the JTAG interface after detecting that the write pointer is updated. According to the method, the character string transmission is carried out through the JTAG interface and the multi-CPU chip, the JTAG interface can be reused, a UART interface is not needed, chip pin resources are saved, the chip area is reduced, the number of evaluation board elements is reduced, and the debugging efficiency is improved.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a data transmission method, a data transmission system, an electronic device, and a computer-readable storage medium.
Background
At present, it is very common to adopt the CPU of ARM company to develop SoC, and the ARM CPU is usually used as the main processor of the system, and a plurality of other CPUs are collocated according to different application scenes to form a complex system on chip. These socs generally implement a debugging function of a chip by using a CoreSight architecture proposed by ARM corporation, and a dap (debug Access port) AHB-AP interface in CoreSight can implement direct Access from JTAG to an on-chip AHB bus, so that JTAG devices can Access on-chip resources connected to the AHB bus in real time, such as RAM, DDR, and the like.
The UART is usually used as a transceiving interface for debugging information in chip debugging, especially in software and hardware combined debugging of a complex SoC. The UART is simple in configuration and stable in work, and can well meet the transmission task of character string information. In order to implement UART transmission, a special UART interface is required to be reserved on the evaluation board or prototype, and is generally composed of a UART-to-USB interface chip and a USB connector. JTAG is a standard test protocol commonly used in the industry, JTAG logic exists in almost all chips, and a JTAG interface is usually used as an interface for chip test and software and hardware combined debugging and is also used as a programming interface of FPGA and CPLD.
JTAG and UART interfaces can be realized on a common chip evaluation board at the same time, wherein the JTAG interface is mainly used for debugging chip hardware, and the UART interface is mainly used for printing log information by software. In a complex SoC, a plurality of CPUs exist, so that a plurality of UART interfaces have to be implemented to output respective log information for different CPUs, but this also increases chip pins, increases area, increases evaluation board devices, and increases cost. In order to save cost, the chip usually does not implement their UARTs for all CPUs, which brings inconvenience to the debugging of the chip.
Therefore, how to solve the above problems is a great concern for those skilled in the art.
Disclosure of Invention
The application aims to provide a data transmission method, a data transmission system, an electronic device and a computer readable storage medium, which save chip pin resources and reduce the number of evaluation board elements.
In order to achieve the above object, the present application provides a data transmission method, including:
when any CPU carries out data writing, whether a preset annular output buffer area is locked or not is judged;
if the annular output buffer area is in an unlocked state, locking the annular output buffer area;
after locking is successful, writing first-class character string data to be written into the annular output buffer area, and updating a first write pointer in a control register group corresponding to the annular output buffer area after writing;
and synchronously updating a second write pointer in the TAP register according to the first write pointer so that the JTAG equipment can read the updated character string data in the ring-shaped output buffer area through a JTAG interface after detecting that the second write pointer is updated.
Optionally, if the ring-shaped output buffer is in an unlocked state, performing a locking operation on the preset ring-shaped output buffer includes:
if the annular output buffer area is in an unlocked state, writing a target identifier corresponding to a CPU currently executing the write operation into a write lock register;
and acquiring a current identifier in the write lock register, and verifying whether the locking operation is successful by comparing whether the current identifier is consistent with the target identifier.
Optionally, after the locking is successful, writing the first type of character string data to be written into the ring-shaped output buffer area, including:
when the locking is successful, acquiring whether the residual free capacity of the annular output buffer area meets the data size of the first type of character string data;
if yes, directly writing the first type character string data into the annular output buffer area;
if not, writing the first type of character string data into the annular output buffer area after finishing reading the data in the annular output buffer area and releasing the memory.
Optionally, after the updating the first write pointer in the control register group corresponding to the ring output buffer after writing, the method further includes:
and unlocking the preset annular output buffer area so as to facilitate other subsequent CPUs to execute writing operation.
Optionally, the reading, by the JTAG device, the updated character string data in the ring output buffer through the JTAG interface after detecting that the second write pointer is updated includes:
when the JTAG equipment detects that the second write pointer is updated, reading updated character string data in the annular output buffer area through a JTAG interface based on a last historical read pointer;
and after the character string data is read, updating a first read pointer in the TAP register, and synchronously updating a second read pointer in a control register group corresponding to the ring-shaped output buffer according to the first read pointer.
Optionally, the method further includes:
after the JTAG equipment writes second type character string data into an input buffer zone corresponding to a target CPU through a JTAG interface, sending an interrupt request to the target CPU to trigger the target CPU to read the character string data;
and after the target CPU finishes reading, carrying out interrupt clearing on interrupt registers in a control register group corresponding to the annular output buffer area.
To achieve the above object, the present application provides a data transmission system, including:
the locking judging module is used for judging whether a preset annular output buffer area is locked or not when any CPU carries out data writing;
the write-in locking module is used for locking the annular output buffer area if the annular output buffer area is in an unlocked state;
the pointer updating module is used for writing the first type of character string data to be written into the annular output buffer area after the locking is successful, and updating a first write pointer in a control register group corresponding to the annular output buffer area after the writing;
and the data reading module is used for synchronously updating a second write pointer in the TAP register according to the first write pointer so that the JTAG equipment can read the updated character string data in the annular output buffer area through a JTAG interface after detecting that the second write pointer is updated.
Optionally, the method further includes:
the interruption triggering module is used for sending an interruption request to the target CPU to trigger the target CPU to read the character string data after the JTAG equipment writes the second type of character string data into the input buffer zone corresponding to the target CPU through the JTAG interface;
and the interrupt clearing module is used for carrying out interrupt clearing on interrupt registers in the control register group corresponding to the input buffer area after the target CPU finishes reading.
To achieve the above object, the present application provides an electronic device including:
a memory for storing a computer program;
a processor for implementing the steps of any of the data transmission methods disclosed above when executing the computer program.
To achieve the above object, the present application provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of any of the data transmission methods disclosed in the foregoing.
According to the scheme, the data transmission method provided by the application comprises the following steps: when any CPU carries out data writing, whether a preset annular output buffer area is locked or not is judged; if the annular output buffer area is in an unlocked state, locking the annular output buffer area; after locking is successful, writing first-class character string data to be written into the annular output buffer area, and updating a first write pointer in a control register group corresponding to the annular output buffer area after writing; and synchronously updating a second write pointer in the TAP register according to the first write pointer so that the JTAG equipment can read the updated character string data in the ring-shaped output buffer area through a JTAG interface after detecting that the second write pointer is updated. Therefore, the shared annular output buffer area is provided for the multiple CPUs, the write-in lock function is provided, and when the CPUs need to write data, the annular output buffer area needs to be locked first, so that write-in conflict is avoided; after the write pointer in the control register group corresponding to the ring output buffer is updated, the write pointer in the TAP register is updated synchronously, so that the handshaking between the JTAG equipment and the CPU can be completed without increasing the handshaking signal between the JTAG equipment and the CPU. In addition, the JTAG interface can be reused by carrying out character string transmission with the multi-CPU chip, a UART interface is not required to be utilized, chip pin resources are saved, the chip area is reduced, the number of evaluation board elements is reduced, and the debugging efficiency is improved.
The application also discloses a data transmission system, an electronic device and a computer readable storage medium, which can also realize the technical effects.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a flowchart of a data transmission method disclosed in an embodiment of the present application;
FIG. 2 is a schematic diagram illustrating a connection relationship between a TAP controller and a DAP according to an embodiment of the present application;
fig. 3 is a schematic overall structure diagram of a data transmission scheme disclosed in an embodiment of the present application;
FIG. 4 is a diagram illustrating a specific buffer data storage format according to an embodiment of the present disclosure;
FIG. 5 is a diagram illustrating ring output buffer sharing according to an embodiment of the present disclosure;
FIG. 6 is a schematic diagram illustrating a locking and unlocking process of an output buffer according to an embodiment of the present disclosure;
FIG. 7 is a schematic diagram of processing logic during multi-CPU contention write disclosed in the embodiments of the present application;
FIG. 8 is a flow chart of a specific data output disclosed in the embodiments of the present application;
fig. 9 is a flowchart of another data transmission method disclosed in the embodiments of the present application;
FIG. 10 is a schematic diagram of a specific data input process disclosed in an embodiment of the present application;
FIG. 11 is a flow chart illustrating interrupt triggering and interrupt clearing disclosed in an embodiment of the present application;
fig. 12 is a block diagram of a data transmission system disclosed in an embodiment of the present application;
fig. 13 is a block diagram of an electronic device disclosed in an embodiment of the present application;
fig. 14 is a block diagram of another electronic device disclosed in the embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
JTAG and UART interfaces can be realized on a traditional chip evaluation board at the same time, wherein the JTAG interface is mainly used for debugging chip hardware, and the UART interface is mainly used for printing log information by software. In a complex SoC, a plurality of CPUs exist, so that a plurality of UART interfaces have to be implemented to output respective log information for different CPUs, but this also increases chip pins, increases area, increases evaluation board devices, and increases cost. In order to save cost, the chip usually does not implement their UARTs for all CPUs, which brings inconvenience to the debugging of the chip.
Therefore, the embodiment of the application discloses a data transmission method, which saves chip pin resources, reduces the chip area, reduces the number of evaluation board elements and improves the debugging efficiency.
Referring to fig. 1, a data transmission method disclosed in the embodiment of the present application includes:
s101: when any CPU carries out data writing, whether a preset annular output buffer area is locked or not is judged;
in the embodiment of the application, the general memory space in the chip can be used as the preset output buffer area for sharing by a plurality of CPUs in the chip, and the address and the length of the buffer area are both agreed in advance by software. In a preferred embodiment, the output buffer can be set as a ring output buffer, which can save resources and improve the utilization rate of the buffer.
Specifically, when any CPU needs to write data, it is first determined whether the ring output buffer is in a locked state. In a specific implementation, a write lock register may be set in the ring output buffer, and when the value of the write lock register is zero, it indicates that the ring output buffer is in an unlocked state, and a lock or read operation may be performed on the ring output buffer. When the value of the write lock register is nonzero, the ring output buffer is represented to be in a locked state, other CPUs in the chip can only read the ring output buffer, and the write operation is ignored. Thus, it is possible to determine whether the ring output buffer is locked by determining whether the value written into the lock register is zero.
S102: if the annular output buffer area is in an unlocked state, locking the annular output buffer area;
in this step, if it is determined that the ring output buffer is in an unlocked state, the current CPU may lock the ring output buffer. Specifically, the target identifier corresponding to the CPU currently performing the write operation may be written to the write lock register to lock the ring output buffer.
After the ring output buffer is locked, it is further verified whether the locking is successful. As a possible implementation manner, the embodiment of the present application may obtain a current identifier in the write lock register, and verify whether the locking operation is successful by comparing whether the current identifier is consistent with a target identifier corresponding to a CPU currently executing the write operation.
S103: after locking is successful, writing first-class character string data to be written into the annular output buffer area, and updating a first write pointer in a control register group corresponding to the annular output buffer area after writing;
it can be understood that, after the ring output buffer is successfully locked, the current CPU can write the first type of string data to be written into the ring output buffer. And after the writing is finished, updating a first writing pointer in a control register group corresponding to the ring-shaped output buffer. The write pointer points to the tail address of the new data in the output buffer area, and the control register group is a register group which can be accessed by the CPU.
The writing of the first type of character string data to be written into the ring-shaped output buffer after the locking is successful may specifically include: when the locking is successful, acquiring whether the residual free capacity of the annular output buffer area meets the data size of the first type of character string data; if yes, directly writing the first type of character string data into the annular output buffer area; and if not, writing the first type of character string data into the annular output buffer area after finishing reading the data in the annular output buffer area and releasing the memory.
After the first type of character string data is written into the preset ring output buffer area or after the corresponding write pointer is updated, the current CPU can perform unlocking operation on the preset ring output buffer area so that other subsequent CPUs can perform writing operation. Specifically, the current CPU may write a value of zero into the write lock release register to modify the value written into the write lock register to zero, thereby releasing the buffer lock.
S104: and synchronously updating a second write pointer in the TAP register according to the first write pointer so that the JTAG equipment can read the updated character string data in the ring-shaped output buffer area through a JTAG interface after detecting that the second write pointer is updated.
In this step, after the first write pointer in the control register group corresponding to the ring output buffer is updated, the second write pointer in the TAP register is immediately and synchronously updated. The TAP register is a register accessible to JTAG devices. When the JTAG device detects that the second write pointer is updated, new data to be read in the representation buffer area exists, and at the moment, the updated character string data in the annular output buffer area can be read through the JTAG interface based on the last historical read pointer.
It is understood that after the JTAG device finishes reading the character string data, the first read pointer in the TAP register may be updated, and the second read pointer in the control register set corresponding to the ring output buffer may be updated synchronously according to the first read pointer. Wherein the read pointer points to the start address of the new data in the output buffer.
According to the scheme, the data transmission method provided by the application comprises the following steps: when any CPU carries out data writing, whether a preset annular output buffer area is locked or not is judged; if the annular output buffer area is in an unlocked state, locking the annular output buffer area; after locking is successful, writing first-class character string data to be written into the annular output buffer area, and updating a first write pointer in a control register group corresponding to the annular output buffer area after writing; and synchronously updating a second write pointer in the TAP register according to the first write pointer so that the JTAG equipment can read the updated character string data in the ring-shaped output buffer area through a JTAG interface after detecting that the second write pointer is updated. Therefore, the shared annular output buffer area is provided for the multiple CPUs, the write-in lock function is provided, and when the CPUs need to write data, the annular output buffer area needs to be locked first, so that write-in conflict is avoided; after the write pointer in the control register group corresponding to the ring output buffer is updated, the write pointer in the TAP register is updated synchronously, so that the handshaking between the JTAG equipment and the CPU can be completed without increasing the handshaking signal between the JTAG equipment and the CPU. In addition, the JTAG interface can be reused by carrying out character string transmission with the multi-CPU chip, a UART interface is not required to be utilized, chip pin resources are saved, the chip area is reduced, the number of evaluation board elements is reduced, and the debugging efficiency is improved.
The following first introduces the infrastructure provided by the embodiments of the present application. Specifically, in the embodiment of the present application, an output buffer and an input buffer are used for exchanging string data, and a hardware module is designed for managing the input buffer, a read-write pointer of the output buffer, and performing interrupt control with a CPU, where the hardware module may include: a custom TAP controller comprising the following extension registers: a plurality of self-defined buffer control register groups and interrupt control register groups; control registers accessible to the respective CPUs: an output buffer control register set and an input buffer control register set. A transfer control unit is also provided that enables mutual synchronization between custom extension registers in the TAP controller and control registers accessible to the CPU.
Referring to fig. 2, the TAP controller and DAP may be connected using a JTAG Daisy-Chain (Daisy Chain) approach, following the IEEE1149.1 protocol. The JTAG device is connected to the JTAG interface of the chip, and thus can access the TAP controller and DAP in the chip respectively.
As shown in fig. 3, in the embodiment of the present application, an input buffer and an output buffer are specifically used to perform character string data exchange between the multiple CPUs and the JTAG device. The input and output buffers utilize the general memory space in the chip, and the address and length are predetermined by software. Referring to fig. 4, data from the CPU will be stored in the buffer in the format of fig. 4, where the first 32-bit word is always a fixed header, whose 16 higher bits are the CPU identifier, and each CPU has a unique 16-bit number as the identifier; the lower 16 bits represent the effective data length in bytes. The data head is followed by valid data, the valid data is always aligned with 4 bytes, the part which is less than 4 bytes after the end of the valid data is ignored by hardware.
Based on the above design framework, a specific data output flow provided by the embodiment of the present application is described below. First, in the embodiment of the present application, a set of buffer control registers accessible by each CPU and a set of TAP registers accessible by JTAG devices are designed. The two sets of registers are used for controlling the output buffer area, specifically, after the initial address and the length of the buffer area are agreed in the software layer, in the chip starting stage, the chip starting code is respectively written into the initial address register of the buffer area of the output buffer area control register group and the length register of the buffer area of the output buffer area control register group, and then the two values are immediately synchronized to the corresponding registers in the user-defined TAP register group by the transmission control module.
It is noted that the read pointer points to the start address of the new data in the output buffer. After the JTAG equipment finishes reading data, the 'read pointer' register in the user-defined TAP register group is immediately updated, and the value of the 'read pointer' register in the output buffer area control register group is immediately synchronized by the transmission control module. The write pointer points to the tail address of the new data in the output buffer. After finishing writing data into the output buffer area, the CPU immediately updates a 'write pointer' register in the control register group of the output buffer area, and the value of the 'write pointer' register is immediately synchronized to a 'write pointer' register in the self-defined TAP register group by the transmission control module.
In the embodiment of the application, a write-in lock register is further designed, when the reset value of the register is 0, the register is not locked, and the CPU in the chip in the state can write in the register and write the identifier of the CPU into the register so as to apply for writing in the output buffer area. The CPU must then read back the value of this register to determine if the lock is complete, and only when the value of the CPU identifier is read back will the lock be successful and the write to the output buffer can begin. When the value of the write lock register is non-zero, all CPUs in the chip can only read the write lock register, and the write operation is ignored. After the CPU completes writing, the write lock can be released, and the lock of the output buffer can be released.
It is understood that the output buffer is used for the CPU to externally output the character string data. In the embodiment of the present application, multiple CPUs share one ring output buffer, as shown in fig. 5. The base address and length of the output buffer area can be configured, after the software is defined, the starting code of the chip is written into the output buffer area base address register and the output buffer area length register in the output buffer control register group, and only needs to be configured once. The transmission control module will then automatically update the start address register and the length register in the TAP, and the JTAG device will know the base address and the length of the output buffer by reading these two registers in the TAP.
In a specific implementation, only one CPU is allowed to write into the output buffer at a time, each CPU needs to lock the output buffer by the "write lock" register before writing and unlock the output buffer by the "write lock release" register after writing is completed, and a specific flow may refer to fig. 6. The write-lock register is a WORM (write-once read-many) register, and after the write-lock register is reset, only the first write operation is allowed, and all subsequent write operations are ignored by hardware, but the read is not limited. The write lock release register is used to initiate a reset to the write lock register, and when the CPU writes 0 to the write lock release register, the write lock register is reset and its value is restored to 0. Therefore, the competition risk when multiple CPUs compete for writing in the write lock can be solved. FIG. 7 shows the processing logic when multiple CPUs are competing to write to the write lock register.
Fig. 8 is a specific data output flowchart according to an embodiment of the present application. As shown in fig. 8, the JTAG device and the on-chip CPU commonly maintain the read/write pointer of the buffer, and poll and calculate the read/write pointer to know whether there is data to be read in the output buffer and whether there is a writable space. A write pointer, indicating the end location of the new data, which is updated by the CPU, is read by the JTAG device. After the CPU finishes writing in the output buffer, the write pointer register in the output buffer control register group is updated immediately, and then the value is synchronously updated to the write pointer register in the TAP by the transmission control module. And the read pointer specifically represents the initial position of new data, is updated by the JTAG equipment and is read by the CPU. After the JTAG device finishes reading the data in the output buffer area, the 'read pointer' register in the TAP is immediately updated, and then the value is synchronously updated to the 'read pointer' register in the output buffer area control register group by the transmission control module.
Therefore, the embodiment of the application provides a method and hardware design for completing data transceiving between a JTAG interface and a multi-CPU chip, so that chip pins are not increased, and the chip packaging area is saved; the universal storage space in the chip is used for exchanging data, and a special cache is not required to be additionally added, so that the design area of the chip is saved; extra connecting interfaces and cables are not added, so that the device cost of the chip evaluation board and the area of the PCB are reduced; in addition, different CPUs in the chip can input and output character string data externally, and great convenience is brought to multi-core software debugging of a complex chip.
The embodiment of the application discloses another data transmission method, and compared with the previous embodiment, the embodiment further explains and optimizes the technical scheme aiming at the data input direction. Referring to fig. 9, specifically:
s201: when JTAG equipment writes second type character string data into an input buffer zone corresponding to a target CPU through a JTAG interface, sending an interrupt request to the target CPU to trigger the target CPU to read the character string data;
in the embodiment of the application, the JTAG device may write data to the input buffer through the JTAG interface. The input buffer area can directly utilize the general memory space in the chip, and the address and the length of the input buffer area are both appointed in advance by software.
Specifically, the embodiment of the present application may provide an independent input buffer for each CPU, and the JTAG device may directly write the second type of character string data into the input buffer corresponding to the target CPU. After the data is written, an interrupt request can be sent to the target CPU to trigger the target CPU to read the character string data in the corresponding input buffer.
S202: and after the target CPU finishes reading, carrying out interrupt clearing on an interrupt register in a control register group corresponding to the input buffer area.
It will be appreciated that when the target CPU read is complete, the interrupt register in the control register set corresponding to the input buffer may be cleared of the corresponding interrupt to inform the JTAG device that data has been taken.
Fig. 10 is a schematic diagram of a specific data input process according to an embodiment of the present application. As shown in FIG. 10, the input buffer is used for the CPU to receive the character string data sent from the outside, each CPU has its own independent input buffer, the base address of each CPU is predetermined by software, and the size of each CPU is 1 KB. After the JTAG device writes the input character string data into the input buffer area corresponding to the CPU, the interruption is triggered by an 'interruption request' register in the TAP, and the CPU is informed to fetch the data. After the CPU finishes fetching, the interrupt is cleared through the "interrupt clear" register in the output buffer control register set, as shown in FIG. 11. In the embodiment of the present application, the interrupt control register may be embodied as 32 bits, which may allow the JTAG device to input character string data to 32 different CPUs, respectively. By extending the bit width of the interrupt control register, a greater number of CPUs can be supported.
In particular, this embodiment contemplates a set of input buffer interrupt control registers that are accessible by the respective CPU, and a set of TAP registers that are accessible by the JTAG device. These two sets of registers are used for interrupt control of the input buffer, where each bit corresponds to a different CPU within the chip. Specifically, the JTAG device writes to an "interrupt request" register in the TAP to request an interrupt. The value of the interrupt request register is then synchronized by the transmission control module to an interrupt trigger register in the input buffer interrupt control register set, which completes the interrupt trigger to the CPU. After the JTAG device writes to the "interrupt request" register in the TAP, the "interrupt status" register value in the TAP is updated accordingly. After the CPU finishes fetching the data from the input buffer area, the CPU writes the data into an interrupt clear register in an interrupt control register group of the input buffer area to clear the interrupt, and then the transmission control module updates an interrupt state register in the TAP. The JTAG device inquires the interrupt state register to see whether the CPU finishes the last fetch and determines whether the next data input can be started.
In the following, a data transmission system provided by an embodiment of the present application is introduced, and a data transmission system described below and a data transmission method described above may be referred to each other.
Referring to fig. 12, a data transmission system provided in an embodiment of the present application includes:
a locking judgment module 301, configured to judge whether a preset ring output buffer is locked when any CPU performs data writing;
a write lock module 302, configured to lock the ring output buffer if the ring output buffer is in an unlocked state;
the pointer updating module 303 is configured to, after locking is successful, write first-class string data to be written into the ring-shaped output buffer, and update a first write pointer in a control register group corresponding to the ring-shaped output buffer after writing;
and the data reading module 304 is configured to synchronously update the second write pointer in the TAP register according to the first write pointer, so that the JTAG device reads the updated character string data in the ring output buffer through the JTAG interface after detecting that the second write pointer is updated.
For the specific implementation process of the modules 301 to 304, reference may be made to the corresponding content disclosed in the foregoing embodiments, and details are not repeated here.
On the basis of the foregoing embodiment, as a preferred implementation, the data transmission system provided in the embodiment of the present application may further include:
the interruption triggering module is used for sending an interruption request to the target CPU to trigger the target CPU to read the character string data after the JTAG equipment writes the second type of character string data into the input buffer zone corresponding to the target CPU through the JTAG interface;
and the interrupt clearing module is used for carrying out interrupt clearing on interrupt registers in the control register group corresponding to the annular output buffer area after the target CPU finishes reading.
The present application further provides an electronic device, and as shown in fig. 13, an electronic device provided in an embodiment of the present application includes:
a memory 100 for storing a computer program;
the processor 200, when executing the computer program, may implement the steps provided by the above embodiments.
Specifically, the memory 100 includes a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and computer-readable instructions, and the internal memory provides an environment for the operating system and the computer-readable instructions in the non-volatile storage medium to run. The processor 200 may be a Central Processing Unit (CPU), a controller, a microcontroller, a microprocessor or other data Processing chip in some embodiments, and provides computing and controlling capability for the electronic device, and when executing the computer program stored in the memory 100, the data transmission method disclosed in any of the foregoing embodiments may be implemented.
On the basis of the above embodiment, as a preferred implementation, referring to fig. 14, the electronic device further includes:
and an input interface 300 connected to the processor 200, for acquiring computer programs, parameters and instructions imported from the outside, and storing the computer programs, parameters and instructions into the memory 100 under the control of the processor 200. The input interface 300 may be connected to an input device for receiving parameters or instructions manually input by a user. The input device may be a touch layer covered on a display screen, or a button, a track ball or a touch pad arranged on a terminal shell, or a keyboard, a touch pad or a mouse, etc.
And a display unit 400 connected to the processor 200 for displaying data processed by the processor 200 and for displaying a visualized user interface. The display unit 400 may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, an OLED (Organic Light-Emitting Diode) touch panel, or the like.
And a network port 500 connected to the processor 200 for performing communication connection with each external terminal device. The communication technology adopted by the communication connection can be a wired communication technology or a wireless communication technology, such as a mobile high definition link (MHL) technology, a Universal Serial Bus (USB), a High Definition Multimedia Interface (HDMI), a wireless fidelity (WiFi), a bluetooth communication technology, a low power consumption bluetooth communication technology, an ieee802.11 s-based communication technology, and the like.
While FIG. 14 shows only an electronic device having the assembly 100 and 500, those skilled in the art will appreciate that the configuration shown in FIG. 14 is not intended to be limiting of electronic devices and may include fewer or more components than those shown, or some components may be combined, or a different arrangement of components.
The present application also provides a computer-readable storage medium, which may include: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk. The storage medium has stored thereon a computer program which, when executed by a processor, implements the data transmission method disclosed in any of the foregoing embodiments.
The method provides a sharable annular output buffer area for the multiple CPUs, provides a write-in lock function, and needs to lock the annular output buffer area first when the CPUs need to write data, so as to avoid write-in conflict; after the write pointer in the control register group corresponding to the ring output buffer is updated, the write pointer in the TAP register is updated synchronously, so that the handshaking between the JTAG equipment and the CPU can be completed without increasing the handshaking signal between the JTAG equipment and the CPU. In addition, the JTAG interface can be reused by carrying out character string transmission with the multi-CPU chip, a UART interface is not required to be utilized, chip pin resources are saved, the chip area is reduced, the number of evaluation board elements is reduced, and the debugging efficiency is improved.
The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Claims (10)
1. A method of data transmission, comprising:
when any CPU carries out data writing, whether a preset annular output buffer area is locked or not is judged;
if the annular output buffer area is in an unlocked state, locking the annular output buffer area;
after locking is successful, writing first-class character string data to be written into the annular output buffer area, and updating a first write pointer in a control register group corresponding to the annular output buffer area after writing;
and synchronously updating a second write pointer in the TAP register according to the first write pointer so that the JTAG equipment can read the updated character string data in the ring-shaped output buffer area through a JTAG interface after detecting that the second write pointer is updated.
2. The data transmission method according to claim 1, wherein if the ring output buffer is in an unlocked state, performing a locking operation on the preset ring output buffer comprises:
if the annular output buffer area is in an unlocked state, writing a target identifier corresponding to a CPU currently executing the write operation into a write lock register;
and acquiring a current identifier in the write lock register, and verifying whether the locking operation is successful by comparing whether the current identifier is consistent with the target identifier.
3. The data transmission method according to claim 1, wherein writing the first type string data to be written into the ring output buffer after the locking is successful comprises:
when the locking is successful, acquiring whether the residual free capacity of the annular output buffer area meets the data size of the first type of character string data;
if yes, directly writing the first type character string data into the annular output buffer area;
if not, writing the first type of character string data into the annular output buffer area after finishing reading the data in the annular output buffer area and releasing the memory.
4. The data transmission method according to claim 1, wherein after the updating the first write pointer in the control register group corresponding to the ring output buffer after writing, the method further comprises:
and unlocking the preset annular output buffer area so as to facilitate other subsequent CPUs to execute writing operation.
5. The data transmission method according to any one of claims 1 to 4, wherein the JTAG device detects that the updated character string data in the ring output buffer is read through a JTAG interface after the second write pointer is updated, and includes:
when the JTAG equipment detects that the second write pointer is updated, reading updated character string data in the annular output buffer area through a JTAG interface based on a last historical read pointer;
and after the character string data is read, updating a first read pointer in the TAP register, and synchronously updating a second read pointer in a control register group corresponding to the ring-shaped output buffer according to the first read pointer.
6. The data transmission method according to claim 5, further comprising:
after the JTAG equipment writes second type character string data into an input buffer zone corresponding to a target CPU through a JTAG interface, sending an interrupt request to the target CPU to trigger the target CPU to read the character string data;
and after the target CPU finishes reading, carrying out interrupt clearing on interrupt registers in a control register group corresponding to the annular output buffer area.
7. A data transmission system, comprising:
the locking judging module is used for judging whether a preset annular output buffer area is locked or not when any CPU carries out data writing;
the write-in locking module is used for locking the annular output buffer area if the annular output buffer area is in an unlocked state;
the pointer updating module is used for writing the first type of character string data to be written into the annular output buffer area after the locking is successful, and updating a first write pointer in a control register group corresponding to the annular output buffer area after the writing;
and the data reading module is used for synchronously updating a second write pointer in the TAP register according to the first write pointer so that the JTAG equipment can read the updated character string data in the annular output buffer area through a JTAG interface after detecting that the second write pointer is updated.
8. The data transmission system of claim 7, further comprising:
the interruption triggering module is used for sending an interruption request to the target CPU to trigger the target CPU to read the character string data after the JTAG equipment writes the second type of character string data into the input buffer zone corresponding to the target CPU through the JTAG interface;
and the interrupt clearing module is used for carrying out interrupt clearing on interrupt registers in the control register group corresponding to the input buffer area after the target CPU finishes reading.
9. An electronic device, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the data transmission method according to any one of claims 1 to 6 when executing the computer program.
10. A computer-readable storage medium, characterized in that a computer program is stored on the computer-readable storage medium, which computer program, when being executed by a processor, carries out the steps of the data transmission method according to one of claims 1 to 6.
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| CN114340097B (en) * | 2021-12-30 | 2024-07-30 | 合肥市芯海电子科技有限公司 | Method and device for controlling lamp strip, chip and electronic equipment |
| CN114691595B (en) * | 2022-04-06 | 2023-03-28 | 北京百度网讯科技有限公司 | Multi-core circuit, data exchange method, electronic device, and storage medium |
| CN115037798B (en) * | 2022-08-11 | 2022-12-27 | 成都金诺信高科技有限公司 | Time system message data packet distribution method |
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